drivers/fpga/socfpga_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  */
   5 #include <image.h>
   6 #include <log.h>
   7 #include <asm/global_data.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/fpga_manager.h>
  10 #include <asm/arch/reset_manager.h>
  11 #include <asm/arch/system_manager.h>
  12 #include <asm/arch/sdram.h>
  13 #include <asm/arch/misc.h>
  14 #include <altera.h>
  15 #include <asm/arch/pinmux.h>
  16 #include <common.h>
  17 #include <dm.h>
  18 #include <dm/ofnode.h>
  19 #include <errno.h>
  20 #include <fs_loader.h>
  21 #include <wait_bit.h>
  22 #include <watchdog.h>
  23 #include <linux/bitops.h>
  24 #include <linux/delay.h>
  25
  26 #define CFGWDTH_32      1
  27 #define MIN_BITSTREAM_SIZECHECK 230
  28 #define ENCRYPTION_OFFSET       69
  29 #define COMPRESSION_OFFSET      229
  30 #define FPGA_TIMEOUT_MSEC       1000  /* timeout in ms */
  31 #define FPGA_TIMEOUT_CNT        0x1000000
  32 #define DEFAULT_DDR_LOAD_ADDRESS        0x400
  33 #define DDR_BUFFER_SIZE         0x100000
  34
  35 /* When reading bitstream from a filesystem, the size of the first read is
  36  * changed so that the subsequent reads are aligned to this value. This value
  37  * was chosen so that in subsequent reads the fat fs driver doesn't have to
  38  * allocate a temporary buffer in get_contents (assuming 8KiB clusters).
  39  */
  40 #define MAX_FIRST_LOAD_SIZE     0x2000
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 static const struct socfpga_fpga_manager *fpga_manager_base =
  45                 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
  46
  47 static void fpgamgr_set_cd_ratio(unsigned long ratio);
  48
  49 static uint32_t fpgamgr_get_msel(void)
  50 {
  51         u32 reg;
  52
  53         reg = readl(&fpga_manager_base->imgcfg_stat);
  54         reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
  55                 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
  56
  57         return reg;
  58 }
  59
  60 static void fpgamgr_set_cfgwdth(int width)
  61 {
  62         if (width)
  63                 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  64                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  65         else
  66                 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  67                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  68 }
  69
  70 int is_fpgamgr_user_mode(void)
  71 {
  72         return (readl(&fpga_manager_base->imgcfg_stat) &
  73                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
  74 }
  75
  76 static int wait_for_user_mode(void)
  77 {
  78         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  79                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
  80                 1, FPGA_TIMEOUT_MSEC, false);
  81 }
  82
  83 static int wait_for_fifo_empty(void)
  84 {
  85         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  86                 ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK,
  87                 1, FPGA_TIMEOUT_MSEC, false);
  88 }
  89
  90 int is_fpgamgr_early_user_mode(void)
  91 {
  92         return (readl(&fpga_manager_base->imgcfg_stat) &
  93                 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
  94 }
  95
  96 int fpgamgr_wait_early_user_mode(void)
  97 {
  98         u32 sync_data = 0xffffffff;
  99         u32 i = 0;
 100         unsigned start = get_timer(0);
 101         unsigned long cd_ratio;
 102
 103         /* Getting existing CDRATIO */
 104         cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
 105                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
 106                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
 107
 108         /* Using CDRATIO_X1 for better compatibility */
 109         fpgamgr_set_cd_ratio(CDRATIO_x1);
 110
 111         while (!is_fpgamgr_early_user_mode()) {
 112                 if (get_timer(start) > FPGA_TIMEOUT_MSEC)
 113                         return -ETIMEDOUT;
 114                 fpgamgr_program_write((const long unsigned int *)&sync_data,
 115                                 sizeof(sync_data));
 116                 udelay(FPGA_TIMEOUT_MSEC);
 117                 i++;
 118         }
 119
 120         debug("FPGA: Additional %i sync word needed\n", i);
 121
 122         /* restoring original CDRATIO */
 123         fpgamgr_set_cd_ratio(cd_ratio);
 124
 125         return 0;
 126 }
 127
 128 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
 129 static int wait_for_nconfig_pin_and_nstatus_pin(void)
 130 {
 131         unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
 132                                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 133
 134         /*
 135          * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
 136          * de-asserted, timeout at 1000ms
 137          */
 138         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
 139                                  true, FPGA_TIMEOUT_MSEC, false);
 140 }
 141
 142 static int wait_for_f2s_nstatus_pin(unsigned long value)
 143 {
 144         /* Poll until f2s to specific value, timeout at 1000ms */
 145         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
 146                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
 147                 value, FPGA_TIMEOUT_MSEC, false);
 148 }
 149
 150 /* set CD ratio */
 151 static void fpgamgr_set_cd_ratio(unsigned long ratio)
 152 {
 153         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 154                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 155
 156         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 157                 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
 158                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 159 }
 160
 161 /* get the MSEL value, verify we are set for FPP configuration mode */
 162 static int fpgamgr_verify_msel(void)
 163 {
 164         u32 msel = fpgamgr_get_msel();
 165
 166         if (msel & ~BIT(0)) {
 167                 printf("Fail: read msel=%d\n", msel);
 168                 return -EPERM;
 169         }
 170
 171         return 0;
 172 }
 173
 174 /*
 175  * Write cdratio and cdwidth based on whether the bitstream is compressed
 176  * and/or encoded
 177  */
 178 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
 179                                        size_t rbf_size)
 180 {
 181         unsigned int cd_ratio;
 182         bool encrypt, compress;
 183
 184         /*
 185          * According to the bitstream specification,
 186          * both encryption and compression status are
 187          * in location before offset 230 of the buffer.
 188          */
 189         if (rbf_size < MIN_BITSTREAM_SIZECHECK)
 190                 return -EINVAL;
 191
 192         encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
 193         encrypt = encrypt != 0;
 194
 195         compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
 196         compress = !compress;
 197
 198         debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
 199         debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
 200         debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
 201              compress);
 202
 203         /*
 204          * from the register map description of cdratio in imgcfg_ctrl_02:
 205          *  Normal Configuration    : 32bit Passive Parallel
 206          *  Partial Reconfiguration : 16bit Passive Parallel
 207          */
 208
 209         /*
 210          * cd ratio is dependent on cfg width and whether the bitstream
 211          * is encrypted and/or compressed.
 212          *
 213          * | width | encr. | compr. | cd ratio |
 214          * |  16   |   0   |   0    |     1    |
 215          * |  16   |   0   |   1    |     4    |
 216          * |  16   |   1   |   0    |     2    |
 217          * |  16   |   1   |   1    |     4    |
 218          * |  32   |   0   |   0    |     1    |
 219          * |  32   |   0   |   1    |     8    |
 220          * |  32   |   1   |   0    |     4    |
 221          * |  32   |   1   |   1    |     8    |
 222          */
 223         if (!compress && !encrypt) {
 224                 cd_ratio = CDRATIO_x1;
 225         } else {
 226                 if (compress)
 227                         cd_ratio = CDRATIO_x4;
 228                 else
 229                         cd_ratio = CDRATIO_x2;
 230
 231                 /* if 32 bit, double the cd ratio (so register
 232                    field setting is incremented) */
 233                 if (cfg_width == CFGWDTH_32)
 234                         cd_ratio += 1;
 235         }
 236
 237         fpgamgr_set_cfgwdth(cfg_width);
 238         fpgamgr_set_cd_ratio(cd_ratio);
 239
 240         return 0;
 241 }
 242
 243 static int fpgamgr_reset(void)
 244 {
 245         unsigned long reg;
 246
 247         /* S2F_NCONFIG = 0 */
 248         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 249                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 250
 251         /* Wait for f2s_nstatus == 0 */
 252         if (wait_for_f2s_nstatus_pin(0))
 253                 return -ETIME;
 254
 255         /* S2F_NCONFIG = 1 */
 256         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 257                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 258
 259         /* Wait for f2s_nstatus == 1 */
 260         if (wait_for_f2s_nstatus_pin(1))
 261                 return -ETIME;
 262
 263         /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
 264         reg = readl(&fpga_manager_base->imgcfg_stat);
 265         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
 266                 return -EPERM;
 267
 268         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
 269                 return -EPERM;
 270
 271         return 0;
 272 }
 273
 274 /* Start the FPGA programming by initialize the FPGA Manager */
 275 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
 276 {
 277         int ret;
 278
 279         /* Step 1 */
 280         if (fpgamgr_verify_msel())
 281                 return -EPERM;
 282
 283         /* Step 2 */
 284         if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
 285                 return -EPERM;
 286
 287         /*
 288          * Step 3:
 289          * Make sure no other external devices are trying to interfere with
 290          * programming:
 291          */
 292         if (wait_for_nconfig_pin_and_nstatus_pin())
 293                 return -ETIME;
 294
 295         /*
 296          * Step 4:
 297          * Deassert the signal drives from HPS
 298          *
 299          * S2F_NCE = 1
 300          * S2F_PR_REQUEST = 0
 301          * EN_CFG_CTRL = 0
 302          * EN_CFG_DATA = 0
 303          * S2F_NCONFIG = 1
 304          * S2F_NSTATUS_OE = 0
 305          * S2F_CONDONE_OE = 0
 306          */
 307         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 308                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 309
 310         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 311                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
 312
 313         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 314                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 315                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 316
 317         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 318                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 319
 320         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 321                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
 322                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
 323
 324         /*
 325          * Step 5:
 326          * Enable overrides
 327          * S2F_NENABLE_CONFIG = 0
 328          * S2F_NENABLE_NCONFIG = 0
 329          */
 330         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 331                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 332         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 333                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 334
 335         /*
 336          * Disable driving signals that HPS doesn't need to drive.
 337          * S2F_NENABLE_NSTATUS = 1
 338          * S2F_NENABLE_CONDONE = 1
 339          */
 340         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 341                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
 342                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
 343
 344         /*
 345          * Step 6:
 346          * Drive chip select S2F_NCE = 0
 347          */
 348          clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 349                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 350
 351         /* Step 7 */
 352         if (wait_for_nconfig_pin_and_nstatus_pin())
 353                 return -ETIME;
 354
 355         /* Step 8 */
 356         ret = fpgamgr_reset();
 357
 358         if (ret)
 359                 return ret;
 360
 361         /*
 362          * Step 9:
 363          * EN_CFG_CTRL and EN_CFG_DATA = 1
 364          */
 365         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 366                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 367                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 368
 369         return 0;
 370 }
 371
 372 /* Ensure the FPGA entering config done */
 373 static int fpgamgr_program_poll_cd(void)
 374 {
 375         unsigned long reg, i;
 376
 377         for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
 378                 reg = readl(&fpga_manager_base->imgcfg_stat);
 379                 if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
 380                         return 0;
 381
 382                 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
 383                         printf("nstatus == 0 while waiting for condone\n");
 384                         return -EPERM;
 385                 }
 386                 WATCHDOG_RESET();
 387         }
 388
 389         if (i == FPGA_TIMEOUT_CNT)
 390                 return -ETIME;
 391
 392         return 0;
 393 }
 394
 395 /* Ensure the FPGA entering user mode */
 396 static int fpgamgr_program_poll_usermode(void)
 397 {
 398         unsigned long reg;
 399         int ret = 0;
 400
 401         if (fpgamgr_dclkcnt_set(0xf))
 402                 return -ETIME;
 403
 404         ret = wait_for_user_mode();
 405         if (ret < 0) {
 406                 printf("%s: Failed to enter user mode with ", __func__);
 407                 printf("error code %d\n", ret);
 408                 return ret;
 409         }
 410
 411         /*
 412          * Step 14:
 413          * Stop DATA path and Dclk
 414          * EN_CFG_CTRL and EN_CFG_DATA = 0
 415          */
 416         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 417                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 418                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 419
 420         /*
 421          * Step 15:
 422          * Disable overrides
 423          * S2F_NENABLE_CONFIG = 1
 424          * S2F_NENABLE_NCONFIG = 1
 425          */
 426         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 427                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 428         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 429                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 430
 431         /* Disable chip select S2F_NCE = 1 */
 432         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 433                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 434
 435         /*
 436          * Step 16:
 437          * Final check
 438          */
 439         reg = readl(&fpga_manager_base->imgcfg_stat);
 440         if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
 441                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
 442             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
 443                 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
 444             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
 445                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
 446                 return -EPERM;
 447
 448         return 0;
 449 }
 450
 451 int fpgamgr_program_finish(void)
 452 {
 453         /* Ensure the FPGA entering config done */
 454         int status = fpgamgr_program_poll_cd();
 455
 456         if (status) {
 457                 printf("FPGA: Poll CD failed with error code %d\n", status);
 458                 return -EPERM;
 459         }
 460
 461         /* Ensure the FPGA entering user mode */
 462         status = fpgamgr_program_poll_usermode();
 463         if (status) {
 464                 printf("FPGA: Poll usermode failed with error code %d\n",
 465                         status);
 466                 return -EPERM;
 467         }
 468
 469         printf("Full Configuration Succeeded.\n");
 470
 471         return 0;
 472 }
 473
 474 ofnode get_fpga_mgr_ofnode(ofnode from)
 475 {
 476         return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
 477 }
 478
 479 const char *get_fpga_filename(void)
 480 {
 481         const char *fpga_filename = NULL;
 482
 483         ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
 484
 485         if (ofnode_valid(fpgamgr_node))
 486                 fpga_filename = ofnode_read_string(fpgamgr_node,
 487                                                 "altr,bitstream");
 488
 489         return fpga_filename;
 490 }
 491
 492 static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
 493 {
 494         /*
 495          * Magic ID starting at:
 496          * -> 1st dword[15:0] in periph.rbf
 497          * -> 2nd dword[15:0] in core.rbf
 498          * Note: dword == 32 bits
 499          */
 500         u32 word_reading_max = 2;
 501         u32 i;
 502
 503         for (i = 0; i < word_reading_max; i++) {
 504                 if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 505                         rbf->security = unencrypted;
 506                 } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 507                         rbf->security = encrypted;
 508                 } else if (*(buffer + i + 1) ==
 509                                 FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 510                         rbf->security = unencrypted;
 511                 } else if (*(buffer + i + 1) ==
 512                                 FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 513                         rbf->security = encrypted;
 514                 } else {
 515                         rbf->security = invalid;
 516                         continue;
 517                 }
 518
 519                 /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
 520                 if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 521                         rbf->section = periph_section;
 522                         break;
 523                 } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
 524                         rbf->section = core_section;
 525                         break;
 526                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 527                         rbf->section = periph_section;
 528                         break;
 529                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
 530                         rbf->section = core_section;
 531                         break;
 532                 }
 533
 534                 rbf->section = unknown;
 535                 break;
 536
 537                 WATCHDOG_RESET();
 538         }
 539 }
 540
 541 #ifdef CONFIG_FS_LOADER
 542 static int first_loading_rbf_to_buffer(struct udevice *dev,
 543                                 struct fpga_loadfs_info *fpga_loadfs,
 544                                 u32 *buffer, size_t *buffer_bsize,
 545                                 size_t *buffer_bsize_ori)
 546 {
 547         u32 *buffer_p = (u32 *)*buffer;
 548         u32 *loadable = buffer_p;
 549         size_t buffer_size = *buffer_bsize;
 550         size_t fit_size;
 551         int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
 552         const char *fpga_node_name = NULL;
 553         const char *uname = NULL;
 554
 555         /* Load image header into buffer */
 556         ret = request_firmware_into_buf(dev,
 557                                         fpga_loadfs->fpga_fsinfo->filename,
 558                                         buffer_p, sizeof(struct image_header),
 559                                         0);
 560         if (ret < 0) {
 561                 debug("FPGA: Failed to read image header from flash.\n");
 562                 return -ENOENT;
 563         }
 564
 565         if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
 566                 debug("FPGA: No FDT magic was found.\n");
 567                 return -EBADF;
 568         }
 569
 570         fit_size = fdt_totalsize(buffer_p);
 571
 572         if (fit_size > buffer_size) {
 573                 debug("FPGA: FIT image is larger than available buffer.\n");
 574                 debug("Please use FIT external data or increasing buffer.\n");
 575                 return -ENOMEM;
 576         }
 577
 578         /* Load entire FIT into buffer */
 579         ret = request_firmware_into_buf(dev,
 580                                         fpga_loadfs->fpga_fsinfo->filename,
 581                                         buffer_p, fit_size, 0);
 582         if (ret < 0)
 583                 return ret;
 584
 585         ret = fit_check_format(buffer_p, IMAGE_SIZE_INVAL);
 586         if (ret) {
 587                 debug("FPGA: No valid FIT image was found.\n");
 588                 return ret;
 589         }
 590
 591         confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
 592         images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
 593         if (confs_noffset < 0 || images_noffset < 0) {
 594                 debug("FPGA: No Configurations or images nodes were found.\n");
 595                 return -ENOENT;
 596         }
 597
 598         /* Get default configuration unit name from default property */
 599         confs_noffset = fit_conf_get_node(buffer_p, NULL);
 600         if (confs_noffset < 0) {
 601                 debug("FPGA: No default configuration was found in config.\n");
 602                 return -ENOENT;
 603         }
 604
 605         count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
 606                                             FIT_FPGA_PROP);
 607         if (count < 0) {
 608                 debug("FPGA: Invalid configuration format for FPGA node.\n");
 609                 return count;
 610         }
 611         debug("FPGA: FPGA node count: %d\n", count);
 612
 613         for (i = 0; i < count; i++) {
 614                 images_noffset = fit_conf_get_prop_node_index(buffer_p,
 615                                                              confs_noffset,
 616                                                              FIT_FPGA_PROP, i);
 617                 uname = fit_get_name(buffer_p, images_noffset, NULL);
 618                 if (uname) {
 619                         debug("FPGA: %s\n", uname);
 620
 621                         if (strstr(uname, "fpga-periph") &&
 622                                 (!is_fpgamgr_early_user_mode() ||
 623                                 is_fpgamgr_user_mode() ||
 624                                 is_periph_program_force())) {
 625                                 fpga_node_name = uname;
 626                                 printf("FPGA: Start to program ");
 627                                 printf("peripheral/full bitstream ...\n");
 628                                 break;
 629                         } else if (strstr(uname, "fpga-core") &&
 630                                         (is_fpgamgr_early_user_mode() &&
 631                                         !is_fpgamgr_user_mode())) {
 632                                 fpga_node_name = uname;
 633                                 printf("FPGA: Start to program core ");
 634                                 printf("bitstream ...\n");
 635                                 break;
 636                         }
 637                 }
 638                 WATCHDOG_RESET();
 639         }
 640
 641         if (!fpga_node_name) {
 642                 debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
 643                 return 1;
 644         }
 645
 646         images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
 647         if (images_noffset < 0) {
 648                 debug("FPGA: No node '%s' was found in FIT.\n",
 649                      fpga_node_name);
 650                 return -ENOENT;
 651         }
 652
 653         if (!fit_image_get_data_position(buffer_p, images_noffset,
 654                                         &rbf_offset)) {
 655                 debug("FPGA: Data position was found.\n");
 656         } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
 657                   &rbf_offset)) {
 658                 /*
 659                  * For FIT with external data, figure out where
 660                  * the external images start. This is the base
 661                  * for the data-offset properties in each image.
 662                  */
 663                 rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
 664                 debug("FPGA: Data offset was found.\n");
 665         } else {
 666                 debug("FPGA: No data position/offset was found.\n");
 667                 return -ENOENT;
 668         }
 669
 670         ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
 671         if (ret < 0) {
 672                 debug("FPGA: No data size was found (err=%d).\n", ret);
 673                 return -ENOENT;
 674         }
 675
 676         if (gd->ram_size < rbf_size) {
 677                 debug("FPGA: Using default OCRAM buffer and size.\n");
 678         } else {
 679                 ret = fit_image_get_load(buffer_p, images_noffset,
 680                                         (ulong *)loadable);
 681                 if (ret < 0) {
 682                         buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
 683                         debug("FPGA: No loadable was found.\n");
 684                         debug("FPGA: Using default DDR load address: 0x%x .\n",
 685                              DEFAULT_DDR_LOAD_ADDRESS);
 686                 } else {
 687                         buffer_p = (u32 *)*loadable;
 688                         debug("FPGA: Found loadable address = 0x%x.\n",
 689                              *loadable);
 690                 }
 691
 692                 buffer_size = rbf_size;
 693                 *buffer_bsize_ori = DDR_BUFFER_SIZE;
 694         }
 695
 696         debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
 697               rbf_offset, rbf_size);
 698
 699         fpga_loadfs->remaining = rbf_size;
 700
 701         /*
 702          * Determine buffer size vs bitstream size, and calculating number of
 703          * chunk by chunk transfer is required due to smaller buffer size
 704          * compare to bitstream
 705          */
 706
 707         if (buffer_size > MAX_FIRST_LOAD_SIZE)
 708                 buffer_size = MAX_FIRST_LOAD_SIZE;
 709
 710         if (rbf_size <= buffer_size) {
 711                 /* Loading whole bitstream into buffer */
 712                 buffer_size = rbf_size;
 713                 fpga_loadfs->remaining = 0;
 714         } else {
 715                 buffer_size -= rbf_offset % buffer_size;
 716                 fpga_loadfs->remaining -= buffer_size;
 717         }
 718
 719         fpga_loadfs->offset = rbf_offset;
 720         /* Loading bitstream into buffer */
 721         ret = request_firmware_into_buf(dev,
 722                                         fpga_loadfs->fpga_fsinfo->filename,
 723                                         buffer_p, buffer_size,
 724                                         fpga_loadfs->offset);
 725         if (ret < 0) {
 726                 debug("FPGA: Failed to read bitstream from flash.\n");
 727                 return -ENOENT;
 728         }
 729
 730         /* Getting info about bitstream types */
 731         get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
 732
 733         /* Update next reading bitstream offset */
 734         fpga_loadfs->offset += buffer_size;
 735
 736         /* Update the final addr for bitstream */
 737         *buffer = (u32)buffer_p;
 738
 739         /* Update the size of bitstream to be programmed into FPGA */
 740         *buffer_bsize = buffer_size;
 741
 742         return 0;
 743 }
 744
 745 static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
 746                                         struct fpga_loadfs_info *fpga_loadfs,
 747                                         u32 *buffer, size_t *buffer_bsize)
 748 {
 749         int ret = 0;
 750         u32 *buffer_p = (u32 *)*buffer;
 751
 752         /* Read the bitstream chunk by chunk. */
 753         if (fpga_loadfs->remaining > *buffer_bsize) {
 754                 fpga_loadfs->remaining -= *buffer_bsize;
 755         } else {
 756                 *buffer_bsize = fpga_loadfs->remaining;
 757                 fpga_loadfs->remaining = 0;
 758         }
 759
 760         ret = request_firmware_into_buf(dev,
 761                                         fpga_loadfs->fpga_fsinfo->filename,
 762                                         buffer_p, *buffer_bsize,
 763                                         fpga_loadfs->offset);
 764         if (ret < 0) {
 765                 debug("FPGA: Failed to read bitstream from flash.\n");
 766                 return -ENOENT;
 767         }
 768
 769         /* Update next reading bitstream offset */
 770         fpga_loadfs->offset += *buffer_bsize;
 771
 772         return 0;
 773 }
 774
 775 int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 776                         u32 offset)
 777 {
 778         struct fpga_loadfs_info fpga_loadfs;
 779         struct udevice *dev;
 780         int status, ret, size;
 781         u32 buffer = (uintptr_t)buf;
 782         size_t buffer_sizebytes = bsize;
 783         size_t buffer_sizebytes_ori = bsize;
 784         size_t total_sizeof_image = 0;
 785         ofnode node;
 786         const fdt32_t *phandle_p;
 787         u32 phandle;
 788
 789         node = get_fpga_mgr_ofnode(ofnode_null());
 790
 791         if (ofnode_valid(node)) {
 792                 phandle_p = ofnode_get_property(node, "firmware-loader", &size);
 793                 if (!phandle_p) {
 794                         node = ofnode_path("/chosen");
 795                         if (!ofnode_valid(node)) {
 796                                 debug("FPGA: /chosen node was not found.\n");
 797                                 return -ENOENT;
 798                         }
 799
 800                         phandle_p = ofnode_get_property(node, "firmware-loader",
 801                                                        &size);
 802                         if (!phandle_p) {
 803                                 debug("FPGA: firmware-loader property was not");
 804                                 debug(" found.\n");
 805                                 return -ENOENT;
 806                         }
 807                 }
 808         } else {
 809                 debug("FPGA: FPGA manager node was not found.\n");
 810                 return -ENOENT;
 811         }
 812
 813         phandle = fdt32_to_cpu(*phandle_p);
 814         ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
 815                                              phandle, &dev);
 816         if (ret)
 817                 return ret;
 818
 819         memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
 820
 821         fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
 822         fpga_loadfs.offset = offset;
 823
 824         printf("FPGA: Checking FPGA configuration setting ...\n");
 825
 826         /*
 827          * Note: Both buffer and buffer_sizebytes values can be altered by
 828          * function below.
 829          */
 830         ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
 831                                            &buffer_sizebytes,
 832                                            &buffer_sizebytes_ori);
 833         if (ret == 1) {
 834                 printf("FPGA: Skipping configuration ...\n");
 835                 return 0;
 836         } else if (ret) {
 837                 return ret;
 838         }
 839
 840         if (fpga_loadfs.rbfinfo.section == core_section &&
 841                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 842                 debug("FPGA : Must be in Early Release mode to program ");
 843                 debug("core bitstream.\n");
 844                 return -EPERM;
 845         }
 846
 847         /* Disable all signals from HPS peripheral controller to FPGA */
 848         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 849
 850         /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
 851         socfpga_bridges_reset();
 852
 853         if (fpga_loadfs.rbfinfo.section == periph_section) {
 854                 /* Initialize the FPGA Manager */
 855                 status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
 856                 if (status) {
 857                         debug("FPGA: Init with peripheral bitstream failed.\n");
 858                         return -EPERM;
 859                 }
 860         }
 861
 862         /* Transfer bitstream to FPGA Manager */
 863         fpgamgr_program_write((void *)buffer, buffer_sizebytes);
 864
 865         total_sizeof_image += buffer_sizebytes;
 866
 867         while (fpga_loadfs.remaining) {
 868                 ret = subsequent_loading_rbf_to_buffer(dev,
 869                                                         &fpga_loadfs,
 870                                                         &buffer,
 871                                                         &buffer_sizebytes_ori);
 872
 873                 if (ret)
 874                         return ret;
 875
 876                 /* Transfer data to FPGA Manager */
 877                 fpgamgr_program_write((void *)buffer,
 878                                         buffer_sizebytes_ori);
 879
 880                 total_sizeof_image += buffer_sizebytes_ori;
 881
 882                 WATCHDOG_RESET();
 883         }
 884         wait_for_fifo_empty();
 885
 886         if (fpga_loadfs.rbfinfo.section == periph_section) {
 887                 if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
 888                         config_pins(gd->fdt_blob, "shared");
 889                         puts("FPGA: Early Release Succeeded.\n");
 890                 } else {
 891                         debug("FPGA: Failed to see Early Release.\n");
 892                         return -EIO;
 893                 }
 894
 895                 /* For monolithic bitstream */
 896                 if (is_fpgamgr_user_mode()) {
 897                         /* Ensure the FPGA entering config done */
 898                         status = fpgamgr_program_finish();
 899                         if (status)
 900                                 return status;
 901
 902                         config_pins(gd->fdt_blob, "fpga");
 903                         puts("FPGA: Enter user mode.\n");
 904                 }
 905         } else if (fpga_loadfs.rbfinfo.section == core_section) {
 906                 /* Ensure the FPGA entering config done */
 907                 status = fpgamgr_program_finish();
 908                 if (status)
 909                         return status;
 910
 911                 config_pins(gd->fdt_blob, "fpga");
 912                 puts("FPGA: Enter user mode.\n");
 913         } else {
 914                 debug("FPGA: Config Error: Unsupported bitstream type.\n");
 915                 return -ENOEXEC;
 916         }
 917
 918         return (int)total_sizeof_image;
 919 }
 920
 921 void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
 922 {
 923         fpga_fs_info fpga_fsinfo;
 924
 925         fpga_fsinfo.filename = get_fpga_filename();
 926
 927         if (fpga_fsinfo.filename)
 928                 socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
 929 }
 930 #endif
 931
 932 /* This function is used to load the core bitstream from the OCRAM. */
 933 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 934 {
 935         unsigned long status;
 936         struct rbf_info rbfinfo;
 937
 938         memset(&rbfinfo, 0, sizeof(rbfinfo));
 939
 940         /* Disable all signals from hps peripheral controller to fpga */
 941         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 942
 943         /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
 944         socfpga_bridges_reset();
 945
 946         /* Getting info about bitstream types */
 947         get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
 948
 949         if (rbfinfo.section == periph_section) {
 950                 /* Initialize the FPGA Manager */
 951                 status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
 952                 if (status)
 953                         return status;
 954         }
 955
 956         if (rbfinfo.section == core_section &&
 957                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 958                 debug("FPGA : Must be in early release mode to program ");
 959                 debug("core bitstream.\n");
 960                 return -EPERM;
 961         }
 962
 963         /* Write the bitstream to FPGA Manager */
 964         fpgamgr_program_write(rbf_data, rbf_size);
 965
 966         status = fpgamgr_program_finish();
 967         if (status)
 968                 return status;
 969
 970         config_pins(gd->fdt_blob, "fpga");
 971         puts("FPGA: Enter user mode.\n");
 972
 973         return status;
 974 }