1 menu "ARM architecture"
11 select SYS_CACHE_SHIFT_6
12 imply SPL_SEPARATE_BSS
15 bool "Enable support for CRC32 instruction"
16 depends on ARM64 && CC_IS_GCC
19 ARMv8 implements dedicated crc32 instruction for crc32 calculation.
20 This is faster than software crc32 calculation. This instruction may
21 not be present on all ARMv8.0, but is always present on ARMv8.1 and
24 config COUNTER_FREQUENCY
25 int "Timer clock frequency"
26 depends on ARM64 || CPU_V7A
27 default 8000000 if IMX8 || MX7 || MX6UL || MX6ULL
28 default 24000000 if ARCH_SUNXI || ARCH_EXYNOS || ROCKCHIP_RK3128 || \
29 ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
30 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
31 default 100000000 if ARCH_ZYNQMP
32 default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5
35 For platforms with ARMv8-A and ARMv7-A which features a system
36 counter, those platforms needs software to program the counter
37 frequency. Setup time clock frequency for certain platform.
38 0 means no need to configure the system counter frequency.
39 For platforms needs the frequency set in U-Boot with a
40 pre-defined value, should have the macro defined as a non-zero value.
42 config POSITION_INDEPENDENT
43 bool "Generate position-independent pre-relocation code"
44 depends on ARM64 || CPU_V7A
46 U-Boot expects to be linked to a specific hard-coded address, and to
47 be loaded to and run from that address. This option lifts that
48 restriction, thus allowing the code to be loaded to and executed from
49 almost any 4K aligned address. This logic relies on the relocation
50 information that is embedded in the binary to support U-Boot
51 relocating itself to the top-of-RAM later during execution.
53 config INIT_SP_RELATIVE
54 bool "Specify the early stack pointer relative to the .bss section"
56 default n if ARCH_QEMU
57 default y if POSITION_INDEPENDENT
59 U-Boot typically uses a hard-coded value for the stack pointer
60 before relocation. Enable this option to instead calculate the
61 initial SP at run-time. This is useful to avoid hard-coding addresses
62 into U-Boot, so that it can be loaded and executed at arbitrary
63 addresses and thus avoid using arbitrary addresses at runtime.
65 If this option is enabled, the early stack pointer is set to
66 &_bss_start with a offset value added. The offset is specified by
67 SYS_INIT_SP_BSS_OFFSET.
69 config SYS_INIT_SP_BSS_OFFSET
70 int "Early stack offset from the .bss base address"
72 depends on INIT_SP_RELATIVE
75 This option's value is the offset added to &_bss_start in order to
76 calculate the stack pointer. This offset should be large enough so
77 that the early malloc region, global data (gd), and early stack usage
78 do not overlap any appended DTB.
80 config SPL_SYS_NO_VECTOR_TABLE
84 config SPL_USE_SEPARATE_FAULT_HANDLERS
85 bool "Use separate fault handlers instead of a single common one"
86 depends on !SPL_SYS_NO_VECTOR_TABLE && !ARM64 && !CPU_V7M
88 Instead of a common fault handler, generate a separate one for
89 undefined_instruction, software_interrupt, prefetch_abort etc.
90 This is for debugging purposes, when you want to set breakpoints
93 config LINUX_KERNEL_IMAGE_HEADER
97 Place a Linux kernel image header at the start of the U-Boot binary.
98 The format of the header is described in the Linux kernel source at
99 Documentation/arm64/booting.txt. This feature is useful since the
100 image header reports the amount of memory (BSS and similar) that
101 U-Boot needs to use, but which isn't part of the binary.
103 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
104 depends on LINUX_KERNEL_IMAGE_HEADER
107 The value subtracted from CONFIG_TEXT_BASE to calculate the
108 TEXT_OFFSET value written to the Linux kernel image header.
120 ARM GICV3 Interrupt translation service (ITS).
121 Basic support for programming locality specific peripheral
122 interrupts (LPI) configuration tables and enable LPI tables.
123 LPI configuration table can be used by u-boot or Linux.
124 ARM GICV3 has limitation, once the LPI table is enabled, LPI
125 configuration table can not be re-programmed, unless GICV3 reset.
127 config GICV3_SUPPORT_GIC600
128 bool "ARM GICV3 GIC600 SUPPORT"
130 ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
131 implements a power control register in the Redistributor frame.This
132 register must be programmed to mark the frame as powered on, before
133 accessing other registers in the frame. Rest of initialization sequence
140 config DMA_ADDR_T_64BIT
150 config GPIO_EXTRA_HEADER
153 # Used for compatibility with asm files copied from the kernel
154 config ARM_ASM_UNIFIED
158 # Used for compatibility with asm files copied from the kernel
162 config SYS_ICACHE_OFF
163 bool "Do not enable icache"
165 Do not enable instruction cache in U-Boot.
167 config SPL_SYS_ICACHE_OFF
168 bool "Do not enable icache in SPL"
170 default SYS_ICACHE_OFF
172 Do not enable instruction cache in SPL.
174 config SYS_DCACHE_OFF
175 bool "Do not enable dcache"
177 Do not enable data cache in U-Boot.
179 config SPL_SYS_DCACHE_OFF
180 bool "Do not enable dcache in SPL"
182 default SYS_DCACHE_OFF
184 Do not enable data cache in SPL.
186 config SYS_ARM_CACHE_CP15
187 bool "CP15 based cache enabling support"
189 Select this if your processor suports enabling caches by using
193 bool "MMU-based Paged Memory Management Support"
194 select SYS_ARM_CACHE_CP15
196 Select if you want MMU-based virtualised addressing space
197 support via paged memory management.
200 bool 'Use the ARM v7 PMSA Compliant MPU'
202 Some ARM systems without an MMU have instead a Memory Protection
203 Unit (MPU) that defines the type and permissions for regions of
205 If your CPU has an MPU then you should choose 'y' here unless you
206 know that you do not want to use the MPU.
208 # If set, the workarounds for these ARM errata are applied early during U-Boot
209 # startup. Note that in general these options force the workarounds to be
210 # applied; no CPU-type/version detection exists, unlike the similar options in
211 # the Linux kernel. Do not set these options unless they apply! Also note that
212 # the following can be machine-specific errata. These do have ability to
213 # provide rudimentary version and machine-specific checks, but expect no
215 # CONFIG_ARM_ERRATA_430973
216 # CONFIG_ARM_ERRATA_454179
217 # CONFIG_ARM_ERRATA_621766
218 # CONFIG_ARM_ERRATA_798870
219 # CONFIG_ARM_ERRATA_801819
220 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
221 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
223 config ARM_ERRATA_430973
226 config ARM_ERRATA_454179
229 config ARM_ERRATA_621766
232 config ARM_ERRATA_716044
235 config ARM_ERRATA_725233
238 config ARM_ERRATA_742230
241 config ARM_ERRATA_743622
244 config ARM_ERRATA_751472
247 config ARM_ERRATA_761320
250 config ARM_ERRATA_773022
253 config ARM_ERRATA_774769
256 config ARM_ERRATA_794072
259 config ARM_ERRATA_798870
262 config ARM_ERRATA_801819
265 config ARM_ERRATA_826974
268 config ARM_ERRATA_828024
271 config ARM_ERRATA_829520
274 config ARM_ERRATA_833069
277 config ARM_ERRATA_833471
280 config ARM_ERRATA_845369
283 config ARM_ERRATA_852421
286 config ARM_ERRATA_852423
289 config ARM_ERRATA_855873
292 config ARM_CORTEX_A8_CVE_2017_5715
295 config ARM_CORTEX_A15_CVE_2017_5715
300 select SYS_CACHE_SHIFT_5
305 select SYS_CACHE_SHIFT_5
310 select SYS_CACHE_SHIFT_5
312 imply SPL_SEPARATE_BSS
316 select SYS_CACHE_SHIFT_5
321 select SYS_CACHE_SHIFT_5
323 imply SPL_SEPARATE_BSS
328 select SYS_CACHE_SHIFT_5
335 select SYS_CACHE_SHIFT_6
342 select SYS_CACHE_SHIFT_5
343 select SYS_THUMB_BUILD
349 select SYS_ARM_CACHE_CP15
351 select SYS_CACHE_SHIFT_6
354 default "arm720t" if CPU_ARM720T
355 default "arm920t" if CPU_ARM920T
356 default "arm926ejs" if CPU_ARM926EJS
357 default "arm946es" if CPU_ARM946ES
358 default "arm1136" if CPU_ARM1136
359 default "arm1176" if CPU_ARM1176
360 default "armv7" if CPU_V7A
361 default "armv7" if CPU_V7R
362 default "armv7m" if CPU_V7M
363 default "armv8" if ARM64
367 default 4 if CPU_ARM720T
368 default 4 if CPU_ARM920T
369 default 5 if CPU_ARM926EJS
370 default 5 if CPU_ARM946ES
371 default 6 if CPU_ARM1136
372 default 6 if CPU_ARM1176
379 prompt "Select the ARM data write cache policy"
380 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMNS || RZA1
381 default SYS_ARM_CACHE_WRITEBACK
383 config SYS_ARM_CACHE_WRITEBACK
384 bool "Write-back (WB)"
386 A write updates the cache only and marks the cache line as dirty.
387 External memory is updated only when the line is evicted or explicitly
390 config SYS_ARM_CACHE_WRITETHROUGH
391 bool "Write-through (WT)"
393 A write updates both the cache and the external memory system.
394 This does not mark the cache line as dirty.
396 config SYS_ARM_CACHE_WRITEALLOC
397 bool "Write allocation (WA)"
399 A cache line is allocated on a write miss. This means that executing a
400 store instruction on the processor might cause a burst read to occur.
401 There is a linefill to obtain the data for the cache line, before the
405 config ARCH_VERY_EARLY_INIT
408 config SPL_ARCH_VERY_EARLY_INIT
412 bool "Enable ARCH_CPU_INIT"
414 Some architectures require a call to arch_cpu_init().
415 Say Y here to enable it
417 config SYS_ARCH_TIMER
418 bool "ARM Generic Timer support"
419 depends on CPU_V7A || ARM64
422 The ARM Generic Timer (aka arch-timer) provides an architected
423 interface to a timer source on an SoC.
424 It is mandatory for ARMv8 implementation and widely available
428 bool "Support for ARM SMC Calling Convention (SMCCC)"
429 depends on CPU_V7A || ARM64
432 Say Y here if you want to enable ARM SMC Calling Convention.
433 This should be enabled if U-Boot needs to communicate with system
434 firmware (for example, PSCI) according to SMCCC.
436 config SYS_THUMB_BUILD
437 bool "Build U-Boot using the Thumb instruction set"
440 Use this flag to build U-Boot using the Thumb instruction set for
441 ARM architectures. Thumb instruction set provides better code
442 density. For ARM architectures that support Thumb2 this flag will
443 result in Thumb2 code generated by GCC.
445 config SPL_SYS_THUMB_BUILD
446 bool "Build SPL using the Thumb instruction set"
447 default y if SYS_THUMB_BUILD
448 depends on !ARM64 && SPL
450 Use this flag to build SPL using the Thumb instruction set for
451 ARM architectures. Thumb instruction set provides better code
452 density. For ARM architectures that support Thumb2 this flag will
453 result in Thumb2 code generated by GCC.
455 config TPL_SYS_THUMB_BUILD
456 bool "Build TPL using the Thumb instruction set"
457 default y if SYS_THUMB_BUILD
458 depends on TPL && !ARM64
460 Use this flag to build TPL using the Thumb instruction set for
461 ARM architectures. Thumb instruction set provides better code
462 density. For ARM architectures that support Thumb2 this flag will
463 result in Thumb2 code generated by GCC.
466 bool "ARM PL310 L2 cache controller"
468 Enable support for ARM PL310 L2 cache controller in U-Boot
470 config SPL_SYS_L2_PL310
471 bool "ARM PL310 L2 cache controller in SPL"
473 Enable support for ARM PL310 L2 cache controller in SPL
475 config SYS_L2CACHE_OFF
478 If SoC does not support L2CACHE or one does not want to enable
479 L2CACHE, choose this option.
481 config ENABLE_ARM_SOC_BOOT0_HOOK
482 bool "prepare BOOT0 header"
484 If the SoC's BOOT0 requires a header area filled with (magic)
485 values, then choose this option, and create a file included as
486 <asm/arch/boot0.h> which contains the required assembler code.
488 config USE_ARCH_MEMCPY
489 bool "Use an assembly optimized implementation of memcpy"
491 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
493 Enable the generation of an optimized version of memcpy.
494 Such an implementation may be faster under some conditions
495 but may increase the binary size.
497 config SPL_USE_ARCH_MEMCPY
498 bool "Use an assembly optimized implementation of memcpy for SPL"
499 default y if USE_ARCH_MEMCPY
502 Enable the generation of an optimized version of memcpy.
503 Such an implementation may be faster under some conditions
504 but may increase the binary size.
506 config TPL_USE_ARCH_MEMCPY
507 bool "Use an assembly optimized implementation of memcpy for TPL"
508 default y if USE_ARCH_MEMCPY
511 Enable the generation of an optimized version of memcpy.
512 Such an implementation may be faster under some conditions
513 but may increase the binary size.
515 config USE_ARCH_MEMMOVE
516 bool "Use an assembly optimized implementation of memmove" if !ARM64
517 default USE_ARCH_MEMCPY if ARM64
520 Enable the generation of an optimized version of memmove.
521 Such an implementation may be faster under some conditions
522 but may increase the binary size.
524 config SPL_USE_ARCH_MEMMOVE
525 bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
526 default SPL_USE_ARCH_MEMCPY if ARM64
527 depends on SPL && ARM64
529 Enable the generation of an optimized version of memmove.
530 Such an implementation may be faster under some conditions
531 but may increase the binary size.
533 config TPL_USE_ARCH_MEMMOVE
534 bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
535 default TPL_USE_ARCH_MEMCPY if ARM64
536 depends on TPL && ARM64
538 Enable the generation of an optimized version of memmove.
539 Such an implementation may be faster under some conditions
540 but may increase the binary size.
542 config USE_ARCH_MEMSET
543 bool "Use an assembly optimized implementation of memset"
545 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
547 Enable the generation of an optimized version of memset.
548 Such an implementation may be faster under some conditions
549 but may increase the binary size.
551 config SPL_USE_ARCH_MEMSET
552 bool "Use an assembly optimized implementation of memset for SPL"
553 default y if USE_ARCH_MEMSET
556 Enable the generation of an optimized version of memset.
557 Such an implementation may be faster under some conditions
558 but may increase the binary size.
560 config TPL_USE_ARCH_MEMSET
561 bool "Use an assembly optimized implementation of memset for TPL"
562 default y if USE_ARCH_MEMSET
565 Enable the generation of an optimized version of memset.
566 Such an implementation may be faster under some conditions
567 but may increase the binary size.
569 config ARM64_SUPPORT_AARCH32
570 bool "ARM64 system support AArch32 execution state"
572 default y if !TARGET_THUNDERX_88XX
574 This ARM64 system supports AArch32 execution state.
580 def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
583 prompt "Target select"
588 select GPIO_EXTRA_HEADER
589 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
590 select SPL_SEPARATE_BSS if SPL
591 imply SYS_THUMB_BUILD
596 select GPIO_EXTRA_HEADER
597 select SPL_DM_SPI if SPL
600 Support for TI's DaVinci platform.
603 bool "Hisilicon HiSTB SoCs"
610 Support for HiSTB SoCs.
613 bool "Marvell Kirkwood"
614 select ARCH_MISC_INIT
615 select BOARD_EARLY_INIT_F
617 select GPIO_EXTRA_HEADER
621 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
622 select ARCH_EARLY_INIT_R if ARM64
627 select GPIO_EXTRA_HEADER
629 select SPL_DM_SPI if SPL
630 select SPL_DM_SPI_FLASH if SPL
631 select SPL_TIMER if SPL
632 select TIMER if !ARM64
641 select GPIO_EXTRA_HEADER
642 select SPL_SEPARATE_BSS if SPL
646 bool "Broadcom BCM283X family"
650 select GPIO_EXTRA_HEADER
653 select SERIAL_SEARCH_ALL
656 imply OF_HAS_PRIOR_STAGE
659 bool "Broadcom BCM7XXX family"
662 select GPIO_EXTRA_HEADER
665 imply OF_HAS_PRIOR_STAGE
667 This enables support for Broadcom ARM-based set-top box
668 chipsets, including the 7445 family of chips.
671 bool "Broadcom broadband chip family"
676 config TARGET_VEXPRESS_CA9X4
677 bool "Support vexpress_ca9x4"
682 bool "Support Broadcom Northstar"
690 select ARM_GLOBAL_TIMER
691 imply SYS_THUMB_BUILD
694 imply NAND_BRCMNAND_IPROC
696 Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit
697 ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094,
701 bool "Support Broadcom NS3"
703 select BOARD_LATE_INIT
705 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
706 ARMv8 Cortex-A72 processors targeting a broad range of networking
710 bool "Samsung EXYNOS"
720 select GPIO_EXTRA_HEADER
721 imply SYS_THUMB_BUILD
726 bool "Samsung S5PC1XX"
732 select GPIO_EXTRA_HEADER
736 bool "Calxeda Highbank"
748 imply OF_HAS_PRIOR_STAGE
750 config ARCH_INTEGRATOR
751 bool "ARM Ltd. Integrator family"
754 select GPIO_EXTRA_HEADER
759 bool "Qualcomm IPQ40xx SoCs"
765 select GPIO_EXTRA_HEADER
769 select CLK_QCOM_IPQ4019
770 select PINCTRL_QCOM_IPQ4019
780 select SPL_BOARD_INIT if SPL
782 select SYS_ARCH_TIMER
783 select SYS_THUMB_BUILD
790 imply TI_KEYSTONE_SERDES
793 bool "Texas Instruments' K3 Architecture"
798 select FIT_SIGNATURE if ARM64
799 imply TI_SECURE_DEVICE
801 config ARCH_OMAP2PLUS
804 select GPIO_EXTRA_HEADER
805 select SPL_SOC_INIT if SPL
806 select SPL_STACK_R if SPL
808 imply TI_SYSC if DM && OF_CONTROL
810 imply SPL_SEPARATE_BSS
814 select GPIO_EXTRA_HEADER
815 imply DISTRO_DEFAULTS
818 Support for the Meson SoC family developed by Amlogic Inc.,
819 targeted at media players and tablet computers. We currently
820 support the S905 (GXBaby) 64-bit SoC.
825 select GPIO_EXTRA_HEADER
828 select SPL_LIBCOMMON_SUPPORT if SPL
829 select SPL_LIBGENERIC_SUPPORT if SPL
830 select SPL_OF_CONTROL if SPL
833 Support for the MediaTek SoCs family developed by MediaTek Inc.
834 Please refer to doc/README.mediatek for more information.
837 bool "NXP LPC32xx platform"
842 select GPIO_EXTRA_HEADER
848 bool "NXP i.MX8 platform"
850 select SYS_FSL_HAS_SEC
851 select SYS_FSL_SEC_COMPAT_4
852 select SYS_FSL_SEC_LE
855 select GPIO_EXTRA_HEADER
858 select ENABLE_ARM_SOC_BOOT0_HOOK
861 bool "NXP i.MX8M platform"
863 select GPIO_EXTRA_HEADER
865 select SYS_FSL_HAS_SEC
866 select SYS_FSL_SEC_COMPAT_4
867 select SYS_FSL_SEC_LE
870 select DM_EVENT if CLK
875 bool "NXP i.MX8ULP platform"
882 select GPIO_EXTRA_HEADER
888 bool "NXP i.MX9 platform"
894 select GPIO_EXTRA_HEADER
900 bool "NXP i.MXRT platform"
904 select GPIO_EXTRA_HEADER
910 bool "NXP i.MX23 family"
912 select GPIO_EXTRA_HEADER
917 bool "NXP i.MX28 family"
919 select GPIO_EXTRA_HEADER
924 bool "NXP i.MX31 family"
926 select GPIO_EXTRA_HEADER
931 select BOARD_POSTCLK_INIT
933 select GPIO_EXTRA_HEADER
935 select SYS_FSL_HAS_SEC
936 select SYS_FSL_SEC_COMPAT_4
937 select SYS_FSL_SEC_LE
938 select ROM_UNIFIED_SECTIONS
940 imply SYS_THUMB_BUILD
944 select ARCH_MISC_INIT
946 select GPIO_EXTRA_HEADER
949 select SYS_FSL_HAS_SEC
950 select SYS_FSL_SEC_COMPAT_4
951 select SYS_FSL_SEC_LE
952 imply BOARD_EARLY_INIT_F
954 imply SYS_THUMB_BUILD
958 select BOARD_POSTCLK_INIT
960 select GPIO_EXTRA_HEADER
963 select SYS_FSL_HAS_SEC
964 select SYS_FSL_SEC_COMPAT_4
965 select SYS_FSL_SEC_LE
966 select SYS_L2_PL310 if !SYS_L2CACHE_OFF
968 imply SYS_THUMB_BUILD
969 imply SPL_SEPARATE_BSS
973 select BOARD_EARLY_INIT_F
975 select GPIO_EXTRA_HEADER
980 bool "Nexell S5P4418/S5P6818 SoC"
981 select ENABLE_ARM_SOC_BOOT0_HOOK
983 select GPIO_EXTRA_HEADER
986 bool "Support Nuvoton SoCs"
1007 select LINUX_KERNEL_IMAGE_HEADER
1009 select OF_BOARD_SETUP
1014 select POSITION_INDEPENDENT
1020 select SYSRESET_WATCHDOG
1021 select SYSRESET_WATCHDOG_AUTO
1026 imply OF_HAS_PRIOR_STAGE
1029 bool "Actions Semi OWL SoCs"
1032 select GPIO_EXTRA_HEADER
1037 select SYS_RELOC_GD_ENV_ADDR
1041 bool "QEMU Virtual Platform"
1050 imply OF_HAS_PRIOR_STAGE
1053 imply SYS_WHITE_ON_BLACK
1054 imply SYS_CONSOLE_IS_IN_ENV
1055 imply PRE_CONSOLE_BUFFER
1063 bool "Renesas ARM SoCs"
1066 select GPIO_EXTRA_HEADER
1068 imply BOARD_EARLY_INIT_F
1072 imply SYS_THUMB_BUILD
1073 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
1075 config ARCH_SNAPDRAGON
1076 bool "Qualcomm Snapdragon SoCs"
1083 select GPIO_EXTRA_HEADER
1089 select BOARD_LATE_INIT
1091 select SAVE_PREV_BL_FDT_ADDR
1092 select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK
1097 bool "Altera SOCFPGA family"
1098 select ARCH_EARLY_INIT_R
1099 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
1100 select ARM64 if TARGET_SOCFPGA_SOC64
1101 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1105 select GPIO_EXTRA_HEADER
1106 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1108 select SPL_DM_RESET if DM_RESET
1109 select SPL_DM_SERIAL
1110 select SPL_LIBCOMMON_SUPPORT
1111 select SPL_LIBGENERIC_SUPPORT
1112 select SPL_OF_CONTROL
1113 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
1114 select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64
1115 select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64
1121 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1123 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1124 select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
1125 TARGET_SOCFPGA_SOC64
1136 imply SPL_DM_SPI_FLASH
1137 imply SPL_LIBDISK_SUPPORT
1139 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1140 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1141 imply SPL_SPI_FLASH_SUPPORT
1146 bool "Support sunxi (Allwinner) SoCs"
1149 select CMD_MMC if MMC
1150 select CMD_USB if DISTRO_DEFAULTS && USB_HOST
1154 select DM_I2C if I2C
1155 select DM_SPI if SPI
1156 select DM_SPI_FLASH if SPI && MTD
1158 select DM_MMC if MMC
1160 select OF_BOARD_SETUP
1164 select SPECIFY_CONSOLE_INDEX
1165 select SPL_SEPARATE_BSS if SPL
1166 select SPL_STACK_R if SPL
1167 select SPL_SYS_MALLOC_SIMPLE if SPL
1168 select SPL_SYS_THUMB_BUILD if SPL && !ARM64
1171 select SYS_THUMB_BUILD if !ARM64
1172 select USB if DISTRO_DEFAULTS
1173 select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
1174 select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
1175 select SPL_USE_TINY_PRINTF if SPL
1177 select SYS_RELOC_GD_ENV_ADDR
1178 imply BOARD_LATE_INIT
1181 imply CMD_UBI if MTD_RAW_NAND
1182 imply DISTRO_DEFAULTS
1184 imply DM_REGULATOR_FIXED
1187 imply OF_LIBFDT_OVERLAY
1188 imply PRE_CONSOLE_BUFFER
1190 imply SPL_LIBCOMMON_SUPPORT
1191 imply SPL_LIBGENERIC_SUPPORT
1192 imply SPL_MMC if MMC
1196 imply SYSRESET_WATCHDOG
1197 imply SYSRESET_WATCHDOG_AUTO
1202 bool "ST-Ericsson U8500 Series"
1206 select DM_MMC if MMC
1208 select DM_USB_GADGET if DM_USB
1212 imply AB8500_USB_PHY
1213 imply ARM_PL180_MMCI
1218 imply NOMADIK_MTU_TIMER
1223 imply SYS_THUMB_BUILD
1224 imply SYSRESET_SYSCON
1227 bool "Support Xilinx Versal Platform"
1231 select DM_MMC if MMC
1236 imply BOARD_LATE_INIT
1237 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1240 bool "Support AMD Versal Gen 2 Platform"
1244 select DM_MMC if MMC
1247 imply BOARD_LATE_INIT
1248 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1249 imply ZYNQMP_FIRMWARE
1251 config ARCH_VERSAL_NET
1252 bool "Support Xilinx Versal NET Platform"
1256 select DM_MMC if MMC
1259 imply BOARD_LATE_INIT
1260 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1263 bool "Freescale Vybrid"
1265 select GPIO_EXTRA_HEADER
1266 select IOMUX_SHARE_CONF_REG
1268 select SYS_FSL_ERRATUM_ESDHC111
1273 bool "Xilinx Zynq based platform"
1274 select ARM_TWD_TIMER
1275 select ARCH_EARLY_INIT_R if FPGA || (SPL && SPL_FPGA)
1279 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1281 select DM_MMC if MMC
1288 select SPL_SOC_INIT if SPL
1289 select SPL_CLK if SPL
1290 select SPL_DM if SPL
1291 select SPL_DM_SPI if SPL
1292 select SPL_DM_SPI_FLASH if SPL
1293 select SPL_OF_CONTROL if SPL
1294 select SPL_SEPARATE_BSS if SPL
1295 select SPL_TIMER if SPL
1298 imply BOARD_LATE_INIT
1302 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1305 config ARCH_ZYNQMP_R5
1306 bool "Xilinx ZynqMP R5 based platform"
1310 select DM_MMC if MMC
1317 bool "Xilinx ZynqMP based platform"
1321 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1323 select DM_MMC if MMC
1326 select DM_SPI if SPI
1327 select DM_SPI_FLASH if DM_SPI
1331 select SPL_SOC_INIT if SPL
1332 select SPL_CLK if SPL
1333 select SPL_DM if SPL
1334 select SPL_DM_SPI if SPI && SPL_DM
1335 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1336 select SPL_DM_MAILBOX if SPL
1337 imply SPL_FIRMWARE if SPL
1338 imply SPL_FS_FAT if SPL
1339 imply SPL_LIBCOMMON_SUPPORT if SPL
1340 imply SPL_LIBDISK_SUPPORT if SPL
1341 imply SPL_LIBGENERIC_SUPPORT if SPL
1342 imply SPL_MMC if SPL && MMC_SDHCI_ZYNQ
1343 imply SPL_SERIAL if SPL
1344 imply SPL_SPI if SPL && ZYNQ_QSPI
1345 imply SPL_SPI_FLASH_SUPPORT if SPL && ZYNQ_QSPI
1346 select SPL_SEPARATE_BSS if SPL
1348 imply ZYNQMP_IPI if DM_MAILBOX
1350 imply BOARD_LATE_INIT
1352 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1356 imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
1360 select GPIO_EXTRA_HEADER
1361 imply BOOTSTD_DEFAULTS
1363 imply SPL_TIMER if SPL
1365 config ARCH_VEXPRESS64
1366 bool "Support ARMv8 Arm Ltd. VExpress based boards and models"
1374 select MTD_NOR_FLASH if MTD
1375 select FLASH_CFI_DRIVER if MTD
1376 select ENV_IS_IN_FLASH if MTD
1377 imply DISTRO_DEFAULTS
1379 config TARGET_CORSTONE1000
1380 bool "Support Corstone1000 Platform"
1385 config TARGET_TOTAL_COMPUTE
1386 bool "Support Total Compute Platform"
1394 config TARGET_LS2080A_EMU
1395 bool "Support ls2080a_emu"
1398 select ARMV8_MULTIENTRY
1399 select FSL_DDR_SYNC_REFRESH
1400 select GPIO_EXTRA_HEADER
1402 Support for Freescale LS2080A_EMU platform.
1403 The LS2080A Development System (EMULATOR) is a pre-silicon
1404 development platform that supports the QorIQ LS2080A
1405 Layerscape Architecture processor.
1407 config TARGET_LS1088AQDS
1408 bool "Support ls1088aqds"
1411 select ARMV8_MULTIENTRY
1412 select ARCH_SUPPORT_TFABOOT
1413 select BOARD_LATE_INIT
1414 select GPIO_EXTRA_HEADER
1416 select FSL_DDR_INTERACTIVE if !SD_BOOT
1418 Support for NXP LS1088AQDS platform.
1419 The LS1088A Development System (QDS) is a high-performance
1420 development platform that supports the QorIQ LS1088A
1421 Layerscape Architecture processor.
1423 config TARGET_LS2080AQDS
1424 bool "Support ls2080aqds"
1427 select ARMV8_MULTIENTRY
1428 select ARCH_SUPPORT_TFABOOT
1429 select BOARD_LATE_INIT
1430 select GPIO_EXTRA_HEADER
1435 select FSL_DDR_INTERACTIVE if !SPL
1437 Support for Freescale LS2080AQDS platform.
1438 The LS2080A Development System (QDS) is a high-performance
1439 development platform that supports the QorIQ LS2080A
1440 Layerscape Architecture processor.
1442 config TARGET_LS2080ARDB
1443 bool "Support ls2080ardb"
1446 select ARMV8_MULTIENTRY
1447 select ARCH_SUPPORT_TFABOOT
1448 select BOARD_LATE_INIT
1451 select FSL_DDR_INTERACTIVE if !SPL
1452 select GPIO_EXTRA_HEADER
1456 Support for Freescale LS2080ARDB platform.
1457 The LS2080A Reference design board (RDB) is a high-performance
1458 development platform that supports the QorIQ LS2080A
1459 Layerscape Architecture processor.
1461 config TARGET_LS2081ARDB
1462 bool "Support ls2081ardb"
1465 select ARMV8_MULTIENTRY
1466 select BOARD_LATE_INIT
1467 select GPIO_EXTRA_HEADER
1470 Support for Freescale LS2081ARDB platform.
1471 The LS2081A Reference design board (RDB) is a high-performance
1472 development platform that supports the QorIQ LS2081A/LS2041A
1473 Layerscape Architecture processor.
1475 config TARGET_LX2160ARDB
1476 bool "Support lx2160ardb"
1479 select ARMV8_MULTIENTRY
1480 select ARCH_SUPPORT_TFABOOT
1481 select BOARD_LATE_INIT
1482 select GPIO_EXTRA_HEADER
1484 Support for NXP LX2160ARDB platform.
1485 The lx2160ardb (LX2160A Reference design board (RDB)
1486 is a high-performance development platform that supports the
1487 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1489 config TARGET_LX2160AQDS
1490 bool "Support lx2160aqds"
1493 select ARMV8_MULTIENTRY
1494 select ARCH_SUPPORT_TFABOOT
1495 select BOARD_LATE_INIT
1496 select GPIO_EXTRA_HEADER
1498 Support for NXP LX2160AQDS platform.
1499 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1500 is a high-performance development platform that supports the
1501 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1503 config TARGET_LX2162AQDS
1504 bool "Support lx2162aqds"
1506 select ARCH_MISC_INIT
1508 select ARMV8_MULTIENTRY
1509 select ARCH_SUPPORT_TFABOOT
1510 select BOARD_LATE_INIT
1511 select GPIO_EXTRA_HEADER
1513 Support for NXP LX2162AQDS platform.
1514 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1517 bool "Support HiKey 96boards Consumer Edition Platform"
1522 select GPIO_EXTRA_HEADER
1525 select SPECIFY_CONSOLE_INDEX
1528 Support for HiKey 96boards platform. It features a HI6220
1529 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1531 config TARGET_HIKEY960
1532 bool "Support HiKey960 96boards Consumer Edition Platform"
1536 select GPIO_EXTRA_HEADER
1541 Support for HiKey960 96boards platform. It features a HI3660
1542 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1544 config TARGET_POPLAR
1545 bool "Support Poplar 96boards Enterprise Edition Platform"
1549 select GPIO_EXTRA_HEADER
1554 Support for Poplar 96boards EE platform. It features a HI3798cv200
1555 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1556 making it capable of running any commercial set-top solution based on
1559 config TARGET_LS1012AQDS
1560 bool "Support ls1012aqds"
1563 select ARCH_SUPPORT_TFABOOT
1564 select BOARD_LATE_INIT
1565 select GPIO_EXTRA_HEADER
1567 Support for Freescale LS1012AQDS platform.
1568 The LS1012A Development System (QDS) is a high-performance
1569 development platform that supports the QorIQ LS1012A
1570 Layerscape Architecture processor.
1572 config TARGET_LS1012ARDB
1573 bool "Support ls1012ardb"
1576 select ARCH_SUPPORT_TFABOOT
1577 select BOARD_LATE_INIT
1578 select GPIO_EXTRA_HEADER
1582 Support for Freescale LS1012ARDB platform.
1583 The LS1012A Reference design board (RDB) is a high-performance
1584 development platform that supports the QorIQ LS1012A
1585 Layerscape Architecture processor.
1587 config TARGET_LS1012A2G5RDB
1588 bool "Support ls1012a2g5rdb"
1591 select ARCH_SUPPORT_TFABOOT
1592 select BOARD_LATE_INIT
1593 select GPIO_EXTRA_HEADER
1596 Support for Freescale LS1012A2G5RDB platform.
1597 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1598 development platform that supports the QorIQ LS1012A
1599 Layerscape Architecture processor.
1601 config TARGET_LS1012AFRWY
1602 bool "Support ls1012afrwy"
1605 select ARCH_SUPPORT_TFABOOT
1606 select BOARD_LATE_INIT
1607 select GPIO_EXTRA_HEADER
1611 Support for Freescale LS1012AFRWY platform.
1612 The LS1012A FRWY board (FRWY) is a high-performance
1613 development platform that supports the QorIQ LS1012A
1614 Layerscape Architecture processor.
1616 config TARGET_LS1012AFRDM
1617 bool "Support ls1012afrdm"
1620 select ARCH_SUPPORT_TFABOOT
1621 select GPIO_EXTRA_HEADER
1623 Support for Freescale LS1012AFRDM platform.
1624 The LS1012A Freedom board (FRDM) is a high-performance
1625 development platform that supports the QorIQ LS1012A
1626 Layerscape Architecture processor.
1628 config TARGET_LS1028AQDS
1629 bool "Support ls1028aqds"
1632 select ARMV8_MULTIENTRY
1633 select ARCH_SUPPORT_TFABOOT
1634 select BOARD_LATE_INIT
1635 select GPIO_EXTRA_HEADER
1637 Support for Freescale LS1028AQDS platform
1638 The LS1028A Development System (QDS) is a high-performance
1639 development platform that supports the QorIQ LS1028A
1640 Layerscape Architecture processor.
1642 config TARGET_LS1028ARDB
1643 bool "Support ls1028ardb"
1646 select ARMV8_MULTIENTRY
1647 select ARCH_SUPPORT_TFABOOT
1648 select BOARD_LATE_INIT
1649 select GPIO_EXTRA_HEADER
1651 Support for Freescale LS1028ARDB platform
1652 The LS1028A Development System (RDB) is a high-performance
1653 development platform that supports the QorIQ LS1028A
1654 Layerscape Architecture processor.
1656 config TARGET_LS1088ARDB
1657 bool "Support ls1088ardb"
1660 select ARMV8_MULTIENTRY
1661 select ARCH_SUPPORT_TFABOOT
1662 select BOARD_LATE_INIT
1664 select FSL_DDR_INTERACTIVE if !SD_BOOT
1665 select GPIO_EXTRA_HEADER
1667 Support for NXP LS1088ARDB platform.
1668 The LS1088A Reference design board (RDB) is a high-performance
1669 development platform that supports the QorIQ LS1088A
1670 Layerscape Architecture processor.
1672 config TARGET_LS1021AQDS
1673 bool "Support ls1021aqds"
1675 select ARCH_SUPPORT_PSCI
1676 select BOARD_EARLY_INIT_F
1677 select BOARD_LATE_INIT
1679 select CPU_V7_HAS_NONSEC
1680 select CPU_V7_HAS_VIRT
1681 select LS1_DEEP_SLEEP
1682 select PEN_ADDR_BIG_ENDIAN
1685 select FSL_DDR_INTERACTIVE
1686 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1687 select GPIO_EXTRA_HEADER
1688 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1691 config TARGET_LS1021ATWR
1692 bool "Support ls1021atwr"
1694 select ARCH_SUPPORT_PSCI
1695 select BOARD_EARLY_INIT_F
1696 select BOARD_LATE_INIT
1698 select CPU_V7_HAS_NONSEC
1699 select CPU_V7_HAS_VIRT
1700 select LS1_DEEP_SLEEP
1701 select PEN_ADDR_BIG_ENDIAN
1703 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1704 select GPIO_EXTRA_HEADER
1707 config TARGET_PG_WCOM_SELI8
1708 bool "Support Hitachi-Powergrids SELI8 service unit card"
1710 select ARCH_SUPPORT_PSCI
1711 select BOARD_EARLY_INIT_F
1712 select BOARD_LATE_INIT
1714 select CPU_V7_HAS_NONSEC
1715 select CPU_V7_HAS_VIRT
1717 select FSL_DDR_INTERACTIVE
1718 select GPIO_EXTRA_HEADER
1722 Support for Hitachi-Powergrids SELI8 service unit card.
1723 SELI8 is a QorIQ LS1021a based service unit card used
1724 in XMC20 and FOX615 product families.
1726 config TARGET_PG_WCOM_EXPU1
1727 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1729 select ARCH_SUPPORT_PSCI
1730 select BOARD_EARLY_INIT_F
1731 select BOARD_LATE_INIT
1733 select CPU_V7_HAS_NONSEC
1734 select CPU_V7_HAS_VIRT
1736 select FSL_DDR_INTERACTIVE
1740 Support for Hitachi-Powergrids EXPU1 service unit card.
1741 EXPU1 is a QorIQ LS1021a based service unit card used
1742 in XMC20 and FOX615 product families.
1744 config TARGET_LS1021ATSN
1745 bool "Support ls1021atsn"
1747 select ARCH_SUPPORT_PSCI
1748 select BOARD_EARLY_INIT_F
1749 select BOARD_LATE_INIT
1751 select CPU_V7_HAS_NONSEC
1752 select CPU_V7_HAS_VIRT
1753 select LS1_DEEP_SLEEP
1755 select GPIO_EXTRA_HEADER
1758 config TARGET_LS1021AIOT
1759 bool "Support ls1021aiot"
1761 select ARCH_SUPPORT_PSCI
1762 select BOARD_LATE_INIT
1764 select CPU_V7_HAS_NONSEC
1765 select CPU_V7_HAS_VIRT
1766 select PEN_ADDR_BIG_ENDIAN
1768 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1769 select GPIO_EXTRA_HEADER
1772 Support for Freescale LS1021AIOT platform.
1773 The LS1021A Freescale board (IOT) is a high-performance
1774 development platform that supports the QorIQ LS1021A
1775 Layerscape Architecture processor.
1777 config TARGET_LS1043AQDS
1778 bool "Support ls1043aqds"
1781 select ARMV8_MULTIENTRY
1782 select ARCH_SUPPORT_TFABOOT
1783 select BOARD_EARLY_INIT_F
1784 select BOARD_LATE_INIT
1786 select FSL_DDR_INTERACTIVE if !SPL
1787 select FSL_DSPI if !SPL_NO_DSPI
1788 select DM_SPI_FLASH if FSL_DSPI
1789 select GPIO_EXTRA_HEADER
1793 Support for Freescale LS1043AQDS platform.
1795 config TARGET_LS1043ARDB
1796 bool "Support ls1043ardb"
1799 select ARMV8_MULTIENTRY
1800 select ARCH_SUPPORT_TFABOOT
1801 select BOARD_EARLY_INIT_F
1802 select BOARD_LATE_INIT
1804 select FSL_DSPI if !SPL_NO_DSPI
1805 select DM_SPI_FLASH if FSL_DSPI
1806 select GPIO_EXTRA_HEADER
1808 Support for Freescale LS1043ARDB platform.
1810 config TARGET_LS1046AQDS
1811 bool "Support ls1046aqds"
1814 select ARMV8_MULTIENTRY
1815 select ARCH_SUPPORT_TFABOOT
1816 select BOARD_EARLY_INIT_F
1817 select BOARD_LATE_INIT
1818 select DM_SPI_FLASH if DM_SPI
1820 select FSL_DDR_BIST if !SPL
1821 select FSL_DDR_INTERACTIVE if !SPL
1822 select FSL_DDR_INTERACTIVE if !SPL
1823 select GPIO_EXTRA_HEADER
1826 Support for Freescale LS1046AQDS platform.
1827 The LS1046A Development System (QDS) is a high-performance
1828 development platform that supports the QorIQ LS1046A
1829 Layerscape Architecture processor.
1831 config TARGET_LS1046ARDB
1832 bool "Support ls1046ardb"
1835 select ARMV8_MULTIENTRY
1836 select ARCH_SUPPORT_TFABOOT
1837 select BOARD_EARLY_INIT_F
1838 select BOARD_LATE_INIT
1839 select DM_SPI_FLASH if DM_SPI
1840 select POWER_MC34VR500
1843 select FSL_DDR_INTERACTIVE if !SPL
1844 select GPIO_EXTRA_HEADER
1847 Support for Freescale LS1046ARDB platform.
1848 The LS1046A Reference Design Board (RDB) is a high-performance
1849 development platform that supports the QorIQ LS1046A
1850 Layerscape Architecture processor.
1852 config TARGET_LS1046AFRWY
1853 bool "Support ls1046afrwy"
1856 select ARMV8_MULTIENTRY
1857 select ARCH_SUPPORT_TFABOOT
1858 select BOARD_EARLY_INIT_F
1859 select BOARD_LATE_INIT
1860 select DM_SPI_FLASH if DM_SPI
1861 select GPIO_EXTRA_HEADER
1864 Support for Freescale LS1046AFRWY platform.
1865 The LS1046A Freeway Board (FRWY) is a high-performance
1866 development platform that supports the QorIQ LS1046A
1867 Layerscape Architecture processor.
1870 bool "Analog Devices SC5XX-processor family"
1876 select ARMV8_MULTIENTRY
1892 select GPIO_EXTRA_HEADER
1893 select SPL_DM if SPL
1894 select SPL_DM_SPI if SPL
1895 select SPL_DM_SPI_FLASH if SPL
1896 select SPL_DM_I2C if SPL
1897 select SPL_DM_MMC if SPL
1898 select SPL_DM_SERIAL if SPL
1900 Support for Kontron SMARC-sAL28 board.
1903 bool "Support ten64"
1905 select ARCH_MISC_INIT
1907 select ARMV8_MULTIENTRY
1908 select ARCH_SUPPORT_TFABOOT
1909 select BOARD_LATE_INIT
1911 select FSL_DDR_INTERACTIVE if !SD_BOOT
1912 select GPIO_EXTRA_HEADER
1914 Support for Traverse Technologies Ten64 board, based
1917 config ARCH_UNIPHIER
1918 bool "Socionext UniPhier SoCs"
1919 select BOARD_LATE_INIT
1927 select OF_BOARD_SETUP
1931 select SPL_BOARD_INIT if SPL
1932 select SPL_DM if SPL
1933 select SPL_LIBCOMMON_SUPPORT if SPL
1934 select SPL_LIBGENERIC_SUPPORT if SPL
1935 select SPL_OF_CONTROL if SPL
1936 select SPL_PINCTRL if SPL
1939 imply DISTRO_DEFAULTS
1942 Support for UniPhier SoC family developed by Socionext Inc.
1943 (formerly, System LSI Business Division of Panasonic Corporation)
1945 config ARCH_SYNQUACER
1946 bool "Socionext SynQuacer SoCs"
1952 select SYSRESET_PSCI
1955 Support for SynQuacer SoC family developed by Socionext Inc.
1956 This SoC is used on 96boards EE DeveloperBox.
1959 bool "Support STMicroelectronics STM32 MCU with cortex M"
1966 bool "Support STMicroelectronics SoCs"
1975 Support for STMicroelectronics STiH407/10 SoC family.
1976 This SoC is used on Linaro 96Board STiH410-B2260
1979 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1980 select ARCH_MISC_INIT
1981 select ARCH_SUPPORT_TFABOOT
1982 select BOARD_LATE_INIT
1991 select OF_SYSTEM_SETUP
1996 select SYS_THUMB_BUILD if !ARM64
2000 imply OF_LIBFDT_OVERLAY
2001 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
2005 Support for STM32MP SoC family developed by STMicroelectronics,
2006 MPUs based on ARM cortex A core
2007 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
2008 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
2010 SPL is the unsecure FSBL for the basic boot chain.
2012 config ARCH_ROCKCHIP
2013 bool "Support Rockchip SoCs"
2015 select BINMAN if SPL_OPTEE || SPL
2025 select DM_USB_GADGET if USB_DWC3_GADGET
2026 select ENABLE_ARM_SOC_BOOT0_HOOK
2030 select SPL_DM if SPL
2031 select SPL_DM_SPI if SPL
2032 select SPL_DM_SPI_FLASH if SPL
2034 select SYS_THUMB_BUILD if !ARM64
2037 imply DEBUG_UART_BOARD_INIT
2038 imply BOOTSTD_DEFAULTS
2040 imply SARADC_ROCKCHIP
2042 imply SPL_SYS_MALLOC_SIMPLE
2045 imply USB_FUNCTION_FASTBOOT
2047 config ARCH_OCTEONTX
2048 bool "Support OcteonTX SoCs"
2051 select GPIO_EXTRA_HEADER
2055 select BOARD_LATE_INIT
2056 select SYS_CACHE_SHIFT_7
2057 select SYS_PCI_64BIT if PCI
2058 imply OF_HAS_PRIOR_STAGE
2060 config ARCH_OCTEONTX2
2061 bool "Support OcteonTX2 SoCs"
2064 select GPIO_EXTRA_HEADER
2068 select BOARD_LATE_INIT
2069 select SYS_CACHE_SHIFT_7
2070 select SYS_PCI_64BIT if PCI
2071 imply OF_HAS_PRIOR_STAGE
2073 config TARGET_THUNDERX_88XX
2074 bool "Support ThunderX 88xx"
2076 select GPIO_EXTRA_HEADER
2079 select SYS_CACHE_SHIFT_7
2082 bool "Support Aspeed SoCs"
2087 config TARGET_DURIAN
2088 bool "Support Phytium Durian Platform"
2090 select GPIO_EXTRA_HEADER
2092 Support for durian platform.
2093 It has 2GB Sdram, uart and pcie.
2095 config TARGET_POMELO
2096 bool "Support Phytium Pomelo Platform"
2109 Support for pomelo platform.
2110 It has 8GB Sdram, uart and pcie.
2112 config TARGET_PE2201
2113 bool "Support Phytium PE2201 Platform"
2116 Support for pe2201 platform.It has 2GB Sdram, uart and pcie.
2118 config TARGET_PRESIDIO_ASIC
2119 bool "Support Cortina Presidio ASIC Platform"
2123 config TARGET_XENGUEST_ARM64
2124 bool "Xen guest ARM64"
2128 select LINUX_KERNEL_IMAGE_HEADER
2130 imply OF_HAS_PRIOR_STAGE
2133 bool "Support HPE GXP SoCs"
2140 config SUPPORT_PASSING_ATAGS
2141 bool "Support pre-devicetree ATAG-based booting"
2143 imply SETUP_MEMORY_TAGS
2145 Support for booting older Linux kernels, using ATAGs rather than
2146 passing a devicetree. This is option is rarely used, and the
2147 semantics are defined at
2148 https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
2150 config SETUP_MEMORY_TAGS
2151 bool "Pass memory size information via ATAG"
2152 depends on SUPPORT_PASSING_ATAGS
2155 bool "Pass Linux kernel cmdline via ATAG"
2156 depends on SUPPORT_PASSING_ATAGS
2159 bool "Pass initrd starting point and size via ATAG"
2160 depends on SUPPORT_PASSING_ATAGS
2163 bool "Pass system revision via ATAG"
2164 depends on SUPPORT_PASSING_ATAGS
2167 bool "Pass system serial number via ATAG"
2168 depends on SUPPORT_PASSING_ATAGS
2170 config STATIC_MACH_TYPE
2171 bool "Statically define the Machine ID number"
2172 default y if TARGET_DS109 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2174 When booting via ATAGs, enable this option if we know the correct
2175 machine ID number to use at compile time. Some systems will be
2176 passed the number dynamically by whatever loads U-Boot.
2179 int "Machine ID number"
2180 depends on STATIC_MACH_TYPE
2181 default 527 if TARGET_DS109
2182 default 3036 if TARGET_DS414
2183 default 4283 if DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2185 When booting via ATAGs, the machine type must be passed as a number.
2186 For the full list see https://www.arm.linux.org.uk/developer/machines
2188 config ARCH_SUPPORT_TFABOOT
2192 bool "Support for booting from TF-A"
2193 depends on ARCH_SUPPORT_TFABOOT
2195 Some platforms support the setup of secure registers (for instance
2196 for CPU errata handling) or provide secure services like PSCI.
2197 Those services could also be provided by other firmware parts
2198 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
2199 does not need to (and cannot) execute this code.
2200 Enabling this option will make a U-Boot binary that is relying
2201 on other firmware layers to provide secure functionality.
2203 config TI_SECURE_DEVICE
2204 bool "HS Device Type Support"
2205 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
2207 If a high secure (HS) device type is being used, this config
2208 must be set. This option impacts various aspects of the
2209 build system (to create signed boot images that can be
2210 authenticated) and the code. See the doc/README.ti-secure
2211 file for further details.
2213 config SYS_KWD_CONFIG
2214 string "kwbimage config file path"
2215 depends on ARCH_KIRKWOOD || ARCH_MVEBU
2216 default "arch/arm/mach-mvebu/kwbimage.cfg"
2218 Path within the source directory to the kwbimage.cfg file to use
2219 when packaging the U-Boot image for use.
2221 source "arch/arm/mach-apple/Kconfig"
2223 source "arch/arm/mach-aspeed/Kconfig"
2225 source "arch/arm/mach-at91/Kconfig"
2227 source "arch/arm/mach-bcm283x/Kconfig"
2229 source "arch/arm/mach-bcmbca/Kconfig"
2231 source "arch/arm/mach-bcmstb/Kconfig"
2233 source "arch/arm/mach-davinci/Kconfig"
2235 source "arch/arm/mach-exynos/Kconfig"
2237 source "arch/arm/mach-hpe/gxp/Kconfig"
2239 source "arch/arm/mach-highbank/Kconfig"
2241 source "arch/arm/mach-histb/Kconfig"
2243 source "arch/arm/mach-integrator/Kconfig"
2245 source "arch/arm/mach-ipq40xx/Kconfig"
2247 source "arch/arm/mach-k3/Kconfig"
2249 source "arch/arm/mach-keystone/Kconfig"
2251 source "arch/arm/mach-kirkwood/Kconfig"
2253 source "arch/arm/mach-lpc32xx/Kconfig"
2255 source "arch/arm/mach-mvebu/Kconfig"
2257 source "arch/arm/mach-octeontx/Kconfig"
2259 source "arch/arm/mach-octeontx2/Kconfig"
2261 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2263 source "arch/arm/mach-imx/mx3/Kconfig"
2265 source "arch/arm/mach-imx/mx5/Kconfig"
2267 source "arch/arm/mach-imx/mx6/Kconfig"
2269 source "arch/arm/mach-imx/mx7/Kconfig"
2271 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2273 source "arch/arm/mach-imx/imx8/Kconfig"
2275 source "arch/arm/mach-imx/imx8m/Kconfig"
2277 source "arch/arm/mach-imx/imx8ulp/Kconfig"
2279 source "arch/arm/mach-imx/imx9/Kconfig"
2281 source "arch/arm/mach-imx/imxrt/Kconfig"
2283 source "arch/arm/mach-imx/mxs/Kconfig"
2285 source "arch/arm/mach-omap2/Kconfig"
2287 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2289 source "arch/arm/mach-orion5x/Kconfig"
2291 source "arch/arm/mach-owl/Kconfig"
2293 source "arch/arm/mach-renesas/Kconfig"
2295 source "arch/arm/mach-meson/Kconfig"
2297 source "arch/arm/mach-mediatek/Kconfig"
2299 source "arch/arm/mach-qemu/Kconfig"
2301 source "arch/arm/mach-rockchip/Kconfig"
2303 source "arch/arm/mach-s5pc1xx/Kconfig"
2305 source "arch/arm/mach-sc5xx/Kconfig"
2307 source "arch/arm/mach-snapdragon/Kconfig"
2309 source "arch/arm/mach-socfpga/Kconfig"
2311 source "arch/arm/mach-sti/Kconfig"
2313 source "arch/arm/mach-stm32/Kconfig"
2315 source "arch/arm/mach-stm32mp/Kconfig"
2317 source "arch/arm/mach-sunxi/Kconfig"
2319 source "arch/arm/mach-tegra/Kconfig"
2321 source "arch/arm/mach-u8500/Kconfig"
2323 source "arch/arm/mach-uniphier/Kconfig"
2325 source "arch/arm/cpu/armv7/vf610/Kconfig"
2327 source "arch/arm/mach-zynq/Kconfig"
2329 source "arch/arm/mach-zynqmp/Kconfig"
2331 source "arch/arm/mach-versal/Kconfig"
2333 source "arch/arm/mach-versal2/Kconfig"
2335 source "arch/arm/mach-versal-net/Kconfig"
2337 source "arch/arm/mach-zynqmp-r5/Kconfig"
2339 source "arch/arm/cpu/armv7/Kconfig"
2341 source "arch/arm/cpu/armv8/Kconfig"
2343 source "arch/arm/mach-imx/Kconfig"
2345 source "arch/arm/mach-nexell/Kconfig"
2347 source "arch/arm/mach-npcm/Kconfig"
2349 source "board/armltd/total_compute/Kconfig"
2350 source "board/armltd/corstone1000/Kconfig"
2351 source "board/bosch/shc/Kconfig"
2352 source "board/bosch/guardian/Kconfig"
2353 source "board/Marvell/octeontx/Kconfig"
2354 source "board/Marvell/octeontx2/Kconfig"
2355 source "board/armltd/vexpress/Kconfig"
2356 source "board/armltd/vexpress64/Kconfig"
2357 source "board/cortina/presidio-asic/Kconfig"
2358 source "board/broadcom/bcmns/Kconfig"
2359 source "board/broadcom/bcmns3/Kconfig"
2360 source "board/cavium/thunderx/Kconfig"
2361 source "board/eets/pdu001/Kconfig"
2362 source "board/emulation/qemu-arm/Kconfig"
2363 source "board/freescale/ls2080aqds/Kconfig"
2364 source "board/freescale/ls2080ardb/Kconfig"
2365 source "board/freescale/ls1088a/Kconfig"
2366 source "board/freescale/ls1028a/Kconfig"
2367 source "board/freescale/ls1021aqds/Kconfig"
2368 source "board/freescale/ls1043aqds/Kconfig"
2369 source "board/freescale/ls1021atwr/Kconfig"
2370 source "board/freescale/ls1021atsn/Kconfig"
2371 source "board/freescale/ls1021aiot/Kconfig"
2372 source "board/freescale/ls1046aqds/Kconfig"
2373 source "board/freescale/ls1043ardb/Kconfig"
2374 source "board/freescale/ls1046ardb/Kconfig"
2375 source "board/freescale/ls1046afrwy/Kconfig"
2376 source "board/freescale/ls1012aqds/Kconfig"
2377 source "board/freescale/ls1012ardb/Kconfig"
2378 source "board/freescale/ls1012afrdm/Kconfig"
2379 source "board/freescale/lx2160a/Kconfig"
2380 source "board/grinn/chiliboard/Kconfig"
2381 source "board/hisilicon/hikey/Kconfig"
2382 source "board/hisilicon/hikey960/Kconfig"
2383 source "board/hisilicon/poplar/Kconfig"
2384 source "board/isee/igep003x/Kconfig"
2385 source "board/kontron/sl28/Kconfig"
2386 source "board/myir/mys_6ulx/Kconfig"
2387 source "board/samsung/common/Kconfig"
2388 source "board/siemens/common/Kconfig"
2389 source "board/seeed/npi_imx6ull/Kconfig"
2390 source "board/socionext/developerbox/Kconfig"
2391 source "board/tcl/sl50/Kconfig"
2392 source "board/traverse/ten64/Kconfig"
2393 source "board/variscite/dart_6ul/Kconfig"
2394 source "board/vscom/baltos/Kconfig"
2395 source "board/phytium/durian/Kconfig"
2396 source "board/phytium/pomelo/Kconfig"
2397 source "board/phytium/pe2201/Kconfig"
2398 source "board/xen/xenguest_arm64/Kconfig"
2400 source "arch/arm/Kconfig.debug"