include/configs/ids8313.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2013
   4  * Heiko Schocher, DENX Software Engineering, [email protected].
   5  *
   6  * Based on:
   7  * Copyright (c) 2011 IDS GmbH, Germany
   8  * Sergej Stepanov <[email protected]>
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17 #define CONFIG_MPC831x
  18 #define CONFIG_MPC8313
  19
  20 #define CONFIG_FSL_ELBC
  21
  22 #define CONFIG_BOOT_RETRY_TIME          900
  23 #define CONFIG_BOOT_RETRY_MIN           30
  24 #define CONFIG_RESET_TO_RETRY
  25
  26 #define CONFIG_83XX_CLKIN               66000000        /* in Hz */
  27 #define CONFIG_SYS_CLK_FREQ             CONFIG_83XX_CLKIN
  28
  29 #define CONFIG_SYS_IMMR         0xF0000000
  30
  31 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  32 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  33
  34 /*
  35  * Hardware Reset Configuration Word
  36  * if CLKIN is 66.000MHz, then
  37  * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
  38  */
  39 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
  40                              HRCWL_DDR_TO_SCB_CLK_2X1 |\
  41                              HRCWL_CSB_TO_CLKIN_2X1 |\
  42                              HRCWL_CORE_TO_CSB_2X1)
  43
  44 #define CONFIG_SYS_HRCW_HIGH    (HRCWH_PCI_HOST |\
  45                                  HRCWH_CORE_ENABLE |\
  46                                  HRCWH_FROM_0XFFF00100 |\
  47                                  HRCWH_BOOTSEQ_DISABLE |\
  48                                  HRCWH_SW_WATCHDOG_DISABLE |\
  49                                  HRCWH_ROM_LOC_LOCAL_8BIT |\
  50                                  HRCWH_RL_EXT_LEGACY |\
  51                                  HRCWH_TSEC1M_IN_MII |\
  52                                  HRCWH_TSEC2M_IN_MII |\
  53                                  HRCWH_BIG_ENDIAN)
  54
  55 #define CONFIG_SYS_SICRH        0x00000000
  56 #define CONFIG_SYS_SICRL        (SICRL_LBC | SICRL_SPI_D)
  57
  58 #define CONFIG_HWCONFIG
  59
  60 #define CONFIG_SYS_HID0_INIT    0x000000000
  61 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK |\
  62                                  HID0_ENABLE_INSTRUCTION_CACHE |\
  63                                  HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
  64
  65 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
  66
  67 /*
  68  * Definitions for initial stack pointer and data area (in DCACHE )
  69  */
  70 #define CONFIG_SYS_INIT_RAM_LOCK
  71 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
  72 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* End of used area in DPRAM */
  73 #define CONFIG_SYS_GBL_DATA_SIZE        0x100
  74 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
  75                                          - CONFIG_SYS_GBL_DATA_SIZE)
  76 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  77
  78 /*
  79  * Local Bus LCRR and LBCR regs
  80  */
  81 #define CONFIG_SYS_LCRR_EADC            LCRR_EADC_1
  82 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
  83 #define CONFIG_SYS_LBC_LBCR             (0x00040000 |\
  84                                          (0xFF << LBCR_BMT_SHIFT) |\
  85                                          0xF)
  86
  87 #define CONFIG_SYS_LBC_MRTPR            0x20000000
  88
  89 /*
  90  * Internal Definitions
  91  */
  92 /*
  93  * DDR Setup
  94  */
  95 #define CONFIG_SYS_DDR_BASE             0x00000000
  96 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  97 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  98
  99 /*
 100  * Manually set up DDR parameters,
 101  * as this board has not the SPD connected to I2C.
 102  */
 103 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 104 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN |\
 105                                          0x00010000 |\
 106                                          CSCONFIG_ROW_BIT_13 |\
 107                                          CSCONFIG_COL_BIT_10)
 108
 109 #define CONFIG_SYS_DDR_CONFIG_256       (CONFIG_SYS_DDR_CONFIG | \
 110                                          CSCONFIG_BANK_BIT_3)
 111
 112 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16)       /* ext refrec */
 113 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
 114                                 (3 << TIMING_CFG0_WRT_SHIFT) |\
 115                                 (3 << TIMING_CFG0_RRT_SHIFT) |\
 116                                 (3 << TIMING_CFG0_WWT_SHIFT) |\
 117                                 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
 118                                 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
 119                                 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 120                                 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 121 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
 122                                 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
 123                                 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
 124                                 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
 125                                 (4 << TIMING_CFG1_REFREC_SHIFT) |\
 126                                 (4 << TIMING_CFG1_WRREC_SHIFT) |\
 127                                 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
 128                                 (2 << TIMING_CFG1_WRTORD_SHIFT))
 129 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
 130                                 (5 << TIMING_CFG2_CPO_SHIFT) |\
 131                                 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
 132                                 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
 133                                 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
 134                                 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
 135                                 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 136
 137 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
 138                                 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 139
 140 #define CONFIG_SYS_SDRAM_CFG            (SDRAM_CFG_SREN |\
 141                                          SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
 142                                          SDRAM_CFG_DBW_32 |\
 143                                          SDRAM_CFG_SDRAM_TYPE_DDR2)
 144
 145 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 146 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
 147                                          (0x0242 << SDRAM_MODE_SD_SHIFT))
 148 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 149 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
 150 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
 151                                          DDRCDR_PZ_NOMZ |\
 152                                          DDRCDR_NZ_NOMZ |\
 153                                          DDRCDR_ODT |\
 154                                          DDRCDR_M_ODR |\
 155                                          DDRCDR_Q_DRN)
 156
 157 /*
 158  * on-board devices
 159  */
 160 #define CONFIG_TSEC1
 161 #define CONFIG_TSEC2
 162 #define CONFIG_HARD_SPI
 163
 164 /*
 165  * NOR FLASH setup
 166  */
 167 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_8BIT
 168 #define CONFIG_FLASH_SHOW_PROGRESS      50
 169
 170 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 171 #define CONFIG_SYS_FLASH_SIZE           8
 172
 173 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 174 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016
 175
 176 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE |\
 177                                          BR_PS_8 |\
 178                                          BR_MS_GPCM |\
 179                                          BR_V)
 180
 181 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
 182                                          OR_GPCM_SCY_10 |\
 183                                          OR_GPCM_EHTR |\
 184                                          OR_GPCM_TRLX |\
 185                                          OR_GPCM_CSNT |\
 186                                          OR_GPCM_EAD)
 187 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 188 #define CONFIG_SYS_MAX_FLASH_SECT       128
 189
 190 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000
 191 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
 192
 193 /*
 194  * NAND FLASH setup
 195  */
 196 #define CONFIG_SYS_NAND_BASE            0xE1000000
 197 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 198 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 199 #define CONFIG_NAND_FSL_ELBC
 200 #define CONFIG_SYS_NAND_PAGE_SIZE       (2048)
 201 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 202 #define NAND_CACHE_PAGES                64
 203
 204 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 205 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E
 206 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 207 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM  CONFIG_SYS_LBLAWAR1_PRELIM
 208
 209 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_NAND_BASE) |\
 210                                  (2<<BR_DECC_SHIFT) |\
 211                                  BR_PS_8 |\
 212                                  BR_MS_FCM |\
 213                                  BR_V)
 214
 215 #define CONFIG_SYS_OR1_PRELIM   (0xFFFF8000 |\
 216                                  OR_FCM_PGS |\
 217                                  OR_FCM_CSCT |\
 218                                  OR_FCM_CST |\
 219                                  OR_FCM_CHT |\
 220                                  OR_FCM_SCY_4 |\
 221                                  OR_FCM_TRLX |\
 222                                  OR_FCM_EHTR |\
 223                                  OR_FCM_RST)
 224
 225 /*
 226  * MRAM setup
 227  */
 228 #define CONFIG_SYS_MRAM_BASE            0xE2000000
 229 #define CONFIG_SYS_MRAM_SIZE            0x20000 /* 128 Kb */
 230 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_MRAM_BASE
 231 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000010      /* 128 Kb  */
 232
 233 #define CONFIG_SYS_OR_TIMING_MRAM
 234
 235 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_MRAM_BASE |\
 236                                          BR_PS_8 |\
 237                                          BR_MS_GPCM |\
 238                                          BR_V)
 239
 240 #define CONFIG_SYS_OR2_PRELIM           0xFFFE0C74
 241
 242 /*
 243  * CPLD setup
 244  */
 245 #define CONFIG_SYS_CPLD_BASE            0xE3000000
 246 #define CONFIG_SYS_CPLD_SIZE            0x8000
 247 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CPLD_BASE
 248 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000E
 249
 250 #define CONFIG_SYS_OR_TIMING_MRAM
 251
 252 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_CPLD_BASE |\
 253                                          BR_PS_8 |\
 254                                          BR_MS_GPCM |\
 255                                          BR_V)
 256
 257 #define CONFIG_SYS_OR3_PRELIM           0xFFFF8814
 258
 259 /*
 260  * HW-Watchdog
 261  */
 262 #define CONFIG_WATCHDOG         1
 263 #define CONFIG_SYS_WATCHDOG_VALUE       0xFFFF
 264
 265 /*
 266  * I2C setup
 267  */
 268 #define CONFIG_SYS_I2C
 269 #define CONFIG_SYS_I2C_FSL
 270 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 271 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 272 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 273 #define CONFIG_RTC_PCF8563
 274 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 275
 276 /*
 277  * SPI setup
 278  */
 279 #ifdef CONFIG_HARD_SPI
 280 #define CONFIG_SYS_GPIO1_PRELIM
 281 #define CONFIG_SYS_GPIO1_DIR            0x00000001
 282 #define CONFIG_SYS_GPIO1_DAT            0x00000001
 283 #endif
 284
 285 /*
 286  * Ethernet setup
 287  */
 288 #ifdef CONFIG_TSEC1
 289 #define CONFIG_HAS_ETH0
 290 #define CONFIG_TSEC1_NAME               "TSEC0"
 291 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 292 #define TSEC1_PHY_ADDR                  0x1
 293 #define TSEC1_FLAGS                     TSEC_GIGABIT
 294 #define TSEC1_PHYIDX                    0
 295 #endif
 296
 297 #ifdef CONFIG_TSEC2
 298 #define CONFIG_HAS_ETH1
 299 #define CONFIG_TSEC2_NAME               "TSEC1"
 300 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 301 #define TSEC2_PHY_ADDR                  0x3
 302 #define TSEC2_FLAGS                     TSEC_GIGABIT
 303 #define TSEC2_PHYIDX                    0
 304 #endif
 305 #define CONFIG_ETHPRIME         "TSEC1"
 306
 307 /*
 308  * Serial Port
 309  */
 310 #define CONFIG_SYS_NS16550_SERIAL
 311 #define CONFIG_SYS_NS16550_REG_SIZE     1
 312
 313 #define CONFIG_SYS_BAUDRATE_TABLE       \
 314         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 315 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 316 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 317 #define CONFIG_SYS_NS16550_CLK          (CONFIG_83XX_CLKIN * 2)
 318
 319 #define CONFIG_HAS_FSL_DR_USB
 320 #define CONFIG_SYS_SCCR_USBDRCM 3
 321
 322 /*
 323  * BAT's
 324  */
 325 #define CONFIG_HIGH_BATS
 326
 327 /* DDR @ 0x00000000 */
 328 #define CONFIG_SYS_IBAT0L               (CONFIG_SYS_SDRAM_BASE |\
 329                                          BATL_PP_10)
 330 #define CONFIG_SYS_IBAT0U               (CONFIG_SYS_SDRAM_BASE |\
 331                                          BATU_BL_256M |\
 332                                          BATU_VS |\
 333                                          BATU_VP)
 334 #define CONFIG_SYS_DBAT0L               CONFIG_SYS_IBAT0L
 335 #define CONFIG_SYS_DBAT0U               CONFIG_SYS_IBAT0U
 336
 337 /* Initial RAM @ 0xFD000000 */
 338 #define CONFIG_SYS_IBAT1L               (CONFIG_SYS_INIT_RAM_ADDR |\
 339                                          BATL_PP_10 |\
 340                                          BATL_GUARDEDSTORAGE)
 341 #define CONFIG_SYS_IBAT1U               (CONFIG_SYS_INIT_RAM_ADDR |\
 342                                          BATU_BL_256K |\
 343                                          BATU_VS |\
 344                                          BATU_VP)
 345 #define CONFIG_SYS_DBAT1L               CONFIG_SYS_IBAT1L
 346 #define CONFIG_SYS_DBAT1U               CONFIG_SYS_IBAT1U
 347
 348 /* FLASH @ 0xFF800000 */
 349 #define CONFIG_SYS_IBAT2L               (CONFIG_SYS_FLASH_BASE |\
 350                                          BATL_PP_10 |\
 351                                          BATL_GUARDEDSTORAGE)
 352 #define CONFIG_SYS_IBAT2U               (CONFIG_SYS_FLASH_BASE |\
 353                                          BATU_BL_8M |\
 354                                          BATU_VS |\
 355                                          BATU_VP)
 356 #define CONFIG_SYS_DBAT2L               (CONFIG_SYS_FLASH_BASE |\
 357                                          BATL_PP_10 |\
 358                                          BATL_CACHEINHIBIT |\
 359                                          BATL_GUARDEDSTORAGE)
 360 #define CONFIG_SYS_DBAT2U               CONFIG_SYS_IBAT2U
 361
 362 #define CONFIG_SYS_IBAT3L               (0)
 363 #define CONFIG_SYS_IBAT3U               (0)
 364 #define CONFIG_SYS_DBAT3L               CONFIG_SYS_IBAT3L
 365 #define CONFIG_SYS_DBAT3U               CONFIG_SYS_IBAT3U
 366
 367 #define CONFIG_SYS_IBAT4L               (0)
 368 #define CONFIG_SYS_IBAT4U               (0)
 369 #define CONFIG_SYS_DBAT4L               CONFIG_SYS_IBAT4L
 370 #define CONFIG_SYS_DBAT4U               CONFIG_SYS_IBAT4U
 371
 372 /* IMMRBAR @ 0xF0000000 */
 373 #define CONFIG_SYS_IBAT5L               (CONFIG_SYS_IMMR |\
 374                                          BATL_PP_10 |\
 375                                          BATL_CACHEINHIBIT |\
 376                                          BATL_GUARDEDSTORAGE)
 377 #define CONFIG_SYS_IBAT5U               (CONFIG_SYS_IMMR |\
 378                                          BATU_BL_128M |\
 379                                          BATU_VS |\
 380                                          BATU_VP)
 381 #define CONFIG_SYS_DBAT5L               CONFIG_SYS_IBAT5L
 382 #define CONFIG_SYS_DBAT5U               CONFIG_SYS_IBAT5U
 383
 384 /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
 385 #define CONFIG_SYS_IBAT6L               (0xE0000000 |\
 386                                          BATL_PP_10 |\
 387                                          BATL_GUARDEDSTORAGE)
 388 #define CONFIG_SYS_IBAT6U               (0xE0000000 |\
 389                                          BATU_BL_256M |\
 390                                          BATU_VS |\
 391                                          BATU_VP)
 392 #define CONFIG_SYS_DBAT6L               CONFIG_SYS_IBAT6L
 393 #define CONFIG_SYS_DBAT6U               CONFIG_SYS_IBAT6U
 394
 395 #define CONFIG_SYS_IBAT7L               (0)
 396 #define CONFIG_SYS_IBAT7U               (0)
 397 #define CONFIG_SYS_DBAT7L               CONFIG_SYS_IBAT7L
 398 #define CONFIG_SYS_DBAT7U               CONFIG_SYS_IBAT7U
 399
 400 /*
 401  * U-Boot environment setup
 402  */
 403 #define CONFIG_BOOTP_BOOTFILESIZE
 404
 405 /*
 406  * The reserved memory
 407  */
 408 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 409 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 410 #define CONFIG_SYS_MALLOC_LEN           (8 * 1024 * 1024)
 411
 412 /*
 413  * Environment Configuration
 414  */
 415 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
 416                                 + CONFIG_SYS_MONITOR_LEN)
 417 #define CONFIG_ENV_SIZE         0x20000
 418 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
 419 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 420
 421 #define CONFIG_NETDEV                   eth1
 422 #define CONFIG_HOSTNAME         "ids8313"
 423 #define CONFIG_ROOTPATH         "/opt/eldk-4.2/ppc_6xx"
 424 #define CONFIG_BOOTFILE         "ids8313/uImage"
 425 #define CONFIG_UBOOTPATH                "ids8313/u-boot.bin"
 426 #define CONFIG_FDTFILE                  "ids8313/ids8313.dtb"
 427 #define CONFIG_LOADADDR         0x400000
 428 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
 429
 430 /* Initial Memory map for Linux*/
 431 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 432
 433 /*
 434  * Miscellaneous configurable options
 435  */
 436 #define CONFIG_SYS_CBSIZE               1024
 437 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 438
 439 #define CONFIG_SYS_MEMTEST_START        0x00001000
 440 #define CONFIG_SYS_MEMTEST_END          0x00C00000
 441
 442 #define CONFIG_SYS_LOAD_ADDR            0x100000
 443 #define CONFIG_LOADS_ECHO
 444 #define CONFIG_TIMESTAMP
 445 #define CONFIG_PREBOOT                  "echo;" \
 446                                         "echo Type \\\"run nfsboot\\\" " \
 447                                         "to mount root filesystem over NFS;echo"
 448 #define CONFIG_BOOTCOMMAND              "run boot_cramfs"
 449 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
 450
 451 #define CONFIG_JFFS2_NAND
 452 #define CONFIG_JFFS2_DEV                "0"
 453
 454 /* mtdparts command line support */
 455
 456 #define CONFIG_EXTRA_ENV_SETTINGS \
 457         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
 458         "ethprime=TSEC1\0"                                              \
 459         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 460         "tftpflash=tftpboot ${loadaddr} ${uboot}; "                     \
 461                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 462                 " +${filesize}; "                                       \
 463                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 464                 " +${filesize}; "                                       \
 465                 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)   \
 466                 " ${filesize}; "                                        \
 467                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 468                 " +${filesize}; "                                       \
 469                 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)  \
 470                 " ${filesize}\0"                                        \
 471         "console=ttyS0\0"                                               \
 472         "fdtaddr=0x780000\0"                                            \
 473         "kernel_addr=ff800000\0"                                        \
 474         "fdtfile=" __stringify(CONFIG_FDTFILE) "\0"                     \
 475         "setbootargs=setenv bootargs "                                  \
 476                 "root=${rootdev} rw console=${console},"                \
 477                         "${baudrate} ${othbootargs}\0"                  \
 478         "setipargs=setenv bootargs root=${rootdev} rw "                 \
 479                         "nfsroot=${serverip}:${rootpath} "              \
 480                         "ip=${ipaddr}:${serverip}:${gatewayip}:"        \
 481                         "${netmask}:${hostname}:${netdev}:off "         \
 482                         "console=${console},${baudrate} ${othbootargs}\0" \
 483         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 484         "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"                                    \
 485         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"                                \
 486         "\0"
 487
 488 #define CONFIG_NFSBOOTCOMMAND                                           \
 489         "setenv rootdev /dev/nfs;"                                      \
 490         "run setipargs;run addmtd;"                                     \
 491         "tftp ${loadaddr} ${bootfile};"                         \
 492         "tftp ${fdtaddr} ${fdtfile};"                                   \
 493         "fdt addr ${fdtaddr};"                                          \
 494         "bootm ${loadaddr} - ${fdtaddr}"
 495
 496 /* UBI Support */
 497
 498 #endif  /* __CONFIG_H */