board/freescale/ls2080ardb/ls2080ardb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor
   4  * Copyright 2017 NXP
   5  */
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <env.h>
   9 #include <init.h>
  10 #include <malloc.h>
  11 #include <errno.h>
  12 #include <netdev.h>
  13 #include <fsl_ifc.h>
  14 #include <fsl_ddr.h>
  15 #include <asm/global_data.h>
  16 #include <asm/io.h>
  17 #include <hwconfig.h>
  18 #include <fdt_support.h>
  19 #include <linux/libfdt.h>
  20 #include <fsl-mc/fsl_mc.h>
  21 #include <env_internal.h>
  22 #include <efi_loader.h>
  23 #include <i2c.h>
  24 #include <asm/arch/mmu.h>
  25 #include <asm/arch/soc.h>
  26 #include <asm/arch/ppa.h>
  27 #include <fsl_sec.h>
  28 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  29 #include "../common/i2c_mux.h"
  30
  31 #ifdef CONFIG_FSL_QIXIS
  32 #include "../common/qixis.h"
  33 #include "ls2080ardb_qixis.h"
  34 #endif
  35 #include "../common/vid.h"
  36
  37 #define CORTINA_FW_ADDR_IFCNOR                  0x580980000
  38 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK  0x584980000
  39 #define CORTINA_FW_ADDR_QSPI                    0x980000
  40 #define PIN_MUX_SEL_SDHC        0x00
  41 #define PIN_MUX_SEL_DSPI        0x0a
  42
  43 #define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0xf0) | value)
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 enum {
  47         MUX_TYPE_SDHC,
  48         MUX_TYPE_DSPI,
  49 };
  50
  51 #ifdef CONFIG_VID
  52 u16 soc_get_fuse_vid(int vid_index)
  53 {
  54         static const u16 vdd[32] = {
  55                 10500,
  56                 0,      /* reserved */
  57                 9750,
  58                 0,      /* reserved */
  59                 9500,
  60                 0,      /* reserved */
  61                 0,      /* reserved */
  62                 0,      /* reserved */
  63                 9000,   /* reserved */
  64                 0,      /* reserved */
  65                 0,      /* reserved */
  66                 0,      /* reserved */
  67                 0,      /* reserved */
  68                 0,      /* reserved */
  69                 0,      /* reserved */
  70                 0,      /* reserved */
  71                 10000,  /* 1.0000V */
  72                 0,      /* reserved */
  73                 10250,
  74                 0,      /* reserved */
  75                 10500,
  76                 0,      /* reserved */
  77                 0,      /* reserved */
  78                 0,      /* reserved */
  79                 0,      /* reserved */
  80                 0,      /* reserved */
  81                 0,      /* reserved */
  82                 0,      /* reserved */
  83                 0,      /* reserved */
  84                 0,      /* reserved */
  85                 0,      /* reserved */
  86                 0,      /* reserved */
  87         };
  88
  89         return vdd[vid_index];
  90 };
  91 #endif
  92
  93 unsigned long long get_qixis_addr(void)
  94 {
  95         unsigned long long addr;
  96
  97         if (gd->flags & GD_FLG_RELOC)
  98                 addr = QIXIS_BASE_PHYS;
  99         else
 100                 addr = QIXIS_BASE_PHYS_EARLY;
 101
 102         /*
 103          * IFC address under 256MB is mapped to 0x30000000, any address above
 104          * is mapped to 0x5_10000000 up to 4GB.
 105          */
 106         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
 107
 108         return addr;
 109 }
 110
 111 int checkboard(void)
 112 {
 113 #ifdef CONFIG_FSL_QIXIS
 114         u8 sw;
 115 #endif
 116         char buf[15];
 117
 118         cpu_name(buf);
 119         printf("Board: %s-RDB, ", buf);
 120
 121 #ifdef CONFIG_TARGET_LS2081ARDB
 122 #ifdef CONFIG_FSL_QIXIS
 123         sw = QIXIS_READ(arch);
 124         printf("Board version: %c, ", (sw & 0xf) + 'A');
 125
 126         sw = QIXIS_READ(brdcfg[0]);
 127         sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
 128         switch (sw) {
 129         case 0:
 130                 puts("boot from QSPI DEV#0\n");
 131                 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
 132                 break;
 133         case 1:
 134                 puts("boot from QSPI DEV#1\n");
 135                 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
 136                 break;
 137         case 2:
 138                 puts("boot from QSPI EMU\n");
 139                 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
 140                 break;
 141         case 3:
 142                 puts("boot from QSPI EMU\n");
 143                 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
 144                 break;
 145         case 4:
 146                 puts("boot from QSPI DEV#0\n");
 147                 puts("QSPI_CSA_1 mapped to QSPI EMU\n");
 148                 break;
 149         default:
 150                 printf("invalid setting of SW%u\n", sw);
 151                 break;
 152         }
 153         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 154 #endif
 155         puts("SERDES1 Reference : ");
 156         printf("Clock1 = 100MHz ");
 157         printf("Clock2 = 161.13MHz");
 158 #else
 159 #ifdef CONFIG_FSL_QIXIS
 160         sw = QIXIS_READ(arch);
 161         printf("Board Arch: V%d, ", sw >> 4);
 162         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 163
 164         sw = QIXIS_READ(brdcfg[0]);
 165         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 166
 167         if (sw < 0x8)
 168                 printf("vBank: %d\n", sw);
 169         else if (sw == 0x9)
 170                 puts("NAND\n");
 171         else
 172                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 173
 174         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 175 #endif
 176         puts("SERDES1 Reference : ");
 177         printf("Clock1 = 156.25MHz ");
 178         printf("Clock2 = 156.25MHz");
 179 #endif
 180
 181         puts("\nSERDES2 Reference : ");
 182         printf("Clock1 = 100MHz ");
 183         printf("Clock2 = 100MHz\n");
 184
 185         return 0;
 186 }
 187
 188 unsigned long get_board_sys_clk(void)
 189 {
 190 #ifdef CONFIG_FSL_QIXIS
 191         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 192
 193         switch (sysclk_conf & 0x0F) {
 194         case QIXIS_SYSCLK_83:
 195                 return 83333333;
 196         case QIXIS_SYSCLK_100:
 197                 return 100000000;
 198         case QIXIS_SYSCLK_125:
 199                 return 125000000;
 200         case QIXIS_SYSCLK_133:
 201                 return 133333333;
 202         case QIXIS_SYSCLK_150:
 203                 return 150000000;
 204         case QIXIS_SYSCLK_160:
 205                 return 160000000;
 206         case QIXIS_SYSCLK_166:
 207                 return 166666666;
 208         }
 209 #endif
 210         return 100000000;
 211 }
 212
 213 int i2c_multiplexer_select_vid_channel(u8 channel)
 214 {
 215         return select_i2c_ch_pca9547(channel, 0);
 216 }
 217
 218 int config_board_mux(int ctrl_type)
 219 {
 220 #ifdef CONFIG_FSL_QIXIS
 221         u8 reg5;
 222
 223         reg5 = QIXIS_READ(brdcfg[5]);
 224
 225         switch (ctrl_type) {
 226         case MUX_TYPE_SDHC:
 227                 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
 228                 break;
 229         case MUX_TYPE_DSPI:
 230                 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
 231                 break;
 232         default:
 233                 printf("Wrong mux interface type\n");
 234                 return -1;
 235         }
 236
 237         QIXIS_WRITE(brdcfg[5], reg5);
 238 #endif
 239         return 0;
 240 }
 241
 242 ulong *cs4340_get_fw_addr(void)
 243 {
 244 #ifdef CONFIG_TFABOOT
 245         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 246         u32 svr = gur_in32(&gur->svr);
 247 #endif
 248         ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
 249
 250 #ifdef CONFIG_TFABOOT
 251         /* LS2088A TFA boot */
 252         if (SVR_SOC_VER(svr) == SVR_LS2088A) {
 253                 enum boot_src src = get_boot_src();
 254                 u8 sw;
 255
 256                 switch (src) {
 257                 case BOOT_SOURCE_IFC_NOR:
 258                         sw = QIXIS_READ(brdcfg[0]);
 259                         sw = (sw & 0x0f);
 260                         if (sw == 0)
 261                                 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
 262                         else if (sw == 4)
 263                                 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
 264                         break;
 265                 case BOOT_SOURCE_QSPI_NOR:
 266                         /* Only one bank in QSPI */
 267                         cortina_fw_addr = CORTINA_FW_ADDR_QSPI;
 268                         break;
 269                 default:
 270                         printf("WARNING: Boot source not found\n");
 271                 }
 272         }
 273 #endif
 274         return (ulong *)cortina_fw_addr;
 275 }
 276
 277 int board_init(void)
 278 {
 279 #ifdef CONFIG_FSL_MC_ENET
 280         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 281 #endif
 282
 283         init_final_memctl_regs();
 284
 285         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 286
 287 #ifdef CONFIG_FSL_QIXIS
 288         QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 289 #endif
 290
 291 #ifdef CONFIG_FSL_CAAM
 292         sec_init();
 293 #endif
 294 #ifdef CONFIG_FSL_LS_PPA
 295         ppa_init();
 296 #endif
 297
 298 #ifdef CONFIG_FSL_MC_ENET
 299         /* invert AQR405 IRQ pins polarity */
 300         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 301 #endif
 302 #ifdef CONFIG_FSL_CAAM
 303         sec_init();
 304 #endif
 305
 306 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 307         pci_init();
 308 #endif
 309
 310         return 0;
 311 }
 312
 313 int board_early_init_f(void)
 314 {
 315 #if defined(CONFIG_SYS_I2C_EARLY_INIT)
 316         i2c_early_init_f();
 317 #endif
 318         fsl_lsch3_early_init_f();
 319         return 0;
 320 }
 321
 322 int misc_init_r(void)
 323 {
 324         char *env_hwconfig;
 325         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 326         u32 val;
 327         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 328         u32 svr = gur_in32(&gur->svr);
 329
 330         val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
 331
 332         env_hwconfig = env_get("hwconfig");
 333
 334         if (hwconfig_f("dspi", env_hwconfig) &&
 335             DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
 336                 config_board_mux(MUX_TYPE_DSPI);
 337         else
 338                 config_board_mux(MUX_TYPE_SDHC);
 339
 340         /*
 341          * LS2081ARDB RevF board has smart voltage translator
 342          * which needs to be programmed to enable high speed SD interface
 343          * by setting GPIO4_10 output to zero
 344          */
 345 #ifdef CONFIG_TARGET_LS2081ARDB
 346                 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
 347                                             in_le32(GPIO4_GPDIR_ADDR)));
 348                 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
 349                                             in_le32(GPIO4_GPDAT_ADDR)));
 350 #endif
 351         if (hwconfig("sdhc"))
 352                 config_board_mux(MUX_TYPE_SDHC);
 353
 354         if (adjust_vdd(0))
 355                 printf("Warning: Adjusting core voltage failed.\n");
 356         /*
 357          * Default value of board env is based on filename which is
 358          * ls2080ardb. Modify board env for other supported SoCs
 359          */
 360         if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
 361             (SVR_SOC_VER(svr) == SVR_LS2048A))
 362                 env_set("board", "ls2088ardb");
 363         else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
 364             (SVR_SOC_VER(svr) == SVR_LS2041A))
 365                 env_set("board", "ls2081ardb");
 366
 367         return 0;
 368 }
 369
 370 void detail_board_ddr_info(void)
 371 {
 372         puts("\nDDR    ");
 373         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 374         print_ddr_info(0);
 375 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 376         if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
 377                 puts("\nDP-DDR ");
 378                 print_size(gd->bd->bi_dram[2].size, "");
 379                 print_ddr_info(CONFIG_DP_DDR_CTRL);
 380         }
 381 #endif
 382 }
 383
 384 #ifdef CONFIG_FSL_MC_ENET
 385 void fdt_fixup_board_enet(void *fdt)
 386 {
 387         int offset;
 388
 389         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 390
 391         if (offset < 0)
 392                 offset = fdt_path_offset(fdt, "/fsl-mc");
 393
 394         if (offset < 0) {
 395                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 396                        __func__, offset);
 397                 return;
 398         }
 399
 400         if (get_mc_boot_status() == 0 &&
 401             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 402                 fdt_status_okay(fdt, offset);
 403         else
 404                 fdt_status_fail(fdt, offset);
 405 }
 406
 407 void board_quiesce_devices(void)
 408 {
 409         fsl_mc_ldpaa_exit(gd->bd);
 410 }
 411 #endif
 412
 413 #ifdef CONFIG_OF_BOARD_SETUP
 414 void fsl_fdt_fixup_flash(void *fdt)
 415 {
 416         int offset;
 417 #ifdef CONFIG_TFABOOT
 418         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 419         u32 val;
 420 #endif
 421
 422 /*
 423  * IFC and QSPI are muxed on board.
 424  * So disable IFC node in dts if QSPI is enabled or
 425  * disable QSPI node in dts in case QSPI is not enabled.
 426  */
 427 #ifdef CONFIG_TFABOOT
 428         enum boot_src src = get_boot_src();
 429         bool disable_ifc = false;
 430
 431         switch (src) {
 432         case BOOT_SOURCE_IFC_NOR:
 433                 disable_ifc = false;
 434                 break;
 435         case BOOT_SOURCE_QSPI_NOR:
 436                 disable_ifc = true;
 437                 break;
 438         default:
 439                 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
 440                 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
 441                         disable_ifc = true;
 442                 break;
 443         }
 444
 445         if (disable_ifc) {
 446                 offset = fdt_path_offset(fdt, "/soc/ifc");
 447
 448                 if (offset < 0)
 449                         offset = fdt_path_offset(fdt, "/ifc");
 450         } else {
 451                 offset = fdt_path_offset(fdt, "/soc/quadspi");
 452
 453                 if (offset < 0)
 454                         offset = fdt_path_offset(fdt, "/quadspi");
 455         }
 456
 457 #else
 458 #ifdef CONFIG_FSL_QSPI
 459         offset = fdt_path_offset(fdt, "/soc/ifc");
 460
 461         if (offset < 0)
 462                 offset = fdt_path_offset(fdt, "/ifc");
 463 #else
 464         offset = fdt_path_offset(fdt, "/soc/quadspi");
 465
 466         if (offset < 0)
 467                 offset = fdt_path_offset(fdt, "/quadspi");
 468 #endif
 469 #endif
 470
 471         if (offset < 0)
 472                 return;
 473
 474         fdt_status_disabled(fdt, offset);
 475 }
 476
 477 int ft_board_setup(void *blob, struct bd_info *bd)
 478 {
 479         int i;
 480         u16 mc_memory_bank = 0;
 481
 482         u64 *base;
 483         u64 *size;
 484         u64 mc_memory_base = 0;
 485         u64 mc_memory_size = 0;
 486         u16 total_memory_banks;
 487
 488         ft_cpu_setup(blob, bd);
 489
 490         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 491
 492         if (mc_memory_base != 0)
 493                 mc_memory_bank++;
 494
 495         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 496
 497         base = calloc(total_memory_banks, sizeof(u64));
 498         size = calloc(total_memory_banks, sizeof(u64));
 499
 500         /* fixup DT for the two GPP DDR banks */
 501         base[0] = gd->bd->bi_dram[0].start;
 502         size[0] = gd->bd->bi_dram[0].size;
 503         base[1] = gd->bd->bi_dram[1].start;
 504         size[1] = gd->bd->bi_dram[1].size;
 505
 506 #ifdef CONFIG_RESV_RAM
 507         /* reduce size if reserved memory is within this bank */
 508         if (gd->arch.resv_ram >= base[0] &&
 509             gd->arch.resv_ram < base[0] + size[0])
 510                 size[0] = gd->arch.resv_ram - base[0];
 511         else if (gd->arch.resv_ram >= base[1] &&
 512                  gd->arch.resv_ram < base[1] + size[1])
 513                 size[1] = gd->arch.resv_ram - base[1];
 514 #endif
 515
 516         if (mc_memory_base != 0) {
 517                 for (i = 0; i <= total_memory_banks; i++) {
 518                         if (base[i] == 0 && size[i] == 0) {
 519                                 base[i] = mc_memory_base;
 520                                 size[i] = mc_memory_size;
 521                                 break;
 522                         }
 523                 }
 524         }
 525
 526         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 527
 528         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 529
 530         fsl_fdt_fixup_dr_usb(blob, bd);
 531
 532         fsl_fdt_fixup_flash(blob);
 533
 534 #ifdef CONFIG_FSL_MC_ENET
 535         fdt_fixup_board_enet(blob);
 536 #endif
 537
 538         fdt_fixup_icid(blob);
 539
 540         return 0;
 541 }
 542 #endif
 543
 544 void qixis_dump_switch(void)
 545 {
 546 #ifdef CONFIG_FSL_QIXIS
 547         int i, nr_of_cfgsw;
 548
 549         QIXIS_WRITE(cms[0], 0x00);
 550         nr_of_cfgsw = QIXIS_READ(cms[1]);
 551
 552         puts("DIP switch settings dump:\n");
 553         for (i = 1; i <= nr_of_cfgsw; i++) {
 554                 QIXIS_WRITE(cms[0], i);
 555                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 556         }
 557 #endif
 558 }
 559
 560 /*
 561  * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
 562  * Both slots has 0x54, resulting 2nd slot unusable.
 563  */
 564 void update_spd_address(unsigned int ctrl_num,
 565                         unsigned int slot,
 566                         unsigned int *addr)
 567 {
 568 #ifndef CONFIG_TARGET_LS2081ARDB
 569 #ifdef CONFIG_FSL_QIXIS
 570         u8 sw;
 571
 572         sw = QIXIS_READ(arch);
 573         if ((sw & 0xf) < 0x3) {
 574                 if (ctrl_num == 1 && slot == 0)
 575                         *addr = SPD_EEPROM_ADDRESS4;
 576                 else if (ctrl_num == 1 && slot == 1)
 577                         *addr = SPD_EEPROM_ADDRESS3;
 578         }
 579 #endif
 580 #endif
 581 }