2 * Copyright (C) 2012 Lucas Stach
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clock.h>
9 #include <asm/arch/funcmux.h>
10 #include <asm/arch/pinmux.h>
11 #include <asm/arch-tegra/ap.h>
12 #include <asm/arch-tegra/board.h>
13 #include <asm/arch-tegra/tegra.h>
18 #include "../common/tdx-common.h"
20 DECLARE_GLOBAL_DATA_PTR;
22 #define PMU_I2C_ADDRESS 0x34
23 #define MAX_I2C_RETRY 3
24 #define PMU_SUPPLYENE 0x14
25 #define PMU_SUPPLYENE_SYSINEN (1<<5)
26 #define PMU_SUPPLYENE_EXITSLREQ (1<<1)
28 int arch_misc_init(void)
30 /* Disable PMIC sleep mode on low supply voltage */
35 err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
37 debug("%s: Cannot find PMIC I2C chip\n", __func__);
43 err = dm_i2c_read(dev, addr, data, 1);
45 debug("failed to get PMU_SUPPLYENE\n");
49 data[0] &= ~PMU_SUPPLYENE_SYSINEN;
50 data[0] |= PMU_SUPPLYENE_EXITSLREQ;
52 err = dm_i2c_write(dev, addr, data, 1);
54 debug("failed to set PMU_SUPPLYENE\n");
58 /* make sure SODIMM pin 87 nRESET_OUT is released properly */
59 pinmux_set_func(PMUX_PINGRP_ATA, PMUX_FUNC_GMI);
61 if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
63 printf("USB recovery mode\n");
70 printf("Model: Toradex Colibri T20 %dMB V%s\n",
71 (gd->ram_size == 0x10000000) ? 256 : 512,
72 (get_nand_dev_by_index(0)->erasesize >> 10 == 512) ?
73 ((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A");
78 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
79 int ft_board_setup(void *blob, bd_t *bd)
81 return ft_common_board_setup(blob, bd);
85 #ifdef CONFIG_MMC_SDHCI_TEGRA
87 * Routine: pin_mux_mmc
88 * Description: setup the pin muxes/tristate values for the SDMMC(s)
90 void pin_mux_mmc(void)
92 funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
93 pinmux_tristate_disable(PMUX_PINGRP_GMB);
97 #ifdef CONFIG_TEGRA_NAND
98 void pin_mux_nand(void)
100 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
103 * configure pingroup ATC to something unrelated to
104 * avoid ATC overriding KBC
106 pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI);
110 #ifdef CONFIG_USB_EHCI_TEGRA
111 void pin_mux_usb(void)
113 /* module internal USB bus to connect ethernet chipset */
114 funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
116 /* ULPI reference clock output */
117 pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
118 pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
121 pinmux_tristate_disable(PMUX_PINGRP_UAC);
124 pinmux_tristate_disable(PMUX_PINGRP_DTE);
126 /* Reset ASIX using LAN_RESET */
127 gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET");
128 gpio_direction_output(TEGRA_GPIO(V, 4), 0);
129 pinmux_tristate_disable(PMUX_PINGRP_GPV);
131 gpio_set_value(TEGRA_GPIO(V, 4), 1);
133 /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
134 pinmux_tristate_disable(PMUX_PINGRP_SPIG);
138 #ifdef CONFIG_VIDEO_TEGRA20
140 * Routine: pin_mux_display
141 * Description: setup the pin muxes/tristate values for the LCD interface)
143 void pin_mux_display(void)
146 * Manually untristate BL_ON (PT4 - SODIMM 71) as specified through
149 pinmux_tristate_disable(PMUX_PINGRP_DTA);
151 pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
152 pinmux_tristate_disable(PMUX_PINGRP_SDC);