include/configs/caddy2.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * esd vme8349 U-Boot configuration file
   4  * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
   5  *
   6  * (C) Copyright 2006-2010
   7  * Wolfgang Denk, DENX Software Engineering, [email protected].
   8  *
   9  * [email protected]
  10  * Based on the MPC8349EMDS config.
  11  */
  12
  13 /*
  14  * vme8349 board configuration file.
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * High Level Configuration Options
  22  */
  23 #define CONFIG_E300             1       /* E300 Family */
  24
  25 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
  26 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  27
  28 #define CONFIG_SYS_IMMR         0xE0000000
  29
  30 #undef CONFIG_SYS_DRAM_TEST                     /* memory test, takes time */
  31 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  32 #define CONFIG_SYS_MEMTEST_END          0x00100000
  33
  34 /*
  35  * DDR Setup
  36  */
  37 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  38 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  39 #define CONFIG_SPD_EEPROM
  40 #define SPD_EEPROM_ADDRESS              0x54
  41 #define CONFIG_SYS_READ_SPD             vme8349_read_spd
  42 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* esd; Fsl board uses CS2/CS3 */
  43
  44 /*
  45  * 32-bit data path mode.
  46  *
  47  * Please note that using this mode for devices with the real density of 64-bit
  48  * effectively reduces the amount of available memory due to the effect of
  49  * wrapping around while translating address to row/columns, for example in the
  50  * 256MB module the upper 128MB get aliased with contents of the lower
  51  * 128MB); normally this define should be used for devices with real 32-bit
  52  * data path.
  53  */
  54 #undef CONFIG_DDR_32BIT
  55
  56 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is sys memory*/
  57 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  58 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  59 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  60                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  61 #define CONFIG_DDR_2T_TIMING
  62 #define CONFIG_SYS_DDRCDR               (DDRCDR_DHC_EN \
  63                                         | DDRCDR_ODT \
  64                                         | DDRCDR_Q_DRN)
  65                                         /* 0x80080001 */
  66
  67 /*
  68  * FLASH on the Local Bus
  69  */
  70 #define CONFIG_SYS_FLASH_BASE           0xffc00000      /* start of FLASH   */
  71 #define CONFIG_SYS_FLASH_SIZE           4               /* flash size in MB */
  72 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | \
  73                                          BR_PS_16 |     /*  16bit */ \
  74                                          BR_MS_GPCM |   /*  MSEL = GPCM */ \
  75                                          BR_V)          /* valid */
  76
  77 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
  78                                         | OR_GPCM_XAM \
  79                                         | OR_GPCM_CSNT \
  80                                         | OR_GPCM_ACS_DIV2 \
  81                                         | OR_GPCM_XACS \
  82                                         | OR_GPCM_SCY_15 \
  83                                         | OR_GPCM_TRLX_SET \
  84                                         | OR_GPCM_EHTR_SET \
  85                                         | OR_GPCM_EAD)
  86                                         /* 0xffc06ff7 */
  87 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
  88 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_4MB)
  89
  90 #define CONFIG_SYS_WINDOW1_BASE         0xf0000000
  91 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_WINDOW1_BASE \
  92                                         | BR_PS_32 \
  93                                         | BR_MS_GPCM \
  94                                         | BR_V)
  95                                         /* 0xF0001801 */
  96 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_256KB \
  97                                         | OR_GPCM_SETA)
  98                                         /* 0xfffc0208 */
  99 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_WINDOW1_BASE
 100 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_256KB)
 101
 102 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 103 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device*/
 104
 105 #undef CONFIG_SYS_FLASH_CHECKSUM
 106 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase TO (ms) */
 107 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write TO (ms) */
 108
 109 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 110
 111 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 112 #define CONFIG_SYS_RAMBOOT
 113 #else
 114 #undef CONFIG_SYS_RAMBOOT
 115 #endif
 116
 117 #define CONFIG_SYS_INIT_RAM_LOCK        1
 118 #define CONFIG_SYS_INIT_RAM_ADDR        0xF7000000      /* Initial RAM addr */
 119 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000          /* size */
 120
 121 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 122                                          GENERATED_GBL_DATA_SIZE)
 123 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 124
 125 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB */
 126 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Malloc size */
 127
 128 /*
 129  * Local Bus LCRR and LBCR regs
 130  *    LCRR:  no DLL bypass, Clock divider is 4
 131  * External Local Bus rate is
 132  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 133  */
 134 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 135 #define CONFIG_SYS_LBC_LBCR     0x00000000
 136
 137 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 138
 139 /*
 140  * Serial Port
 141  */
 142 #define CONFIG_SYS_NS16550_SERIAL
 143 #define CONFIG_SYS_NS16550_REG_SIZE     1
 144 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 145
 146 #define CONFIG_SYS_BAUDRATE_TABLE  \
 147                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 148
 149 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR + 0x4500)
 150 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR + 0x4600)
 151
 152 /* I2C */
 153 #define CONFIG_SYS_I2C
 154 #define CONFIG_SYS_I2C_FSL
 155 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 156 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 157 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 158 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 159 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 160 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 161 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 162 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 163
 164 #define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
 165
 166 /* TSEC */
 167 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 168 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 169 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 170 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 171
 172 /*
 173  * General PCI
 174  * Addresses are mapped 1-1.
 175  */
 176 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 177 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 178 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 179 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 180 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 181 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 182 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 183 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 184 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 185
 186 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 187 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 188 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 189 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 190 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 191 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 192 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 193 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 194 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 195
 196 #if defined(CONFIG_PCI)
 197
 198 #undef CONFIG_EEPRO100
 199 #undef CONFIG_TULIP
 200
 201 #if !defined(CONFIG_PCI_PNP)
 202         #define PCI_ENET0_IOADDR        0xFIXME
 203         #define PCI_ENET0_MEMADDR       0xFIXME
 204         #define PCI_IDSEL_NUMBER        0xFIXME
 205 #endif
 206
 207 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 208 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 209
 210 #endif  /* CONFIG_PCI */
 211
 212 /*
 213  * TSEC configuration
 214  */
 215
 216 #if defined(CONFIG_TSEC_ENET)
 217
 218 #define CONFIG_GMII                     /* MII PHY management */
 219 #define CONFIG_TSEC1
 220 #define CONFIG_TSEC1_NAME       "TSEC0"
 221 #define CONFIG_TSEC2
 222 #define CONFIG_TSEC2_NAME       "TSEC1"
 223 #define CONFIG_PHY_M88E1111
 224 #define TSEC1_PHY_ADDR          0x08
 225 #define TSEC2_PHY_ADDR          0x10
 226 #define TSEC1_PHYIDX            0
 227 #define TSEC2_PHYIDX            0
 228 #define TSEC1_FLAGS             TSEC_GIGABIT
 229 #define TSEC2_FLAGS             TSEC_GIGABIT
 230
 231 /* Options are: TSEC[0-1] */
 232 #define CONFIG_ETHPRIME         "TSEC0"
 233
 234 #endif  /* CONFIG_TSEC_ENET */
 235
 236 /*
 237  * Environment
 238  */
 239 #ifndef CONFIG_SYS_RAMBOOT
 240         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0xc0000)
 241         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 242         #define CONFIG_ENV_SIZE         0x2000
 243
 244 /* Address and size of Redundant Environment Sector     */
 245 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 246 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 247
 248 #else
 249         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 250         #define CONFIG_ENV_SIZE         0x2000
 251 #endif
 252
 253 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 254 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 255
 256 /*
 257  * BOOTP options
 258  */
 259 #define CONFIG_BOOTP_BOOTFILESIZE
 260
 261 /*
 262  * Command line configuration.
 263  */
 264 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 265 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 266 #define CONFIG_RTC_RX8025
 267
 268 /* Pass Ethernet MAC to VxWorks */
 269 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x000043f0
 270
 271 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 272
 273 /*
 274  * Miscellaneous configurable options
 275  */
 276 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 277
 278 /*
 279  * For booting Linux, the board info and command line data
 280  * have to be in the first 256 MB of memory, since this is
 281  * the maximum mapped by the Linux kernel during initialization.
 282  */
 283 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Init Memory map for Linux*/
 284
 285 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 286
 287 /* System IO Config */
 288 #define CONFIG_SYS_SICRH 0
 289 #define CONFIG_SYS_SICRL SICRL_LDP_A
 290
 291 #define CONFIG_SYS_HID0_INIT    0x000000000
 292 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 293                                  HID0_ENABLE_INSTRUCTION_CACHE)
 294
 295 #define CONFIG_SYS_HID2         HID2_HBE
 296
 297 #define CONFIG_SYS_GPIO1_PRELIM
 298 #define CONFIG_SYS_GPIO1_DIR    0x00100000
 299 #define CONFIG_SYS_GPIO1_DAT    0x00100000
 300
 301 #define CONFIG_SYS_GPIO2_PRELIM
 302 #define CONFIG_SYS_GPIO2_DIR    0x78900000
 303 #define CONFIG_SYS_GPIO2_DAT    0x70100000
 304
 305 #define CONFIG_HIGH_BATS                /* High BATs supported */
 306
 307 /* DDR @ 0x00000000 */
 308 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 309                                  BATL_MEMCOHERENCE)
 310 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 311                                  BATU_VS | BATU_VP)
 312
 313 /* PCI @ 0x80000000 */
 314 #ifdef CONFIG_PCI
 315 #define CONFIG_PCI_INDIRECT_BRIDGE
 316 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
 317                                  BATL_MEMCOHERENCE)
 318 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
 319                                  BATU_VS | BATU_VP)
 320 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
 321                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 322 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
 323                                  BATU_VS | BATU_VP)
 324 #else
 325 #define CONFIG_SYS_IBAT1L       (0)
 326 #define CONFIG_SYS_IBAT1U       (0)
 327 #define CONFIG_SYS_IBAT2L       (0)
 328 #define CONFIG_SYS_IBAT2U       (0)
 329 #endif
 330
 331 #ifdef CONFIG_MPC83XX_PCI2
 332 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
 333                                  BATL_MEMCOHERENCE)
 334 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
 335                                  BATU_VS | BATU_VP)
 336 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
 337                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 338 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
 339                                  BATU_VS | BATU_VP)
 340 #else
 341 #define CONFIG_SYS_IBAT3L       (0)
 342 #define CONFIG_SYS_IBAT3U       (0)
 343 #define CONFIG_SYS_IBAT4L       (0)
 344 #define CONFIG_SYS_IBAT4U       (0)
 345 #endif
 346
 347 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 348 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 349                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 350 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | \
 351                                  BATU_VS | BATU_VP)
 352
 353 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
 354 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 355
 356 #if (CONFIG_SYS_DDR_SIZE == 512)
 357 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
 358                                  BATL_PP_RW | BATL_MEMCOHERENCE)
 359 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
 360                                  BATU_BL_256M | BATU_VS | BATU_VP)
 361 #else
 362 #define CONFIG_SYS_IBAT7L       (0)
 363 #define CONFIG_SYS_IBAT7U       (0)
 364 #endif
 365
 366 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 367 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 368 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 369 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 370 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 371 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 372 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 373 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 374 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 375 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 376 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 377 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 378 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 379 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 380 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 381 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 382
 383 #if defined(CONFIG_CMD_KGDB)
 384 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 385 #endif
 386
 387 /*
 388  * Environment Configuration
 389  */
 390 #define CONFIG_ENV_OVERWRITE
 391
 392 #if defined(CONFIG_TSEC_ENET)
 393 #define CONFIG_HAS_ETH0
 394 #define CONFIG_HAS_ETH1
 395 #endif
 396
 397 #define CONFIG_HOSTNAME         "VME8349"
 398 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 399 #define CONFIG_BOOTFILE         "uImage"
 400
 401 #define CONFIG_LOADADDR         800000  /* def location for tftp and bootm */
 402
 403 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 404         "netdev=eth0\0"                                                 \
 405         "hostname=vme8349\0"                                            \
 406         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 407                 "nfsroot=${serverip}:${rootpath}\0"                     \
 408         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 409         "addip=setenv bootargs ${bootargs} "                            \
 410                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 411                 ":${hostname}:${netdev}:off panic=1\0"                  \
 412         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 413         "flash_nfs=run nfsargs addip addtty;"                           \
 414                 "bootm ${kernel_addr}\0"                                \
 415         "flash_self=run ramargs addip addtty;"                          \
 416                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 417         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 418                 "bootm\0"                                               \
 419         "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"              \
 420         "update=protect off fff00000 fff3ffff; "                        \
 421                 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
 422         "upd=run load update\0"                                         \
 423         "fdtaddr=780000\0"                                              \
 424         "fdtfile=vme8349.dtb\0"                                         \
 425         ""
 426
 427 #define CONFIG_NFSBOOTCOMMAND                                           \
 428         "setenv bootargs root=/dev/nfs rw "                             \
 429                 "nfsroot=$serverip:$rootpath "                          \
 430                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 431                                                         "$netdev:off "  \
 432                 "console=$consoledev,$baudrate $othbootargs;"           \
 433         "tftp $loadaddr $bootfile;"                                     \
 434         "tftp $fdtaddr $fdtfile;"                                       \
 435         "bootm $loadaddr - $fdtaddr"
 436
 437 #define CONFIG_RAMBOOTCOMMAND                                           \
 438         "setenv bootargs root=/dev/ram rw "                             \
 439                 "console=$consoledev,$baudrate $othbootargs;"           \
 440         "tftp $ramdiskaddr $ramdiskfile;"                               \
 441         "tftp $loadaddr $bootfile;"                                     \
 442         "tftp $fdtaddr $fdtfile;"                                       \
 443         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 444
 445 #define CONFIG_BOOTCOMMAND      "run flash_self"
 446
 447 #ifndef __ASSEMBLY__
 448 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
 449                      unsigned char *buffer, int len);
 450 #endif
 451
 452 #endif  /* __CONFIG_H */