arch/arm/mach-socfpga/misc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <cpu_func.h>
   9 #include <hang.h>
  10 #include <asm/cache.h>
  11 #include <init.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <errno.h>
  15 #include <fdtdec.h>
  16 #include <linux/libfdt.h>
  17 #include <altera.h>
  18 #include <miiphy.h>
  19 #include <netdev.h>
  20 #include <watchdog.h>
  21 #include <asm/arch/misc.h>
  22 #include <asm/arch/reset_manager.h>
  23 #include <asm/arch/scan_manager.h>
  24 #include <asm/arch/system_manager.h>
  25 #include <asm/arch/nic301.h>
  26 #include <asm/arch/scu.h>
  27 #include <asm/pl310.h>
  28 #include <linux/printk.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 phys_addr_t socfpga_clkmgr_base __section(".data");
  33 phys_addr_t socfpga_rstmgr_base __section(".data");
  34 phys_addr_t socfpga_sysmgr_base __section(".data");
  35
  36 #ifdef CONFIG_SYS_L2_PL310
  37 static const struct pl310_regs *const pl310 =
  38         (struct pl310_regs *)CFG_SYS_PL310_BASE;
  39 #endif
  40
  41 struct bsel bsel_str[] = {
  42         { "rsvd", "Reserved", },
  43         { "fpga", "FPGA (HPS2FPGA Bridge)", },
  44         { "nand", "NAND Flash (1.8V)", },
  45         { "nand", "NAND Flash (3.0V)", },
  46         { "sd", "SD/MMC External Transceiver (1.8V)", },
  47         { "sd", "SD/MMC Internal Transceiver (3.0V)", },
  48         { "qspi", "QSPI Flash (1.8V)", },
  49         { "qspi", "QSPI Flash (3.0V)", },
  50 };
  51
  52 int dram_init(void)
  53 {
  54         if (fdtdec_setup_mem_size_base() != 0)
  55                 return -EINVAL;
  56
  57         return 0;
  58 }
  59
  60 void enable_caches(void)
  61 {
  62 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  63         icache_enable();
  64 #endif
  65 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  66         dcache_enable();
  67 #endif
  68 }
  69
  70 #ifdef CONFIG_SYS_L2_PL310
  71 void v7_outer_cache_enable(void)
  72 {
  73         struct udevice *dev;
  74
  75         if (uclass_get_device(UCLASS_CACHE, 0, &dev))
  76                 pr_err("cache controller driver NOT found!\n");
  77 }
  78
  79 void v7_outer_cache_disable(void)
  80 {
  81         /* Disable the L2 cache */
  82         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  83 }
  84
  85 void socfpga_pl310_clear(void)
  86 {
  87         u32 mask = 0xff, ena = 0;
  88
  89         icache_enable();
  90
  91         /* Disable the L2 cache */
  92         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  93
  94         writel(0x0, &pl310->pl310_tag_latency_ctrl);
  95         writel(0x10, &pl310->pl310_data_latency_ctrl);
  96
  97         /* enable BRESP, instruction and data prefetch, full line of zeroes */
  98         setbits_le32(&pl310->pl310_aux_ctrl,
  99                      L310_AUX_CTRL_DATA_PREFETCH_MASK |
 100                      L310_AUX_CTRL_INST_PREFETCH_MASK |
 101                      L310_SHARED_ATT_OVERRIDE_ENABLE);
 102
 103         /* Enable the L2 cache */
 104         ena = readl(&pl310->pl310_ctrl);
 105         ena |= L2X0_CTRL_EN;
 106
 107         /*
 108          * Invalidate the PL310 L2 cache. Keep the invalidation code
 109          * entirely in L1 I-cache to avoid any bus traffic through
 110          * the L2.
 111          */
 112         asm volatile(
 113                 ".align 5                       \n"
 114                 "       b       3f              \n"
 115                 "1:     str     %1,     [%4]    \n"
 116                 "       dsb                     \n"
 117                 "       isb                     \n"
 118                 "       str     %0,     [%2]    \n"
 119                 "       dsb                     \n"
 120                 "       isb                     \n"
 121                 "2:     ldr     %0,     [%2]    \n"
 122                 "       cmp     %0,     #0      \n"
 123                 "       bne     2b              \n"
 124                 "       str     %0,     [%3]    \n"
 125                 "       dsb                     \n"
 126                 "       isb                     \n"
 127                 "       b       4f              \n"
 128                 "3:     b       1b              \n"
 129                 "4:     nop                     \n"
 130         : "+r"(mask), "+r"(ena)
 131         : "r"(&pl310->pl310_inv_way),
 132           "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
 133         : "memory", "cc");
 134
 135         /* Disable the L2 cache */
 136         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 137 }
 138 #endif
 139
 140 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 141 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 142 int overwrite_console(void)
 143 {
 144         return 0;
 145 }
 146 #endif
 147
 148 #ifdef CONFIG_FPGA
 149 /* add device descriptor to FPGA device table */
 150 void socfpga_fpga_add(void *fpga_desc)
 151 {
 152         fpga_init();
 153         fpga_add(fpga_altera, fpga_desc);
 154 }
 155 #endif
 156
 157 int arch_cpu_init(void)
 158 {
 159         socfpga_get_managers_addr();
 160
 161 #ifdef CONFIG_HW_WATCHDOG
 162         /*
 163          * In case the watchdog is enabled, make sure to (re-)configure it
 164          * so that the defined timeout is valid. Otherwise the SPL (Perloader)
 165          * timeout value is still active which might too short for Linux
 166          * booting.
 167          */
 168         hw_watchdog_init();
 169 #else
 170         /*
 171          * If the HW watchdog is NOT enabled, make sure it is not running,
 172          * for example because it was enabled in the preloader. This might
 173          * trigger a watchdog-triggered reboot of Linux kernel later.
 174          * Toggle watchdog reset, so watchdog in not running state.
 175          */
 176         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 177         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 178 #endif
 179
 180         return 0;
 181 }
 182
 183 #ifndef CONFIG_SPL_BUILD
 184 static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc,
 185                      char *const argv[])
 186 {
 187         unsigned int mask = ~0;
 188
 189         if (argc < 2 || argc > 3)
 190                 return CMD_RET_USAGE;
 191
 192         argv++;
 193
 194         if (argc == 3)
 195                 mask = hextoul(argv[1], NULL);
 196
 197         switch (*argv[0]) {
 198         case 'e':       /* Enable */
 199                 do_bridge_reset(1, mask);
 200                 break;
 201         case 'd':       /* Disable */
 202                 do_bridge_reset(0, mask);
 203                 break;
 204         default:
 205                 return CMD_RET_USAGE;
 206         }
 207
 208         return 0;
 209 }
 210
 211 U_BOOT_CMD(bridge, 3, 1, do_bridge,
 212            "SoCFPGA HPS FPGA bridge control",
 213            "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 214            "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 215            ""
 216 );
 217
 218 #endif
 219
 220 static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
 221 {
 222         const void *blob = gd->fdt_blob;
 223         struct fdt_resource r;
 224         int node;
 225         int ret;
 226
 227         node = fdt_node_offset_by_compatible(blob, -1, compat);
 228         if (node < 0)
 229                 return node;
 230
 231         if (!fdtdec_get_is_enabled(blob, node))
 232                 return -ENODEV;
 233
 234         ret = fdt_get_resource(blob, node, "reg", 0, &r);
 235         if (ret)
 236                 return ret;
 237
 238         *base = (phys_addr_t)r.start;
 239
 240         return 0;
 241 }
 242
 243 void socfpga_get_managers_addr(void)
 244 {
 245         int ret;
 246
 247         ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
 248         if (ret)
 249                 hang();
 250
 251         ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
 252         if (ret)
 253                 hang();
 254
 255 #ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 256         ret = socfpga_get_base_addr("intel,agilex-clkmgr",
 257                                     &socfpga_clkmgr_base);
 258 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
 259         ret = socfpga_get_base_addr("intel,n5x-clkmgr",
 260                                     &socfpga_clkmgr_base);
 261 #else
 262         ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
 263 #endif
 264         if (ret)
 265                 hang();
 266 }
 267
 268 phys_addr_t socfpga_get_rstmgr_addr(void)
 269 {
 270         return socfpga_rstmgr_base;
 271 }
 272
 273 phys_addr_t socfpga_get_sysmgr_addr(void)
 274 {
 275         return socfpga_sysmgr_base;
 276 }
 277
 278 phys_addr_t socfpga_get_clkmgr_addr(void)
 279 {
 280         return socfpga_clkmgr_base;
 281 }