1 // SPDX-License-Identifier: GPL-2.0+
5 * Generated code from MX8M_DDR_tool
6 * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
9 #include <linux/kernel.h>
11 #include <asm/arch/ddr.h>
12 #include <asm/arch/lpddr4_define.h>
14 static struct dram_cfg_param ddr_ddrc_cfg[] = {
15 /** Initialize DDRC registers **/
18 {0x3d400000, 0xa3080020},
21 {0x3d400024, 0x3e800},
22 {0x3d400064, 0x6100e0},
23 {0x3d4000d0, 0xc003061c},
24 {0x3d4000d4, 0x9e0000},
25 {0x3d4000dc, 0xd4002d},
26 {0x3d4000e0, 0x310008},
27 {0x3d4000e8, 0x66004a},
28 {0x3d4000ec, 0x16004a},
29 {0x3d400100, 0x1a201b22},
30 {0x3d400104, 0x60633},
31 {0x3d40010c, 0xc0c000},
32 {0x3d400110, 0xf04080f},
33 {0x3d400114, 0x2040c0c},
34 {0x3d400118, 0x1010007},
36 {0x3d400130, 0x20600},
37 {0x3d400134, 0xc100002},
39 {0x3d400144, 0xa00050},
40 {0x3d400180, 0xc3200018},
41 {0x3d400184, 0x28061a8},
43 {0x3d400190, 0x497820a},
44 {0x3d400194, 0x80303},
45 {0x3d4001a0, 0xe0400018},
46 {0x3d4001a4, 0xdf00e4},
47 {0x3d4001a8, 0x80000000},
53 {0x3d400108, 0x70e1617},
57 {0x3d400204, 0x80808},
58 {0x3d400214, 0x7070707},
59 {0x3d400218, 0x48080707},
62 {0x3d402050, 0x20d040},
63 {0x3d402064, 0x14002f},
64 {0x3d4020dc, 0x940009},
65 {0x3d4020e0, 0x310000},
66 {0x3d4020e8, 0x66004a},
67 {0x3d4020ec, 0x16004a},
68 {0x3d402100, 0xb070508},
69 {0x3d402104, 0x3040b},
70 {0x3d402108, 0x305090c},
71 {0x3d40210c, 0x505000},
72 {0x3d402110, 0x4040204},
73 {0x3d402114, 0x2030303},
74 {0x3d402118, 0x1010004},
76 {0x3d402130, 0x20300},
77 {0x3d402134, 0xa100002},
79 {0x3d402144, 0x220011},
80 {0x3d402180, 0xc0a70006},
81 {0x3d402190, 0x3858202},
82 {0x3d402194, 0x80303},
85 {0x3d400250, 0x29001505},
87 {0x3d40025c, 0x5900575b},
88 {0x3d400264, 0x90000096},
89 {0x3d40026c, 0x1000012c},
100 {0x3d400498, 0x62ffff},
102 {0x3d4004a0, 0xffff},
105 /* PHY Initialize Configuration */
106 static struct dram_cfg_param ddr_ddrphy_cfg[] = {
270 /* ddr phy trained csr */
271 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
993 /* P0 message block paremeter for training firmware */
994 static struct dram_cfg_param ddr_fsp0_cfg[] = {
1032 /* P1 message block paremeter for training firmware */
1033 static struct dram_cfg_param ddr_fsp1_cfg[] = {
1072 /* P0 2D message block paremeter for training firmware */
1073 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1112 /* DRAM PHY init engine image */
1113 static struct dram_cfg_param ddr_phy_pie[] = {
1696 static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
1700 .fw_type = FW_1D_IMAGE,
1701 .fsp_cfg = ddr_fsp0_cfg,
1702 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
1707 .fw_type = FW_1D_IMAGE,
1708 .fsp_cfg = ddr_fsp1_cfg,
1709 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
1714 .fw_type = FW_2D_IMAGE,
1715 .fsp_cfg = ddr_fsp0_2d_cfg,
1716 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
1720 /* ddr timing config params */
1721 struct dram_timing_info dram_timing_3gb = {
1722 .ddrc_cfg = ddr_ddrc_cfg,
1723 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
1726 .fsp_msg = ddr_dram_fsp_msg,
1727 .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
1728 .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
1729 .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
1730 .ddrphy_pie = ddr_phy_pie,
1731 .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
1732 .fsp_table = { 3200, 667, },