1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/kernel.h>
8 #include <asm/arch/ddr.h>
9 #include <asm/arch/lpddr4_define.h>
11 struct dram_cfg_param lpddr4_ddrc_cfg[] = {
12 /* Start to config, default 3200mbps */
13 { DDRC_DBG1(0), 0x00000001 },
14 { DDRC_PWRCTL(0), 0x00000001 },
15 { DDRC_MSTR(0), 0xa1080020 },
16 { DDRC_RFSHTMG(0), 0x005b00d2 },
17 { DDRC_INIT0(0), 0xC003061B },
18 { DDRC_INIT1(0), 0x009D0000 },
19 { DDRC_INIT3(0), 0x00D4002D },
20 { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
21 { DDRC_INIT6(0), 0x0066004a },
22 { DDRC_INIT7(0), 0x0006004a },
24 { DDRC_DRAMTMG0(0), 0x1A201B22 },
25 { DDRC_DRAMTMG1(0), 0x00060633 },
26 { DDRC_DRAMTMG3(0), 0x00C0C000 },
27 { DDRC_DRAMTMG4(0), 0x0F04080F },
28 { DDRC_DRAMTMG5(0), 0x02040C0C },
29 { DDRC_DRAMTMG6(0), 0x01010007 },
30 { DDRC_DRAMTMG7(0), 0x00000401 },
31 { DDRC_DRAMTMG12(0), 0x00020600 },
32 { DDRC_DRAMTMG13(0), 0x0C100002 },
33 { DDRC_DRAMTMG14(0), 0x000000E6 },
34 { DDRC_DRAMTMG17(0), 0x00A00050 },
36 { DDRC_ZQCTL0(0), 0x03200018 },
37 { DDRC_ZQCTL1(0), 0x028061A8 },
38 { DDRC_ZQCTL2(0), 0x00000000 },
40 { DDRC_DFITMG0(0), 0x0497820A },
41 { DDRC_DFITMG2(0), 0x0000170A },
42 { DDRC_DRAMTMG2(0), 0x070E171a },
43 { DDRC_DBICTL(0), 0x00000001 },
45 { DDRC_DFITMG1(0), 0x00080303 },
46 { DDRC_DFIUPD0(0), 0xE0400018 },
47 { DDRC_DFIUPD1(0), 0x00DF00E4 },
48 { DDRC_DFIUPD2(0), 0x80000000 },
49 { DDRC_DFIMISC(0), 0x00000011 },
51 { DDRC_DFIPHYMSTR(0), 0x00000000 },
52 { DDRC_RANKCTL(0), 0x00000c99 },
55 { DDRC_ADDRMAP0(0), 0x0000001f },
56 { DDRC_ADDRMAP1(0), 0x00080808 },
57 { DDRC_ADDRMAP2(0), 0x00000000 },
58 { DDRC_ADDRMAP3(0), 0x00000000 },
59 { DDRC_ADDRMAP4(0), 0x00001f1f },
60 { DDRC_ADDRMAP5(0), 0x07070707 },
61 { DDRC_ADDRMAP6(0), 0x07070707 },
62 { DDRC_ADDRMAP7(0), 0x00000f0f },
64 /* performance setting */
65 { DDRC_SCHED(0), 0x29001701 },
66 { DDRC_SCHED1(0), 0x0000002c },
67 { DDRC_PERFHPR1(0), 0x04000030 },
68 { DDRC_PERFLPR1(0), 0x900093e7 },
69 { DDRC_PERFWR1(0), 0x20005574 },
70 { DDRC_PCCFG(0), 0x00000111 },
71 { DDRC_PCFGW_0(0), 0x000072ff },
72 { DDRC_PCFGQOS0_0(0), 0x02100e07 },
73 { DDRC_PCFGQOS1_0(0), 0x00620096 },
74 { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
75 { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
78 /* Frequency 1: 400mbps */
79 { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
80 { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
81 { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
82 { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
83 { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
84 { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
85 { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
86 { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
87 { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
88 { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
89 { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
90 { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
91 { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
92 { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
93 { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
94 { DDRC_FREQ1_INIT3(0), 0x00840000 },
95 { DDRC_FREQ1_INIT4(0), 0x00310000 },
96 { DDRC_FREQ1_INIT6(0), 0x0066004a },
97 { DDRC_FREQ1_INIT7(0), 0x0006004a },
99 /* Frequency 2: 100mbps */
100 { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
101 { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
102 { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
103 { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
104 { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
105 { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
106 { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
107 { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
108 { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
109 { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
110 { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
111 { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
112 { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
113 { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
114 { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
115 { DDRC_FREQ2_INIT3(0), 0x00840000 },
116 { DDRC_FREQ2_INIT4(0), 0x00310008 },
117 { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
118 { DDRC_FREQ2_INIT6(0), 0x0066004a },
119 { DDRC_FREQ2_INIT7(0), 0x0006004a },
121 /* boot start point */
122 { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
125 /* PHY Initialize Configuration */
126 struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
311 { 0x2002d, LPDDR4_PHY_DMIPinPresent },
312 { 0x12002d, LPDDR4_PHY_DMIPinPresent },
313 { 0x22002d, LPDDR4_PHY_DMIPinPresent },
322 /* ddr phy trained csr */
323 struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
1045 /* P0 message block paremeter for training firmware */
1046 struct dram_cfg_param lpddr4_fsp0_cfg[] = {
1053 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
1054 { 0x54006, LPDDR4_PHY_VREF_VALUE },
1056 { 0x54008, 0x131f },
1066 { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
1073 { 0x54019, 0x2dd4 },
1074 { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
1075 { 0x5401b, 0x4d66 },
1076 { 0x5401c, 0x4d08 },
1078 { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
1079 { 0x5401f, 0x2dd4 },
1080 { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
1081 { 0x54021, 0x4d66 },
1082 { 0x54022, 0x4d08 },
1084 { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
1091 { 0x5402b, 0x1000 },
1092 { 0x5402c, LPDDR4_CS },
1098 { 0x54032, 0xd400 },
1099 { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
1100 { 0x54034, 0x6600 },
1103 { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
1104 { 0x54038, 0xd400 },
1105 { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
1106 { 0x5403a, 0x6600 },
1109 { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
1120 /* P1 message block paremeter for training firmware */
1121 struct dram_cfg_param lpddr4_fsp1_cfg[] = {
1128 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */
1129 { 0x54006, LPDDR4_PHY_VREF_VALUE },
1131 { 0x54008, 0x121f },
1141 { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
1149 { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
1150 { 0x5401b, 0x4d66 },
1151 { 0x5401c, 0x4d08 },
1153 { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
1155 { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
1156 { 0x54021, 0x4d66 },
1157 { 0x54022, 0x4d08 },
1159 { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
1166 { 0x5402b, 0x1000 },
1167 { 0x5402c, LPDDR4_CS },
1173 { 0x54032, 0x8400 },
1174 { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
1175 { 0x54034, 0x6600 },
1178 { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
1179 { 0x54038, 0x8400 },
1180 { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
1181 { 0x5403a, 0x6600 },
1184 { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
1195 /* P1 message block paremeter for training firmware */
1196 struct dram_cfg_param lpddr4_fsp2_cfg[] = {
1203 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
1204 { 0x54006, LPDDR4_PHY_VREF_VALUE },
1206 { 0x54008, 0x121f },
1216 { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
1224 { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
1225 { 0x5401b, 0x4d66 },
1226 { 0x5401c, 0x4d08 },
1228 { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
1230 { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
1231 { 0x54021, 0x4d66 },
1232 { 0x54022, 0x4d08 },
1234 { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
1241 { 0x5402b, 0x1000 },
1242 { 0x5402c, LPDDR4_CS },
1248 { 0x54032, 0x8400 },
1249 { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
1250 { 0x54034, 0x6600 },
1253 { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
1254 { 0x54038, 0x8400 },
1255 { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
1256 { 0x5403a, 0x6600 },
1259 { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
1270 /* P0 2D message block paremeter for training firmware */
1271 struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
1278 { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
1279 { 0x54006, LPDDR4_PHY_VREF_VALUE },
1289 { 0x54010, 0x1f7f },
1291 { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
1298 { 0x54019, 0x2dd4 },
1299 { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
1300 { 0x5401b, 0x4d66 },
1301 { 0x5401c, 0x4d08 },
1303 { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
1304 { 0x5401f, 0x2dd4 },
1305 { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
1306 { 0x54021, 0x4d66 },
1307 { 0x54022, 0x4d08 },
1309 { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
1316 { 0x5402b, 0x1000 },
1317 { 0x5402c, LPDDR4_CS },
1323 { 0x54032, 0xd400 },
1324 { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
1325 { 0x54034, 0x6600 },
1328 { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
1329 { 0x54038, 0xd400 },
1330 { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
1331 { 0x5403a, 0x6600 },
1334 { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
1345 /* DRAM PHY init engine image */
1346 struct dram_cfg_param lpddr4_phy_pie[] = {
1405 { 0x9005c, 0x40c0 },
1411 { 0x90062, 0x4040 },
1484 { 0x40001, 0x4008 },
1488 { 0x40002, 0x4040 },
1498 { 0x40044, 0x1740 },
1506 { 0x40046, 0x2001 },
1510 { 0x40047, 0x2800 },
1518 { 0x40049, 0x1400 },
1528 { 0x4000c, 0x4028 },
1540 { 0x4000f, 0x4040 },
1544 { 0x40010, 0x2604 },
1551 { 0x40071, 0x2002 },
1556 { 0x40013, 0x2604 },
1563 { 0x40074, 0x2002 },
1564 { 0x40015, 0x4040 },
1570 { 0x40056, 0x1200 },
1574 { 0x40057, 0x1300 },
1578 { 0x40058, 0x1200 },
1582 { 0x40059, 0x1300 },
1584 { 0x4001a, 0x4808 },
1622 { 0x900c9, 0x8568 },
1631 { 0x900d2, 0x8558 },
1636 { 0x900d7, 0x1ff8 },
1637 { 0x900d8, 0x85a8 },
1646 { 0x900e1, 0x8310 },
1649 { 0x900e4, 0xa310 },
1661 { 0x900f0, 0x8310 },
1664 { 0x900f3, 0xa310 },
1666 { 0x900f5, 0x1ff8 },
1667 { 0x900f6, 0x85a8 },
1679 { 0x90102, 0x8b10 },
1682 { 0x90105, 0xab10 },
1694 { 0x90111, 0x8b10 },
1697 { 0x90114, 0xab10 },
1712 { 0x90123, 0x8080 },
1727 { 0x90132, 0x8080 },
1733 { 0x90138, 0x8568 },
1742 { 0x90141, 0x8558 },
1754 { 0x9014d, 0x8558 },
1772 { 0x9015f, 0x8140 },
1775 { 0x90162, 0x8138 },
1805 { 0x90180, 0x8140 },
1850 { 0x9000f, 0x6110 },
1851 { 0x90010, 0x2152 },
1852 { 0x90011, 0xdfbd },
1854 { 0x90013, 0x6152 },
1880 { 0x10002, 0x6209 },
1894 { 0x11002, 0x6209 },
1908 { 0x12002, 0x6209 },
1922 { 0x13002, 0x6209 },
1937 struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
1941 .fw_type = FW_1D_IMAGE,
1942 .fsp_cfg = lpddr4_fsp0_cfg,
1943 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
1948 .fw_type = FW_2D_IMAGE,
1949 .fsp_cfg = lpddr4_fsp0_2d_cfg,
1950 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
1955 .fw_type = FW_1D_IMAGE,
1956 .fsp_cfg = lpddr4_fsp1_cfg,
1957 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
1962 .fw_type = FW_1D_IMAGE,
1963 .fsp_cfg = lpddr4_fsp2_cfg,
1964 .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
1968 /* lpddr4 timing config params on EVK board */
1969 struct dram_timing_info dram_timing = {
1970 .ddrc_cfg = lpddr4_ddrc_cfg,
1971 .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
1972 .ddrphy_cfg = lpddr4_ddrphy_cfg,
1973 .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
1974 .fsp_msg = lpddr4_dram_fsp_msg,
1975 .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
1976 .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
1977 .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
1978 .ddrphy_pie = lpddr4_phy_pie,
1979 .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),