include/configs/ls1021atwr.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019, 2021 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 #define DDR_SDRAM_CFG                   0x470c0008
  14 #define DDR_CS0_BNDS                    0x008000bf
  15 #define DDR_CS0_CONFIG                  0x80014302
  16 #define DDR_TIMING_CFG_0                0x50550004
  17 #define DDR_TIMING_CFG_1                0xbcb38c56
  18 #define DDR_TIMING_CFG_2                0x0040d120
  19 #define DDR_TIMING_CFG_3                0x010e1000
  20 #define DDR_TIMING_CFG_4                0x00000001
  21 #define DDR_TIMING_CFG_5                0x03401400
  22 #define DDR_SDRAM_CFG_2                 0x00401010
  23 #define DDR_SDRAM_MODE                  0x00061c60
  24 #define DDR_SDRAM_MODE_2                0x00180000
  25 #define DDR_SDRAM_INTERVAL              0x18600618
  26 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  27 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  28 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  29 #define DDR_DDR_CDR1                    0x80040000
  30 #define DDR_DDR_CDR2                    0x00000001
  31 #define DDR_SDRAM_CLK_CNTL              0x02000000
  32 #define DDR_DDR_ZQ_CNTL                 0x89080600
  33 #define DDR_CS0_CONFIG_2                0
  34 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  35 #define SDRAM_CFG2_D_INIT               0x00000010
  36 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  37 #define SDRAM_CFG2_FRC_SR               0x80000000
  38 #define SDRAM_CFG_BI                    0x00000001
  39
  40 #ifdef CONFIG_SD_BOOT
  41 #ifdef CONFIG_NXP_ESBC
  42 /*
  43  * HDR would be appended at end of image and copied to DDR along
  44  * with U-Boot image.
  45  */
  46 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  47 #endif /* ifdef CONFIG_NXP_ESBC */
  48
  49 #ifdef CONFIG_U_BOOT_HDR_SIZE
  50 /*
  51  * HDR would be appended at end of image and copied to DDR along
  52  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  53  * size increases then increase this size in case of secure boot as
  54  * it uses raw u-boot image instead of fit image.
  55  */
  56 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  57 #else
  58 #define CONFIG_SYS_MONITOR_LEN          0x100000
  59 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  60 #endif
  61
  62 #define PHYS_SDRAM                      0x80000000
  63 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  64
  65 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
  66 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
  67
  68 /*
  69  * IFC Definitions
  70  */
  71 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  72 #define CONFIG_SYS_FLASH_BASE           0x60000000
  73 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  74
  75 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  76 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  77                                 CSPR_PORT_SIZE_16 | \
  78                                 CSPR_MSEL_NOR | \
  79                                 CSPR_V)
  80 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  81
  82 /* NOR Flash Timing Params */
  83 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  84                                         CSOR_NOR_TRHZ_80)
  85 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  86                                         FTIM0_NOR_TEADC(0x5) | \
  87                                         FTIM0_NOR_TAVDS(0x0) | \
  88                                         FTIM0_NOR_TEAHC(0x5))
  89 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  90                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
  91                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  92 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  93                                         FTIM2_NOR_TCH(0x4) | \
  94                                         FTIM2_NOR_TWP(0x1c) | \
  95                                         FTIM2_NOR_TWPH(0x0e))
  96 #define CONFIG_SYS_NOR_FTIM3            0
  97
  98 #define CONFIG_SYS_FLASH_QUIET_TEST
  99 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 100
 101 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 102
 103 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 104 #endif
 105
 106 /* CPLD */
 107
 108 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 109 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 110
 111 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 112 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 113                                         CSPR_PORT_SIZE_8 | \
 114                                         CSPR_MSEL_GPCM | \
 115                                         CSPR_V)
 116 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 117 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 118                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 119                                         CSOR_NOR_TRHZ_80)
 120
 121 /* CPLD Timing parameters for IFC GPCM */
 122 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 123                                         FTIM0_GPCM_TEADC(0xf) | \
 124                                         FTIM0_GPCM_TEAHC(0xf))
 125 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 126                                         FTIM1_GPCM_TRAD(0x3f))
 127 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 128                                         FTIM2_GPCM_TCH(0xf) | \
 129                                         FTIM2_GPCM_TWP(0xff))
 130 #define CONFIG_SYS_FPGA_FTIM3           0x0
 131 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 132 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 133 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 134 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 135 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 136 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 137 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 138 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 139 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 140 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 141 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 142 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 143 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 144 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 145 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 146 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 147
 148 /*
 149  * Serial Port
 150  */
 151 #ifndef CONFIG_LPUART
 152 #define CONFIG_SYS_NS16550_SERIAL
 153 #ifndef CONFIG_DM_SERIAL
 154 #define CONFIG_SYS_NS16550_REG_SIZE     1
 155 #endif
 156 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 157 #endif
 158
 159 /*
 160  * I2C
 161  */
 162
 163 /* GPIO */
 164
 165 /* EEPROM */
 166 #define CONFIG_SYS_I2C_EEPROM_NXID
 167 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 168
 169 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 170 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 171
 172 #define CONFIG_HWCONFIG
 173 #define HWCONFIG_BUFFER_SIZE            256
 174
 175 #define CONFIG_FSL_DEVICE_DISABLE
 176
 177 #define BOOT_TARGET_DEVICES(func) \
 178         func(MMC, mmc, 0) \
 179         func(USB, usb, 0) \
 180         func(DHCP, dhcp, na)
 181 #include <config_distro_bootcmd.h>
 182
 183 #ifdef CONFIG_LPUART
 184 #define CONFIG_EXTRA_ENV_SETTINGS       \
 185         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "     \
 186                 "cma=64M@0x0-0xb0000000\0" \
 187         "initrd_high=0xffffffff\0"      \
 188         "kernel_addr=0x65000000\0"      \
 189         "scriptaddr=0x80000000\0"       \
 190         "scripthdraddr=0x80080000\0"    \
 191         "fdtheader_addr_r=0x80100000\0" \
 192         "kernelheader_addr_r=0x80200000\0"      \
 193         "kernel_addr_r=0x81000000\0"    \
 194         "fdt_addr_r=0x90000000\0"       \
 195         "ramdisk_addr_r=0xa0000000\0"   \
 196         "load_addr=0xa0000000\0"        \
 197         "kernel_size=0x2800000\0"       \
 198         "kernel_addr_sd=0x8000\0"       \
 199         "kernel_size_sd=0x14000\0"      \
 200         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 201         BOOTENV                         \
 202         "boot_scripts=ls1021atwr_boot.scr\0"    \
 203         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 204                 "scan_dev_for_boot_part="       \
 205                         "part list ${devtype} ${devnum} devplist; "     \
 206                         "env exists devplist || setenv devplist 1; "    \
 207                         "for distro_bootpart in ${devplist}; do "       \
 208                         "if fstype ${devtype} "                         \
 209                                 "${devnum}:${distro_bootpart} "         \
 210                                 "bootfstype; then "                     \
 211                                 "run scan_dev_for_boot; "               \
 212                         "fi; "                  \
 213                 "done\0"                        \
 214         "scan_dev_for_boot="                              \
 215                 "echo Scanning ${devtype} "               \
 216                                 "${devnum}:${distro_bootpart}...; "  \
 217                 "for prefix in ${boot_prefixes}; do "     \
 218                         "run scan_dev_for_scripts; "      \
 219                 "done;"                                   \
 220                 "\0"                                      \
 221         "boot_a_script="                                  \
 222                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 223                         "${scriptaddr} ${prefix}${script}; "    \
 224                 "env exists secureboot && load ${devtype} "     \
 225                         "${devnum}:${distro_bootpart} "         \
 226                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 227                         "env exists secureboot "        \
 228                         "&& esbc_validate ${scripthdraddr};"    \
 229                 "source ${scriptaddr}\0"          \
 230         "installer=load mmc 0:2 $load_addr "    \
 231                 "/flex_installer_arm32.itb; "           \
 232                 "bootm $load_addr#ls1021atwr\0" \
 233         "qspi_bootcmd=echo Trying load from qspi..;"    \
 234                 "sf probe && sf read $load_addr "       \
 235                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
 236         "nor_bootcmd=echo Trying load from nor..;"      \
 237                 "cp.b $kernel_addr $load_addr "         \
 238                 "$kernel_size && bootm $load_addr#$board\0"
 239 #else
 240 #define CONFIG_EXTRA_ENV_SETTINGS       \
 241         "bootargs=root=/dev/ram0 rw console=ttyS0,115200 "      \
 242                 "cma=64M@0x0-0xb0000000\0" \
 243         "initrd_high=0xffffffff\0"      \
 244         "kernel_addr=0x61000000\0"      \
 245         "kernelheader_addr=0x60800000\0"        \
 246         "scriptaddr=0x80000000\0"       \
 247         "scripthdraddr=0x80080000\0"    \
 248         "fdtheader_addr_r=0x80100000\0" \
 249         "kernelheader_addr_r=0x80200000\0"      \
 250         "kernel_addr_r=0x81000000\0"    \
 251         "kernelheader_size=0x40000\0"   \
 252         "fdt_addr_r=0x90000000\0"       \
 253         "ramdisk_addr_r=0xa0000000\0"   \
 254         "load_addr=0xa0000000\0"        \
 255         "kernel_size=0x2800000\0"       \
 256         "kernel_addr_sd=0x8000\0"       \
 257         "kernel_size_sd=0x14000\0"      \
 258         "kernelhdr_addr_sd=0x4000\0"            \
 259         "kernelhdr_size_sd=0x10\0"              \
 260         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 261         BOOTENV                         \
 262         "boot_scripts=ls1021atwr_boot.scr\0"    \
 263         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 264                 "scan_dev_for_boot_part="       \
 265                         "part list ${devtype} ${devnum} devplist; "     \
 266                         "env exists devplist || setenv devplist 1; "    \
 267                         "for distro_bootpart in ${devplist}; do "       \
 268                         "if fstype ${devtype} "                         \
 269                                 "${devnum}:${distro_bootpart} "         \
 270                                 "bootfstype; then "                     \
 271                                 "run scan_dev_for_boot; "               \
 272                         "fi; "                  \
 273                 "done\0"                        \
 274         "scan_dev_for_boot="                              \
 275                 "echo Scanning ${devtype} "               \
 276                                 "${devnum}:${distro_bootpart}...; "  \
 277                 "for prefix in ${boot_prefixes}; do "     \
 278                         "run scan_dev_for_scripts; "      \
 279                 "done;"                                   \
 280                 "\0"                                      \
 281         "boot_a_script="                                  \
 282                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 283                         "${scriptaddr} ${prefix}${script}; "    \
 284                 "env exists secureboot && load ${devtype} "     \
 285                         "${devnum}:${distro_bootpart} "         \
 286                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 287                         "&& esbc_validate ${scripthdraddr};"    \
 288                 "source ${scriptaddr}\0"          \
 289         "qspi_bootcmd=echo Trying load from qspi..;"    \
 290                 "sf probe && sf read $load_addr "       \
 291                 "$kernel_addr $kernel_size; env exists secureboot "     \
 292                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 293                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 294                 "bootm $load_addr#$board\0" \
 295         "nor_bootcmd=echo Trying load from nor..;"      \
 296                 "cp.b $kernel_addr $load_addr "         \
 297                 "$kernel_size; env exists secureboot "  \
 298                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 299                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 300                 "bootm $load_addr#$board\0"     \
 301         "sd_bootcmd=echo Trying load from SD ..;"       \
 302                 "mmcinfo && mmc read $load_addr "       \
 303                 "$kernel_addr_sd $kernel_size_sd && "   \
 304                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
 305                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 306                 " && esbc_validate ${kernelheader_addr_r};"     \
 307                 "bootm $load_addr#$board\0"
 308 #endif
 309
 310 /*
 311  * Miscellaneous configurable options
 312  */
 313 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 314
 315 #define CONFIG_LS102XA_STREAM_ID
 316
 317 /*
 318  * Environment
 319  */
 320
 321 #include <asm/fsl_secure_boot.h>
 322
 323 #endif