board/gdsys/405ep/io.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, [email protected]
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <asm/ppc4xx-gpio.h>
  13
  14 #include <dtt.h>
  15 #include <miiphy.h>
  16
  17 #include "405ep.h"
  18 #include <gdsys_fpga.h>
  19
  20 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  21 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  22 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  23
  24 #define PHYREG_CONTROL                          0
  25 #define PHYREG_PAGE_ADDRESS                     22
  26 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1    16
  27 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2    26
  28
  29 enum {
  30         UNITTYPE_CCD_SWITCH = 1,
  31 };
  32
  33 enum {
  34         HWVER_100 = 0,
  35         HWVER_110 = 1,
  36         HWVER_121 = 2,
  37         HWVER_122 = 3,
  38 };
  39
  40 int misc_init_r(void)
  41 {
  42         /* startup fans */
  43         dtt_init();
  44
  45         return 0;
  46 }
  47
  48 int configure_gbit_phy(unsigned char addr)
  49 {
  50         unsigned short value;
  51
  52         /* select page 2 */
  53         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  54                 PHYREG_PAGE_ADDRESS, 0x0002))
  55                 goto err_out;
  56         /* disable SGMII autonegotiation */
  57         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  58                 PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
  59                 goto err_out;
  60         /* select page 0 */
  61         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  62                 PHYREG_PAGE_ADDRESS, 0x0000))
  63                 goto err_out;
  64         /* switch from powerdown to normal operation */
  65         if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  66                 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
  67                 goto err_out;
  68         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  69                 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
  70                 goto err_out;
  71         /* reset phy so settings take effect */
  72         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  73                 PHYREG_CONTROL, 0x9140))
  74                 goto err_out;
  75
  76         return 0;
  77
  78 err_out:
  79         printf("Error writing to the PHY addr=%02x\n", addr);
  80         return -1;
  81 }
  82
  83 /*
  84  * Check Board Identity:
  85  */
  86 int checkboard(void)
  87 {
  88         char *s = getenv("serial#");
  89
  90         puts("Board: CATCenter Io");
  91
  92         if (s != NULL) {
  93                 puts(", serial# ");
  94                 puts(s);
  95         }
  96
  97         puts("\n");
  98
  99         return 0;
 100 }
 101
 102 static void print_fpga_info(void)
 103 {
 104         struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
 105         u16 versions = in_le16(&fpga->versions);
 106         u16 fpga_version = in_le16(&fpga->fpga_version);
 107         u16 fpga_features = in_le16(&fpga->fpga_features);
 108         unsigned unit_type;
 109         unsigned hardware_version;
 110         unsigned feature_channels;
 111         unsigned feature_expansion;
 112
 113         unit_type = (versions & 0xf000) >> 12;
 114         hardware_version = versions & 0x000f;
 115         feature_channels = fpga_features & 0x007f;
 116         feature_expansion = fpga_features & (1<<15);
 117
 118         puts("FPGA:  ");
 119
 120         switch (unit_type) {
 121         case UNITTYPE_CCD_SWITCH:
 122                 printf("CCD-Switch");
 123                 break;
 124
 125         default:
 126                 printf("UnitType %d(not supported)", unit_type);
 127                 break;
 128         }
 129
 130         switch (hardware_version) {
 131         case HWVER_100:
 132                 printf(" HW-Ver 1.00\n");
 133                 break;
 134
 135         case HWVER_110:
 136                 printf(" HW-Ver 1.10\n");
 137                 break;
 138
 139         case HWVER_121:
 140                 printf(" HW-Ver 1.21\n");
 141                 break;
 142
 143         case HWVER_122:
 144                 printf(" HW-Ver 1.22\n");
 145                 break;
 146
 147         default:
 148                 printf(" HW-Ver %d(not supported)\n",
 149                        hardware_version);
 150                 break;
 151         }
 152
 153         printf("       FPGA V %d.%02d, features:",
 154                 fpga_version / 100, fpga_version % 100);
 155
 156         printf(" %d channel(s)", feature_channels);
 157
 158         printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
 159 }
 160
 161 /*
 162  * setup Gbit PHYs
 163  */
 164 int last_stage_init(void)
 165 {
 166         struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
 167         unsigned int k;
 168
 169         print_fpga_info();
 170
 171         miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
 172                 bb_miiphy_read, bb_miiphy_write);
 173
 174         for (k = 0; k < 32; ++k)
 175                 configure_gbit_phy(k);
 176
 177         /* take fpga serdes blocks out of reset */
 178         out_le16(&fpga->quad_serdes_reset, 0);
 179
 180         return 0;
 181 }
 182
 183 void gd405ep_init(void)
 184 {
 185 }
 186
 187 void gd405ep_set_fpga_reset(unsigned state)
 188 {
 189         if (state) {
 190                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
 191                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
 192         } else {
 193                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 194                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 195         }
 196 }
 197
 198 void gd405ep_setup_hw(void)
 199 {
 200         /*
 201          * set "startup-finished"-gpios
 202          */
 203         gpio_write_bit(21, 0);
 204         gpio_write_bit(22, 1);
 205 }
 206
 207 int gd405ep_get_fpga_done(unsigned fpga)
 208 {
 209         return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
 210 }