board/keymile/kmp204x/ddr.c

   1 /*
   2  * (C) Copyright 2013 Keymile AG
   3  * Valentin Longchamp <[email protected]>
   4  *
   5  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8   */
   9
  10 #include <common.h>
  11 #include <i2c.h>
  12 #include <hwconfig.h>
  13 #include <asm/mmu.h>
  14 #include <fsl_ddr_sdram.h>
  15 #include <fsl_ddr_dimm_params.h>
  16
  17 void fsl_ddr_board_options(memctl_options_t *popts,
  18                                 dimm_params_t *pdimm,
  19                                 unsigned int ctrl_num)
  20 {
  21         if (ctrl_num) {
  22                 printf("Wrong parameter for controller number %d", ctrl_num);
  23                 return;
  24         }
  25
  26         /* automatic calibration for nb of cycles between read and DQS pre */
  27         popts->cpo_override = 0xFF;
  28
  29         /* 1/2 clk delay between wr command and data strobe */
  30         popts->write_data_delay = 4;
  31         /* clk lauched 1/2 applied cylcle after address command */
  32         popts->clk_adjust = 4;
  33         /* 1T timing: command/address held for only 1 cycle */
  34         popts->twot_en = 0;
  35
  36         /* we have only one module, half str should be OK */
  37         popts->half_strength_driver_enable = 1;
  38
  39         /* wrlvl values overriden as recommended by ddr init func */
  40         popts->wrlvl_override = 1;
  41         popts->wrlvl_sample = 0xf;
  42         popts->wrlvl_start = 0x6;
  43
  44         /* Enable ZQ calibration */
  45         popts->zq_en = 1;
  46
  47         /* DHC_EN =1, ODT = 75 Ohm */
  48         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
  49 }
  50
  51 phys_size_t initdram(int board_type)
  52 {
  53         phys_size_t dram_size = 0;
  54
  55         puts("Initializing with SPD\n");
  56
  57         dram_size = fsl_ddr_sdram();
  58
  59         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  60         dram_size *= 0x100000;
  61
  62         debug("    DDR: ");
  63         return dram_size;
  64 }