1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016, NVIDIA CORPORATION.
5 * Portions based on U-Boot's rtl8169.c.
9 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
10 * Service) IP block. The IP supports multiple options for bus type, clocking/
11 * reset structure, and feature list.
13 * The driver is written such that generic core logic is kept separate from
14 * configuration-specific logic. Code that interacts with configuration-
15 * specific resources is split out into separate functions to avoid polluting
16 * common code. If/when this driver is enhanced to support multiple
17 * configurations, the core code should be adapted to call all configuration-
18 * specific functions through function pointers, with the definition of those
19 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
22 * The following configurations are currently supported:
24 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
25 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
26 * supports a single RGMII PHY. This configuration also has SW control over
27 * all clock and reset signals to the HW block.
46 #define EQOS_MAC_REGS_BASE 0x000
47 struct eqos_mac_regs {
48 uint32_t configuration; /* 0x000 */
49 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
50 uint32_t q0_tx_flow_ctrl; /* 0x070 */
51 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
52 uint32_t rx_flow_ctrl; /* 0x090 */
53 uint32_t unused_094; /* 0x094 */
54 uint32_t txq_prty_map0; /* 0x098 */
55 uint32_t unused_09c; /* 0x09c */
56 uint32_t rxq_ctrl0; /* 0x0a0 */
57 uint32_t unused_0a4; /* 0x0a4 */
58 uint32_t rxq_ctrl2; /* 0x0a8 */
59 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
60 uint32_t us_tic_counter; /* 0x0dc */
61 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
62 uint32_t hw_feature0; /* 0x11c */
63 uint32_t hw_feature1; /* 0x120 */
64 uint32_t hw_feature2; /* 0x124 */
65 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
66 uint32_t mdio_address; /* 0x200 */
67 uint32_t mdio_data; /* 0x204 */
68 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
69 uint32_t address0_high; /* 0x300 */
70 uint32_t address0_low; /* 0x304 */
73 #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
74 #define EQOS_MAC_CONFIGURATION_CST BIT(21)
75 #define EQOS_MAC_CONFIGURATION_ACS BIT(20)
76 #define EQOS_MAC_CONFIGURATION_WD BIT(19)
77 #define EQOS_MAC_CONFIGURATION_JD BIT(17)
78 #define EQOS_MAC_CONFIGURATION_JE BIT(16)
79 #define EQOS_MAC_CONFIGURATION_PS BIT(15)
80 #define EQOS_MAC_CONFIGURATION_FES BIT(14)
81 #define EQOS_MAC_CONFIGURATION_DM BIT(13)
82 #define EQOS_MAC_CONFIGURATION_TE BIT(1)
83 #define EQOS_MAC_CONFIGURATION_RE BIT(0)
85 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
86 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
87 #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
89 #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
91 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
92 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
94 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
95 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
96 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
97 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
98 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
100 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
101 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
103 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
104 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
105 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
106 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
108 #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
109 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
110 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
111 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
112 #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
113 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
114 #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
115 #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
116 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
117 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
118 #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
120 #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
122 #define EQOS_MTL_REGS_BASE 0xd00
123 struct eqos_mtl_regs {
124 uint32_t txq0_operation_mode; /* 0xd00 */
125 uint32_t unused_d04; /* 0xd04 */
126 uint32_t txq0_debug; /* 0xd08 */
127 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
128 uint32_t txq0_quantum_weight; /* 0xd18 */
129 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
130 uint32_t rxq0_operation_mode; /* 0xd30 */
131 uint32_t unused_d34; /* 0xd34 */
132 uint32_t rxq0_debug; /* 0xd38 */
135 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
136 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
137 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
138 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
139 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
140 #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
141 #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
143 #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
144 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
145 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
147 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
148 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
149 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
150 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
151 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
152 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
153 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
154 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
156 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
157 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
158 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
159 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
161 #define EQOS_DMA_REGS_BASE 0x1000
162 struct eqos_dma_regs {
163 uint32_t mode; /* 0x1000 */
164 uint32_t sysbus_mode; /* 0x1004 */
165 uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
166 uint32_t ch0_control; /* 0x1100 */
167 uint32_t ch0_tx_control; /* 0x1104 */
168 uint32_t ch0_rx_control; /* 0x1108 */
169 uint32_t unused_110c; /* 0x110c */
170 uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
171 uint32_t ch0_txdesc_list_address; /* 0x1114 */
172 uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
173 uint32_t ch0_rxdesc_list_address; /* 0x111c */
174 uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
175 uint32_t unused_1124; /* 0x1124 */
176 uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
177 uint32_t ch0_txdesc_ring_length; /* 0x112c */
178 uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
181 #define EQOS_DMA_MODE_SWR BIT(0)
183 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
184 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
185 #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
186 #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
187 #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
188 #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
190 #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
192 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
193 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
194 #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
195 #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
197 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
198 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
199 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
200 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
201 #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
203 /* These registers are Tegra186-specific */
204 #define EQOS_TEGRA186_REGS_BASE 0x8800
205 struct eqos_tegra186_regs {
206 uint32_t sdmemcomppadctrl; /* 0x8800 */
207 uint32_t auto_cal_config; /* 0x8804 */
208 uint32_t unused_8808; /* 0x8808 */
209 uint32_t auto_cal_status; /* 0x880c */
212 #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
214 #define EQOS_AUTO_CAL_CONFIG_START BIT(31)
215 #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
217 #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
221 #define EQOS_DESCRIPTOR_WORDS 4
222 #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
223 /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
224 #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
225 #define EQOS_DESCRIPTORS_TX 4
226 #define EQOS_DESCRIPTORS_RX 4
227 #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
228 #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
229 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
230 #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
231 #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
232 #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
235 * Warn if the cache-line size is larger than the descriptor size. In such
236 * cases the driver will likely fail because the CPU needs to flush the cache
237 * when requeuing RX buffers, therefore descriptors written by the hardware
238 * may be discarded. Architectures with full IO coherence, such as x86, do not
239 * experience this issue, and hence are excluded from this condition.
241 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
242 * the driver to allocate descriptors from a pool of non-cached memory.
244 #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
245 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
246 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
247 #warning Cache line size is larger than descriptor size
258 #define EQOS_DESC3_OWN BIT(31)
259 #define EQOS_DESC3_FD BIT(29)
260 #define EQOS_DESC3_LD BIT(28)
261 #define EQOS_DESC3_BUF1V BIT(24)
264 bool reg_access_always_ok;
269 phy_interface_t (*interface)(struct udevice *dev);
270 struct eqos_ops *ops;
274 void (*eqos_inval_desc)(void *desc);
275 void (*eqos_flush_desc)(void *desc);
276 void (*eqos_inval_buffer)(void *buf, size_t size);
277 void (*eqos_flush_buffer)(void *buf, size_t size);
278 int (*eqos_probe_resources)(struct udevice *dev);
279 int (*eqos_remove_resources)(struct udevice *dev);
280 int (*eqos_stop_resets)(struct udevice *dev);
281 int (*eqos_start_resets)(struct udevice *dev);
282 void (*eqos_stop_clks)(struct udevice *dev);
283 int (*eqos_start_clks)(struct udevice *dev);
284 int (*eqos_calibrate_pads)(struct udevice *dev);
285 int (*eqos_disable_calibration)(struct udevice *dev);
286 int (*eqos_set_tx_clk_speed)(struct udevice *dev);
287 ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
292 const struct eqos_config *config;
294 struct eqos_mac_regs *mac_regs;
295 struct eqos_mtl_regs *mtl_regs;
296 struct eqos_dma_regs *dma_regs;
297 struct eqos_tegra186_regs *tegra186_regs;
298 struct reset_ctl reset_ctl;
299 struct gpio_desc phy_reset_gpio;
300 struct clk clk_master_bus;
302 struct clk clk_ptp_ref;
305 struct clk clk_slave_bus;
307 struct phy_device *phy;
309 struct eqos_desc *tx_descs;
310 struct eqos_desc *rx_descs;
311 int tx_desc_idx, rx_desc_idx;
320 * TX and RX descriptors are 16 bytes. This causes problems with the cache
321 * maintenance on CPUs where the cache-line size exceeds the size of these
322 * descriptors. What will happen is that when the driver receives a packet
323 * it will be immediately requeued for the hardware to reuse. The CPU will
324 * therefore need to flush the cache-line containing the descriptor, which
325 * will cause all other descriptors in the same cache-line to be flushed
326 * along with it. If one of those descriptors had been written to by the
327 * device those changes (and the associated packet) will be lost.
329 * To work around this, we make use of non-cached memory if available. If
330 * descriptors are mapped uncached there's no need to manually flush them
331 * or invalidate them.
333 * Note that this only applies to descriptors. The packet data buffers do
334 * not have the same constraints since they are 1536 bytes large, so they
335 * are unlikely to share cache-lines.
337 static void *eqos_alloc_descs(unsigned int num)
339 #ifdef CONFIG_SYS_NONCACHED_MEMORY
340 return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE,
341 EQOS_DESCRIPTOR_ALIGN);
343 return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE);
347 static void eqos_free_descs(void *descs)
349 #ifdef CONFIG_SYS_NONCACHED_MEMORY
350 /* FIXME: noncached_alloc() has no opposite */
356 static void eqos_inval_desc_tegra186(void *desc)
358 #ifndef CONFIG_SYS_NONCACHED_MEMORY
359 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
360 unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE,
363 invalidate_dcache_range(start, end);
367 static void eqos_inval_desc_stm32(void *desc)
369 #ifndef CONFIG_SYS_NONCACHED_MEMORY
370 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
371 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
374 invalidate_dcache_range(start, end);
378 static void eqos_flush_desc_tegra186(void *desc)
380 #ifndef CONFIG_SYS_NONCACHED_MEMORY
381 flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE);
385 static void eqos_flush_desc_stm32(void *desc)
387 #ifndef CONFIG_SYS_NONCACHED_MEMORY
388 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
389 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
392 flush_dcache_range(start, end);
396 static void eqos_inval_buffer_tegra186(void *buf, size_t size)
398 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
399 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
401 invalidate_dcache_range(start, end);
404 static void eqos_inval_buffer_stm32(void *buf, size_t size)
406 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
407 unsigned long end = roundup((unsigned long)buf + size,
410 invalidate_dcache_range(start, end);
413 static void eqos_flush_buffer_tegra186(void *buf, size_t size)
415 flush_cache((unsigned long)buf, size);
418 static void eqos_flush_buffer_stm32(void *buf, size_t size)
420 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
421 unsigned long end = roundup((unsigned long)buf + size,
424 flush_dcache_range(start, end);
427 static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
429 return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
430 EQOS_MAC_MDIO_ADDRESS_GB, false,
434 static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
437 struct eqos_priv *eqos = bus->priv;
441 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
444 ret = eqos_mdio_wait_idle(eqos);
446 pr_err("MDIO not idle at entry");
450 val = readl(&eqos->mac_regs->mdio_address);
451 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
452 EQOS_MAC_MDIO_ADDRESS_C45E;
453 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
454 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
455 (eqos->config->config_mac_mdio <<
456 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
457 (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
458 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
459 EQOS_MAC_MDIO_ADDRESS_GB;
460 writel(val, &eqos->mac_regs->mdio_address);
462 udelay(eqos->config->mdio_wait);
464 ret = eqos_mdio_wait_idle(eqos);
466 pr_err("MDIO read didn't complete");
470 val = readl(&eqos->mac_regs->mdio_data);
471 val &= EQOS_MAC_MDIO_DATA_GD_MASK;
473 debug("%s: val=%x\n", __func__, val);
478 static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
479 int mdio_reg, u16 mdio_val)
481 struct eqos_priv *eqos = bus->priv;
485 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
486 mdio_addr, mdio_reg, mdio_val);
488 ret = eqos_mdio_wait_idle(eqos);
490 pr_err("MDIO not idle at entry");
494 writel(mdio_val, &eqos->mac_regs->mdio_data);
496 val = readl(&eqos->mac_regs->mdio_address);
497 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
498 EQOS_MAC_MDIO_ADDRESS_C45E;
499 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
500 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
501 (eqos->config->config_mac_mdio <<
502 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
503 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
504 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
505 EQOS_MAC_MDIO_ADDRESS_GB;
506 writel(val, &eqos->mac_regs->mdio_address);
508 udelay(eqos->config->mdio_wait);
510 ret = eqos_mdio_wait_idle(eqos);
512 pr_err("MDIO read didn't complete");
519 static int eqos_start_clks_tegra186(struct udevice *dev)
521 struct eqos_priv *eqos = dev_get_priv(dev);
524 debug("%s(dev=%p):\n", __func__, dev);
526 ret = clk_enable(&eqos->clk_slave_bus);
528 pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
532 ret = clk_enable(&eqos->clk_master_bus);
534 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
535 goto err_disable_clk_slave_bus;
538 ret = clk_enable(&eqos->clk_rx);
540 pr_err("clk_enable(clk_rx) failed: %d", ret);
541 goto err_disable_clk_master_bus;
544 ret = clk_enable(&eqos->clk_ptp_ref);
546 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
547 goto err_disable_clk_rx;
550 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
552 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
553 goto err_disable_clk_ptp_ref;
556 ret = clk_enable(&eqos->clk_tx);
558 pr_err("clk_enable(clk_tx) failed: %d", ret);
559 goto err_disable_clk_ptp_ref;
562 debug("%s: OK\n", __func__);
565 err_disable_clk_ptp_ref:
566 clk_disable(&eqos->clk_ptp_ref);
568 clk_disable(&eqos->clk_rx);
569 err_disable_clk_master_bus:
570 clk_disable(&eqos->clk_master_bus);
571 err_disable_clk_slave_bus:
572 clk_disable(&eqos->clk_slave_bus);
574 debug("%s: FAILED: %d\n", __func__, ret);
578 static int eqos_start_clks_stm32(struct udevice *dev)
580 struct eqos_priv *eqos = dev_get_priv(dev);
583 debug("%s(dev=%p):\n", __func__, dev);
585 ret = clk_enable(&eqos->clk_master_bus);
587 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
591 ret = clk_enable(&eqos->clk_rx);
593 pr_err("clk_enable(clk_rx) failed: %d", ret);
594 goto err_disable_clk_master_bus;
597 ret = clk_enable(&eqos->clk_tx);
599 pr_err("clk_enable(clk_tx) failed: %d", ret);
600 goto err_disable_clk_rx;
603 if (clk_valid(&eqos->clk_ck)) {
604 ret = clk_enable(&eqos->clk_ck);
606 pr_err("clk_enable(clk_ck) failed: %d", ret);
607 goto err_disable_clk_tx;
611 debug("%s: OK\n", __func__);
615 clk_disable(&eqos->clk_tx);
617 clk_disable(&eqos->clk_rx);
618 err_disable_clk_master_bus:
619 clk_disable(&eqos->clk_master_bus);
621 debug("%s: FAILED: %d\n", __func__, ret);
625 static void eqos_stop_clks_tegra186(struct udevice *dev)
627 struct eqos_priv *eqos = dev_get_priv(dev);
629 debug("%s(dev=%p):\n", __func__, dev);
631 clk_disable(&eqos->clk_tx);
632 clk_disable(&eqos->clk_ptp_ref);
633 clk_disable(&eqos->clk_rx);
634 clk_disable(&eqos->clk_master_bus);
635 clk_disable(&eqos->clk_slave_bus);
637 debug("%s: OK\n", __func__);
640 static void eqos_stop_clks_stm32(struct udevice *dev)
642 struct eqos_priv *eqos = dev_get_priv(dev);
644 debug("%s(dev=%p):\n", __func__, dev);
646 clk_disable(&eqos->clk_tx);
647 clk_disable(&eqos->clk_rx);
648 clk_disable(&eqos->clk_master_bus);
649 if (clk_valid(&eqos->clk_ck))
650 clk_disable(&eqos->clk_ck);
652 debug("%s: OK\n", __func__);
655 static int eqos_start_resets_tegra186(struct udevice *dev)
657 struct eqos_priv *eqos = dev_get_priv(dev);
660 debug("%s(dev=%p):\n", __func__, dev);
662 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
664 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
670 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
672 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
676 ret = reset_assert(&eqos->reset_ctl);
678 pr_err("reset_assert() failed: %d", ret);
684 ret = reset_deassert(&eqos->reset_ctl);
686 pr_err("reset_deassert() failed: %d", ret);
690 debug("%s: OK\n", __func__);
694 static int eqos_start_resets_stm32(struct udevice *dev)
699 static int eqos_stop_resets_tegra186(struct udevice *dev)
701 struct eqos_priv *eqos = dev_get_priv(dev);
703 reset_assert(&eqos->reset_ctl);
704 dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
709 static int eqos_stop_resets_stm32(struct udevice *dev)
714 static int eqos_calibrate_pads_tegra186(struct udevice *dev)
716 struct eqos_priv *eqos = dev_get_priv(dev);
719 debug("%s(dev=%p):\n", __func__, dev);
721 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
722 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
726 setbits_le32(&eqos->tegra186_regs->auto_cal_config,
727 EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
729 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
730 EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
732 pr_err("calibrate didn't start");
736 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
737 EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
739 pr_err("calibrate didn't finish");
746 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
747 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
749 debug("%s: returns %d\n", __func__, ret);
754 static int eqos_disable_calibration_tegra186(struct udevice *dev)
756 struct eqos_priv *eqos = dev_get_priv(dev);
758 debug("%s(dev=%p):\n", __func__, dev);
760 clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
761 EQOS_AUTO_CAL_CONFIG_ENABLE);
766 static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
768 struct eqos_priv *eqos = dev_get_priv(dev);
770 return clk_get_rate(&eqos->clk_slave_bus);
773 static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
775 struct eqos_priv *eqos = dev_get_priv(dev);
777 return clk_get_rate(&eqos->clk_master_bus);
780 static int eqos_calibrate_pads_stm32(struct udevice *dev)
785 static int eqos_disable_calibration_stm32(struct udevice *dev)
790 static int eqos_set_full_duplex(struct udevice *dev)
792 struct eqos_priv *eqos = dev_get_priv(dev);
794 debug("%s(dev=%p):\n", __func__, dev);
796 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
801 static int eqos_set_half_duplex(struct udevice *dev)
803 struct eqos_priv *eqos = dev_get_priv(dev);
805 debug("%s(dev=%p):\n", __func__, dev);
807 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
809 /* WAR: Flush TX queue when switching to half-duplex */
810 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
811 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
816 static int eqos_set_gmii_speed(struct udevice *dev)
818 struct eqos_priv *eqos = dev_get_priv(dev);
820 debug("%s(dev=%p):\n", __func__, dev);
822 clrbits_le32(&eqos->mac_regs->configuration,
823 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
828 static int eqos_set_mii_speed_100(struct udevice *dev)
830 struct eqos_priv *eqos = dev_get_priv(dev);
832 debug("%s(dev=%p):\n", __func__, dev);
834 setbits_le32(&eqos->mac_regs->configuration,
835 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
840 static int eqos_set_mii_speed_10(struct udevice *dev)
842 struct eqos_priv *eqos = dev_get_priv(dev);
844 debug("%s(dev=%p):\n", __func__, dev);
846 clrsetbits_le32(&eqos->mac_regs->configuration,
847 EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
852 static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
854 struct eqos_priv *eqos = dev_get_priv(dev);
858 debug("%s(dev=%p):\n", __func__, dev);
860 switch (eqos->phy->speed) {
862 rate = 125 * 1000 * 1000;
865 rate = 25 * 1000 * 1000;
868 rate = 2.5 * 1000 * 1000;
871 pr_err("invalid speed %d", eqos->phy->speed);
875 ret = clk_set_rate(&eqos->clk_tx, rate);
877 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
884 static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
889 static int eqos_adjust_link(struct udevice *dev)
891 struct eqos_priv *eqos = dev_get_priv(dev);
895 debug("%s(dev=%p):\n", __func__, dev);
897 if (eqos->phy->duplex)
898 ret = eqos_set_full_duplex(dev);
900 ret = eqos_set_half_duplex(dev);
902 pr_err("eqos_set_*_duplex() failed: %d", ret);
906 switch (eqos->phy->speed) {
908 en_calibration = true;
909 ret = eqos_set_gmii_speed(dev);
912 en_calibration = true;
913 ret = eqos_set_mii_speed_100(dev);
916 en_calibration = false;
917 ret = eqos_set_mii_speed_10(dev);
920 pr_err("invalid speed %d", eqos->phy->speed);
924 pr_err("eqos_set_*mii_speed*() failed: %d", ret);
928 if (en_calibration) {
929 ret = eqos->config->ops->eqos_calibrate_pads(dev);
931 pr_err("eqos_calibrate_pads() failed: %d",
936 ret = eqos->config->ops->eqos_disable_calibration(dev);
938 pr_err("eqos_disable_calibration() failed: %d",
943 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
945 pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
952 static int eqos_write_hwaddr(struct udevice *dev)
954 struct eth_pdata *plat = dev_get_platdata(dev);
955 struct eqos_priv *eqos = dev_get_priv(dev);
959 * This function may be called before start() or after stop(). At that
960 * time, on at least some configurations of the EQoS HW, all clocks to
961 * the EQoS HW block will be stopped, and a reset signal applied. If
962 * any register access is attempted in this state, bus timeouts or CPU
963 * hangs may occur. This check prevents that.
965 * A simple solution to this problem would be to not implement
966 * write_hwaddr(), since start() always writes the MAC address into HW
967 * anyway. However, it is desirable to implement write_hwaddr() to
968 * support the case of SW that runs subsequent to U-Boot which expects
969 * the MAC address to already be programmed into the EQoS registers,
970 * which must happen irrespective of whether the U-Boot user (or
971 * scripts) actually made use of the EQoS device, and hence
972 * irrespective of whether start() was ever called.
974 * Note that this requirement by subsequent SW is not valid for
975 * Tegra186, and is likely not valid for any non-PCI instantiation of
976 * the EQoS HW block. This function is implemented solely as
977 * future-proofing with the expectation the driver will eventually be
978 * ported to some system where the expectation above is true.
980 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
983 /* Update the MAC address */
984 val = (plat->enetaddr[5] << 8) |
986 writel(val, &eqos->mac_regs->address0_high);
987 val = (plat->enetaddr[3] << 24) |
988 (plat->enetaddr[2] << 16) |
989 (plat->enetaddr[1] << 8) |
991 writel(val, &eqos->mac_regs->address0_low);
996 static int eqos_start(struct udevice *dev)
998 struct eqos_priv *eqos = dev_get_priv(dev);
1001 u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
1004 debug("%s(dev=%p):\n", __func__, dev);
1006 eqos->tx_desc_idx = 0;
1007 eqos->rx_desc_idx = 0;
1009 ret = eqos->config->ops->eqos_start_clks(dev);
1011 pr_err("eqos_start_clks() failed: %d", ret);
1015 ret = eqos->config->ops->eqos_start_resets(dev);
1017 pr_err("eqos_start_resets() failed: %d", ret);
1023 eqos->reg_access_ok = true;
1025 ret = wait_for_bit_le32(&eqos->dma_regs->mode,
1026 EQOS_DMA_MODE_SWR, false,
1027 eqos->config->swr_wait, false);
1029 pr_err("EQOS_DMA_MODE_SWR stuck");
1030 goto err_stop_resets;
1033 ret = eqos->config->ops->eqos_calibrate_pads(dev);
1035 pr_err("eqos_calibrate_pads() failed: %d", ret);
1036 goto err_stop_resets;
1038 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
1040 val = (rate / 1000000) - 1;
1041 writel(val, &eqos->mac_regs->us_tic_counter);
1044 * if PHY was already connected and configured,
1045 * don't need to reconnect/reconfigure again
1048 eqos->phy = phy_connect(eqos->mii, 0, dev,
1049 eqos->config->interface(dev));
1051 pr_err("phy_connect() failed");
1052 goto err_stop_resets;
1054 ret = phy_config(eqos->phy);
1056 pr_err("phy_config() failed: %d", ret);
1057 goto err_shutdown_phy;
1061 ret = phy_startup(eqos->phy);
1063 pr_err("phy_startup() failed: %d", ret);
1064 goto err_shutdown_phy;
1067 if (!eqos->phy->link) {
1069 goto err_shutdown_phy;
1072 ret = eqos_adjust_link(dev);
1074 pr_err("eqos_adjust_link() failed: %d", ret);
1075 goto err_shutdown_phy;
1080 /* Enable Store and Forward mode for TX */
1081 /* Program Tx operating mode */
1082 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1083 EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
1084 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
1085 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
1087 /* Transmit Queue weight */
1088 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
1090 /* Enable Store and Forward mode for RX, since no jumbo frame */
1091 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1092 EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
1094 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
1095 val = readl(&eqos->mac_regs->hw_feature1);
1096 tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
1097 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
1098 rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
1099 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
1102 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
1103 * r/tqs is encoded as (n / 256) - 1.
1105 tqs = (128 << tx_fifo_sz) / 256 - 1;
1106 rqs = (128 << rx_fifo_sz) / 256 - 1;
1108 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1109 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
1110 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
1111 tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
1112 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1113 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
1114 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
1115 rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
1117 /* Flow control used only if each channel gets 4KB or more FIFO */
1118 if (rqs >= ((4096 / 256) - 1)) {
1121 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1122 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
1125 * Set Threshold for Activating Flow Contol space for min 2
1126 * frames ie, (1500 * 1) = 1500 bytes.
1128 * Set Threshold for Deactivating Flow Contol for space of
1129 * min 1 frame (frame size 1500bytes) in receive fifo
1131 if (rqs == ((4096 / 256) - 1)) {
1133 * This violates the above formula because of FIFO size
1134 * limit therefore overflow may occur inspite of this.
1136 rfd = 0x3; /* Full-3K */
1137 rfa = 0x1; /* Full-1.5K */
1138 } else if (rqs == ((8192 / 256) - 1)) {
1139 rfd = 0x6; /* Full-4K */
1140 rfa = 0xa; /* Full-6K */
1141 } else if (rqs == ((16384 / 256) - 1)) {
1142 rfd = 0x6; /* Full-4K */
1143 rfa = 0x12; /* Full-10K */
1145 rfd = 0x6; /* Full-4K */
1146 rfa = 0x1E; /* Full-16K */
1149 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1150 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
1151 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1152 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
1153 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
1155 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1157 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
1162 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
1163 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
1164 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
1165 eqos->config->config_mac <<
1166 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1168 /* Set TX flow control parameters */
1169 /* Set Pause Time */
1170 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1171 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
1172 /* Assign priority for TX flow control */
1173 clrbits_le32(&eqos->mac_regs->txq_prty_map0,
1174 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
1175 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
1176 /* Assign priority for RX flow control */
1177 clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
1178 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
1179 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
1180 /* Enable flow control */
1181 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1182 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
1183 setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
1184 EQOS_MAC_RX_FLOW_CTRL_RFE);
1186 clrsetbits_le32(&eqos->mac_regs->configuration,
1187 EQOS_MAC_CONFIGURATION_GPSLCE |
1188 EQOS_MAC_CONFIGURATION_WD |
1189 EQOS_MAC_CONFIGURATION_JD |
1190 EQOS_MAC_CONFIGURATION_JE,
1191 EQOS_MAC_CONFIGURATION_CST |
1192 EQOS_MAC_CONFIGURATION_ACS);
1194 eqos_write_hwaddr(dev);
1198 /* Enable OSP mode */
1199 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1200 EQOS_DMA_CH0_TX_CONTROL_OSP);
1202 /* RX buffer size. Must be a multiple of bus width */
1203 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1204 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
1205 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
1206 EQOS_MAX_PACKET_SIZE <<
1207 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
1209 setbits_le32(&eqos->dma_regs->ch0_control,
1210 EQOS_DMA_CH0_CONTROL_PBLX8);
1213 * Burst length must be < 1/2 FIFO size.
1214 * FIFO size in tqs is encoded as (n / 256) - 1.
1215 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
1216 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
1221 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
1222 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
1223 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
1224 pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
1226 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1227 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
1228 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
1229 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
1231 /* DMA performance configuration */
1232 val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
1233 EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
1234 EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
1235 writel(val, &eqos->dma_regs->sysbus_mode);
1237 /* Set up descriptors */
1239 memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE);
1240 for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
1241 struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
1242 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
1243 (i * EQOS_MAX_PACKET_SIZE));
1244 rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1246 eqos->config->ops->eqos_flush_desc(eqos->descs);
1248 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
1249 writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
1250 writel(EQOS_DESCRIPTORS_TX - 1,
1251 &eqos->dma_regs->ch0_txdesc_ring_length);
1253 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
1254 writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);
1255 writel(EQOS_DESCRIPTORS_RX - 1,
1256 &eqos->dma_regs->ch0_rxdesc_ring_length);
1258 /* Enable everything */
1260 setbits_le32(&eqos->mac_regs->configuration,
1261 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1263 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1264 EQOS_DMA_CH0_TX_CONTROL_ST);
1265 setbits_le32(&eqos->dma_regs->ch0_rx_control,
1266 EQOS_DMA_CH0_RX_CONTROL_SR);
1268 /* TX tail pointer not written until we need to TX a packet */
1270 * Point RX tail pointer at last descriptor. Ideally, we'd point at the
1271 * first descriptor, implying all descriptors were available. However,
1272 * that's not distinguishable from none of the descriptors being
1275 last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]);
1276 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1278 eqos->started = true;
1280 debug("%s: OK\n", __func__);
1284 phy_shutdown(eqos->phy);
1286 eqos->config->ops->eqos_stop_resets(dev);
1288 eqos->config->ops->eqos_stop_clks(dev);
1290 pr_err("FAILED: %d", ret);
1294 static void eqos_stop(struct udevice *dev)
1296 struct eqos_priv *eqos = dev_get_priv(dev);
1299 debug("%s(dev=%p):\n", __func__, dev);
1303 eqos->started = false;
1304 eqos->reg_access_ok = false;
1306 /* Disable TX DMA */
1307 clrbits_le32(&eqos->dma_regs->ch0_tx_control,
1308 EQOS_DMA_CH0_TX_CONTROL_ST);
1310 /* Wait for TX all packets to drain out of MTL */
1311 for (i = 0; i < 1000000; i++) {
1312 u32 val = readl(&eqos->mtl_regs->txq0_debug);
1313 u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
1314 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
1315 u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
1316 if ((trcsts != 1) && (!txqsts))
1320 /* Turn off MAC TX and RX */
1321 clrbits_le32(&eqos->mac_regs->configuration,
1322 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1324 /* Wait for all RX packets to drain out of MTL */
1325 for (i = 0; i < 1000000; i++) {
1326 u32 val = readl(&eqos->mtl_regs->rxq0_debug);
1327 u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
1328 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
1329 u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
1330 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
1331 if ((!prxq) && (!rxqsts))
1335 /* Turn off RX DMA */
1336 clrbits_le32(&eqos->dma_regs->ch0_rx_control,
1337 EQOS_DMA_CH0_RX_CONTROL_SR);
1340 phy_shutdown(eqos->phy);
1342 eqos->config->ops->eqos_stop_resets(dev);
1343 eqos->config->ops->eqos_stop_clks(dev);
1345 debug("%s: OK\n", __func__);
1348 static int eqos_send(struct udevice *dev, void *packet, int length)
1350 struct eqos_priv *eqos = dev_get_priv(dev);
1351 struct eqos_desc *tx_desc;
1354 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
1357 memcpy(eqos->tx_dma_buf, packet, length);
1358 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length);
1360 tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]);
1361 eqos->tx_desc_idx++;
1362 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
1364 tx_desc->des0 = (ulong)eqos->tx_dma_buf;
1366 tx_desc->des2 = length;
1368 * Make sure that if HW sees the _OWN write below, it will see all the
1369 * writes to the rest of the descriptor too.
1372 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
1373 eqos->config->ops->eqos_flush_desc(tx_desc);
1375 writel((ulong)(tx_desc + 1), &eqos->dma_regs->ch0_txdesc_tail_pointer);
1377 for (i = 0; i < 1000000; i++) {
1378 eqos->config->ops->eqos_inval_desc(tx_desc);
1379 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
1384 debug("%s: TX timeout\n", __func__);
1389 static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
1391 struct eqos_priv *eqos = dev_get_priv(dev);
1392 struct eqos_desc *rx_desc;
1395 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
1397 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1398 if (rx_desc->des3 & EQOS_DESC3_OWN) {
1399 debug("%s: RX packet not available\n", __func__);
1403 *packetp = eqos->rx_dma_buf +
1404 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1405 length = rx_desc->des3 & 0x7fff;
1406 debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
1408 eqos->config->ops->eqos_inval_buffer(*packetp, length);
1413 static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
1415 struct eqos_priv *eqos = dev_get_priv(dev);
1416 uchar *packet_expected;
1417 struct eqos_desc *rx_desc;
1419 debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
1421 packet_expected = eqos->rx_dma_buf +
1422 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1423 if (packet != packet_expected) {
1424 debug("%s: Unexpected packet (expected %p)\n", __func__,
1429 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
1430 rx_desc->des0 = (u32)(ulong)packet;
1434 * Make sure that if HW sees the _OWN write below, it will see all the
1435 * writes to the rest of the descriptor too.
1438 rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
1439 eqos->config->ops->eqos_flush_desc(rx_desc);
1441 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1443 eqos->rx_desc_idx++;
1444 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
1449 static int eqos_probe_resources_core(struct udevice *dev)
1451 struct eqos_priv *eqos = dev_get_priv(dev);
1454 debug("%s(dev=%p):\n", __func__, dev);
1456 eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX +
1457 EQOS_DESCRIPTORS_RX);
1459 debug("%s: eqos_alloc_descs() failed\n", __func__);
1463 eqos->tx_descs = (struct eqos_desc *)eqos->descs;
1464 eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX);
1465 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs,
1468 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
1469 if (!eqos->tx_dma_buf) {
1470 debug("%s: memalign(tx_dma_buf) failed\n", __func__);
1472 goto err_free_descs;
1474 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
1476 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
1477 if (!eqos->rx_dma_buf) {
1478 debug("%s: memalign(rx_dma_buf) failed\n", __func__);
1480 goto err_free_tx_dma_buf;
1482 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
1484 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
1485 if (!eqos->rx_pkt) {
1486 debug("%s: malloc(rx_pkt) failed\n", __func__);
1488 goto err_free_rx_dma_buf;
1490 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
1492 debug("%s: OK\n", __func__);
1495 err_free_rx_dma_buf:
1496 free(eqos->rx_dma_buf);
1497 err_free_tx_dma_buf:
1498 free(eqos->tx_dma_buf);
1500 eqos_free_descs(eqos->descs);
1503 debug("%s: returns %d\n", __func__, ret);
1507 static int eqos_remove_resources_core(struct udevice *dev)
1509 struct eqos_priv *eqos = dev_get_priv(dev);
1511 debug("%s(dev=%p):\n", __func__, dev);
1514 free(eqos->rx_dma_buf);
1515 free(eqos->tx_dma_buf);
1516 eqos_free_descs(eqos->descs);
1518 debug("%s: OK\n", __func__);
1522 static int eqos_probe_resources_tegra186(struct udevice *dev)
1524 struct eqos_priv *eqos = dev_get_priv(dev);
1527 debug("%s(dev=%p):\n", __func__, dev);
1529 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
1531 pr_err("reset_get_by_name(rst) failed: %d", ret);
1535 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1536 &eqos->phy_reset_gpio,
1537 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
1539 pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
1540 goto err_free_reset_eqos;
1543 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
1545 pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
1546 goto err_free_gpio_phy_reset;
1549 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
1551 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1552 goto err_free_clk_slave_bus;
1555 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
1557 pr_err("clk_get_by_name(rx) failed: %d", ret);
1558 goto err_free_clk_master_bus;
1561 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
1563 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
1564 goto err_free_clk_rx;
1568 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
1570 pr_err("clk_get_by_name(tx) failed: %d", ret);
1571 goto err_free_clk_ptp_ref;
1574 debug("%s: OK\n", __func__);
1577 err_free_clk_ptp_ref:
1578 clk_free(&eqos->clk_ptp_ref);
1580 clk_free(&eqos->clk_rx);
1581 err_free_clk_master_bus:
1582 clk_free(&eqos->clk_master_bus);
1583 err_free_clk_slave_bus:
1584 clk_free(&eqos->clk_slave_bus);
1585 err_free_gpio_phy_reset:
1586 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1587 err_free_reset_eqos:
1588 reset_free(&eqos->reset_ctl);
1590 debug("%s: returns %d\n", __func__, ret);
1594 /* board-specific Ethernet Interface initializations. */
1595 __weak int board_interface_eth_init(struct udevice *dev,
1596 phy_interface_t interface_type)
1601 static int eqos_probe_resources_stm32(struct udevice *dev)
1603 struct eqos_priv *eqos = dev_get_priv(dev);
1605 phy_interface_t interface;
1607 debug("%s(dev=%p):\n", __func__, dev);
1609 interface = eqos->config->interface(dev);
1611 if (interface == PHY_INTERFACE_MODE_NONE) {
1612 pr_err("Invalid PHY interface\n");
1616 ret = board_interface_eth_init(dev, interface);
1620 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
1622 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1626 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
1628 pr_err("clk_get_by_name(rx) failed: %d", ret);
1629 goto err_free_clk_master_bus;
1632 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
1634 pr_err("clk_get_by_name(tx) failed: %d", ret);
1635 goto err_free_clk_rx;
1638 /* Get ETH_CLK clocks (optional) */
1639 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
1641 pr_warn("No phy clock provided %d", ret);
1643 debug("%s: OK\n", __func__);
1647 clk_free(&eqos->clk_rx);
1648 err_free_clk_master_bus:
1649 clk_free(&eqos->clk_master_bus);
1652 debug("%s: returns %d\n", __func__, ret);
1656 static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
1658 const char *phy_mode;
1659 phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
1661 debug("%s(dev=%p):\n", __func__, dev);
1663 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1666 interface = phy_get_interface_by_name(phy_mode);
1671 static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
1673 return PHY_INTERFACE_MODE_MII;
1676 static int eqos_remove_resources_tegra186(struct udevice *dev)
1678 struct eqos_priv *eqos = dev_get_priv(dev);
1680 debug("%s(dev=%p):\n", __func__, dev);
1682 clk_free(&eqos->clk_tx);
1683 clk_free(&eqos->clk_ptp_ref);
1684 clk_free(&eqos->clk_rx);
1685 clk_free(&eqos->clk_slave_bus);
1686 clk_free(&eqos->clk_master_bus);
1687 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1688 reset_free(&eqos->reset_ctl);
1690 debug("%s: OK\n", __func__);
1694 static int eqos_remove_resources_stm32(struct udevice *dev)
1696 struct eqos_priv *eqos = dev_get_priv(dev);
1698 debug("%s(dev=%p):\n", __func__, dev);
1700 clk_free(&eqos->clk_tx);
1701 clk_free(&eqos->clk_rx);
1702 clk_free(&eqos->clk_master_bus);
1703 if (clk_valid(&eqos->clk_ck))
1704 clk_free(&eqos->clk_ck);
1706 debug("%s: OK\n", __func__);
1710 static int eqos_probe(struct udevice *dev)
1712 struct eqos_priv *eqos = dev_get_priv(dev);
1715 debug("%s(dev=%p):\n", __func__, dev);
1718 eqos->config = (void *)dev_get_driver_data(dev);
1720 eqos->regs = devfdt_get_addr(dev);
1721 if (eqos->regs == FDT_ADDR_T_NONE) {
1722 pr_err("devfdt_get_addr() failed");
1725 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
1726 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
1727 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
1728 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
1730 ret = eqos_probe_resources_core(dev);
1732 pr_err("eqos_probe_resources_core() failed: %d", ret);
1736 ret = eqos->config->ops->eqos_probe_resources(dev);
1738 pr_err("eqos_probe_resources() failed: %d", ret);
1739 goto err_remove_resources_core;
1742 eqos->mii = mdio_alloc();
1744 pr_err("mdio_alloc() failed");
1746 goto err_remove_resources_tegra;
1748 eqos->mii->read = eqos_mdio_read;
1749 eqos->mii->write = eqos_mdio_write;
1750 eqos->mii->priv = eqos;
1751 strcpy(eqos->mii->name, dev->name);
1753 ret = mdio_register(eqos->mii);
1755 pr_err("mdio_register() failed: %d", ret);
1759 debug("%s: OK\n", __func__);
1763 mdio_free(eqos->mii);
1764 err_remove_resources_tegra:
1765 eqos->config->ops->eqos_remove_resources(dev);
1766 err_remove_resources_core:
1767 eqos_remove_resources_core(dev);
1769 debug("%s: returns %d\n", __func__, ret);
1773 static int eqos_remove(struct udevice *dev)
1775 struct eqos_priv *eqos = dev_get_priv(dev);
1777 debug("%s(dev=%p):\n", __func__, dev);
1779 mdio_unregister(eqos->mii);
1780 mdio_free(eqos->mii);
1781 eqos->config->ops->eqos_remove_resources(dev);
1783 eqos_probe_resources_core(dev);
1785 debug("%s: OK\n", __func__);
1789 static const struct eth_ops eqos_ops = {
1790 .start = eqos_start,
1794 .free_pkt = eqos_free_pkt,
1795 .write_hwaddr = eqos_write_hwaddr,
1798 static struct eqos_ops eqos_tegra186_ops = {
1799 .eqos_inval_desc = eqos_inval_desc_tegra186,
1800 .eqos_flush_desc = eqos_flush_desc_tegra186,
1801 .eqos_inval_buffer = eqos_inval_buffer_tegra186,
1802 .eqos_flush_buffer = eqos_flush_buffer_tegra186,
1803 .eqos_probe_resources = eqos_probe_resources_tegra186,
1804 .eqos_remove_resources = eqos_remove_resources_tegra186,
1805 .eqos_stop_resets = eqos_stop_resets_tegra186,
1806 .eqos_start_resets = eqos_start_resets_tegra186,
1807 .eqos_stop_clks = eqos_stop_clks_tegra186,
1808 .eqos_start_clks = eqos_start_clks_tegra186,
1809 .eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
1810 .eqos_disable_calibration = eqos_disable_calibration_tegra186,
1811 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
1812 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
1815 static const struct eqos_config eqos_tegra186_config = {
1816 .reg_access_always_ok = false,
1819 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
1820 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
1821 .interface = eqos_get_interface_tegra186,
1822 .ops = &eqos_tegra186_ops
1825 static struct eqos_ops eqos_stm32_ops = {
1826 .eqos_inval_desc = eqos_inval_desc_stm32,
1827 .eqos_flush_desc = eqos_flush_desc_stm32,
1828 .eqos_inval_buffer = eqos_inval_buffer_stm32,
1829 .eqos_flush_buffer = eqos_flush_buffer_stm32,
1830 .eqos_probe_resources = eqos_probe_resources_stm32,
1831 .eqos_remove_resources = eqos_remove_resources_stm32,
1832 .eqos_stop_resets = eqos_stop_resets_stm32,
1833 .eqos_start_resets = eqos_start_resets_stm32,
1834 .eqos_stop_clks = eqos_stop_clks_stm32,
1835 .eqos_start_clks = eqos_start_clks_stm32,
1836 .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
1837 .eqos_disable_calibration = eqos_disable_calibration_stm32,
1838 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
1839 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
1842 static const struct eqos_config eqos_stm32_config = {
1843 .reg_access_always_ok = false,
1846 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
1847 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
1848 .interface = eqos_get_interface_stm32,
1849 .ops = &eqos_stm32_ops
1852 static const struct udevice_id eqos_ids[] = {
1854 .compatible = "nvidia,tegra186-eqos",
1855 .data = (ulong)&eqos_tegra186_config
1858 .compatible = "snps,dwmac-4.20a",
1859 .data = (ulong)&eqos_stm32_config
1865 U_BOOT_DRIVER(eth_eqos) = {
1868 .of_match = eqos_ids,
1869 .probe = eqos_probe,
1870 .remove = eqos_remove,
1872 .priv_auto_alloc_size = sizeof(struct eqos_priv),
1873 .platdata_auto_alloc_size = sizeof(struct eth_pdata),