drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <[email protected]>,
   8  *          Sebastian Andrzej Siewior <[email protected]>
   9  *
  10  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
  11  * to uboot.
  12  *
  13  * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
  14  */
  15
  16 #include <common.h>
  17 #include <clk.h>
  18 #include <cpu_func.h>
  19 #include <malloc.h>
  20 #include <dwc3-uboot.h>
  21 #include <dm/device_compat.h>
  22 #include <dm/devres.h>
  23 #include <linux/bug.h>
  24 #include <linux/delay.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/err.h>
  27 #include <linux/ioport.h>
  28 #include <dm.h>
  29 #include <generic-phy.h>
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32 #include <linux/bitfield.h>
  33 #include <linux/math64.h>
  34 #include <linux/time.h>
  35
  36 #include "core.h"
  37 #include "gadget.h"
  38 #include "io.h"
  39
  40 #include "linux-compat.h"
  41
  42 static LIST_HEAD(dwc3_list);
  43 /* -------------------------------------------------------------------------- */
  44
  45 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  46 {
  47         u32 reg;
  48
  49         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  50         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  51         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  52         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  53 }
  54
  55 /**
  56  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  57  * @dwc: pointer to our context structure
  58  */
  59 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  60 {
  61         u32             reg;
  62
  63         /* Before Resetting PHY, put Core in Reset */
  64         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  65         reg |= DWC3_GCTL_CORESOFTRESET;
  66         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  67
  68         /* Assert USB3 PHY reset */
  69         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  70         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  71         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  72
  73         /* Assert USB2 PHY reset */
  74         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  75         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  76         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  77
  78         mdelay(100);
  79
  80         /* Clear USB3 PHY reset */
  81         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  82         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  83         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  84
  85         /* Clear USB2 PHY reset */
  86         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  87         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  88         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  89
  90         mdelay(100);
  91
  92         /* After PHYs are stable we can take Core out of reset state */
  93         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  94         reg &= ~DWC3_GCTL_CORESOFTRESET;
  95         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  96
  97         return 0;
  98 }
  99
 100 /*
 101  * dwc3_frame_length_adjustment - Adjusts frame length if required
 102  * @dwc3: Pointer to our controller context structure
 103  * @fladj: Value of GFLADJ_30MHZ to adjust frame length
 104  */
 105 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
 106 {
 107         u32 reg;
 108
 109         if (dwc->revision < DWC3_REVISION_250A)
 110                 return;
 111
 112         if (fladj == 0)
 113                 return;
 114
 115         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 116         reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 117         reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
 118         dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 119 }
 120
 121 /**
 122  * dwc3_ref_clk_period - Reference clock period configuration
 123  *              Default reference clock period depends on hardware
 124  *              configuration. For systems with reference clock that differs
 125  *              from the default, this will set clock period in DWC3_GUCTL
 126  *              register.
 127  * @dwc: Pointer to our controller context structure
 128  * @ref_clk_per: reference clock period in ns
 129  */
 130 static void dwc3_ref_clk_period(struct dwc3 *dwc)
 131 {
 132         unsigned long period;
 133         unsigned long fladj;
 134         unsigned long decr;
 135         unsigned long rate;
 136         u32 reg;
 137
 138         if (dwc->ref_clk) {
 139                 rate = clk_get_rate(dwc->ref_clk);
 140                 if (!rate)
 141                         return;
 142                 period = NSEC_PER_SEC / rate;
 143         } else {
 144                 return;
 145         }
 146
 147         reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
 148         reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
 149         reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
 150         dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
 151
 152         if (dwc->revision <= DWC3_REVISION_250A)
 153                 return;
 154
 155         /*
 156          * The calculation below is
 157          *
 158          * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
 159          *
 160          * but rearranged for fixed-point arithmetic. The division must be
 161          * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
 162          * neither does rate * period).
 163          *
 164          * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
 165          * nanoseconds of error caused by the truncation which happened during
 166          * the division when calculating rate or period (whichever one was
 167          * derived from the other). We first calculate the relative error, then
 168          * scale it to units of 8 ppm.
 169          */
 170         fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
 171         fladj -= 125000;
 172
 173         /*
 174          * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
 175          */
 176         decr = 480000000 / rate;
 177
 178         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 179         reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
 180             &  ~DWC3_GFLADJ_240MHZDECR
 181             &  ~DWC3_GFLADJ_240MHZDECR_PLS1;
 182         reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
 183             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
 184             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
 185         dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 186 }
 187
 188 /**
 189  * dwc3_free_one_event_buffer - Frees one event buffer
 190  * @dwc: Pointer to our controller context structure
 191  * @evt: Pointer to event buffer to be freed
 192  */
 193 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 194                 struct dwc3_event_buffer *evt)
 195 {
 196         dma_free_coherent(evt->buf);
 197 }
 198
 199 /**
 200  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 201  * @dwc: Pointer to our controller context structure
 202  * @length: size of the event buffer
 203  *
 204  * Returns a pointer to the allocated event buffer structure on success
 205  * otherwise ERR_PTR(errno).
 206  */
 207 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 208                 unsigned length)
 209 {
 210         struct dwc3_event_buffer        *evt;
 211
 212         evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
 213                            GFP_KERNEL);
 214         if (!evt)
 215                 return ERR_PTR(-ENOMEM);
 216
 217         evt->dwc        = dwc;
 218         evt->length     = length;
 219         evt->buf        = dma_alloc_coherent(length,
 220                                              (unsigned long *)&evt->dma);
 221         if (!evt->buf)
 222                 return ERR_PTR(-ENOMEM);
 223
 224         dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
 225
 226         return evt;
 227 }
 228
 229 /**
 230  * dwc3_free_event_buffers - frees all allocated event buffers
 231  * @dwc: Pointer to our controller context structure
 232  */
 233 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 234 {
 235         struct dwc3_event_buffer        *evt;
 236         int i;
 237
 238         for (i = 0; i < dwc->num_event_buffers; i++) {
 239                 evt = dwc->ev_buffs[i];
 240                 if (evt)
 241                         dwc3_free_one_event_buffer(dwc, evt);
 242         }
 243 }
 244
 245 /**
 246  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 247  * @dwc: pointer to our controller context structure
 248  * @length: size of event buffer
 249  *
 250  * Returns 0 on success otherwise negative errno. In the error case, dwc
 251  * may contain some buffers allocated but not all which were requested.
 252  */
 253 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 254 {
 255         int                     num;
 256         int                     i;
 257
 258         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 259         dwc->num_event_buffers = num;
 260
 261         dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
 262                                  sizeof(*dwc->ev_buffs) * num);
 263         if (!dwc->ev_buffs)
 264                 return -ENOMEM;
 265
 266         for (i = 0; i < num; i++) {
 267                 struct dwc3_event_buffer        *evt;
 268
 269                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 270                 if (IS_ERR(evt)) {
 271                         dev_err(dwc->dev, "can't allocate event buffer\n");
 272                         return PTR_ERR(evt);
 273                 }
 274                 dwc->ev_buffs[i] = evt;
 275         }
 276
 277         return 0;
 278 }
 279
 280 /**
 281  * dwc3_event_buffers_setup - setup our allocated event buffers
 282  * @dwc: pointer to our controller context structure
 283  *
 284  * Returns 0 on success otherwise negative errno.
 285  */
 286 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 287 {
 288         struct dwc3_event_buffer        *evt;
 289         int                             n;
 290
 291         for (n = 0; n < dwc->num_event_buffers; n++) {
 292                 evt = dwc->ev_buffs[n];
 293                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 294                                 evt->buf, (unsigned long long) evt->dma,
 295                                 evt->length);
 296
 297                 evt->lpos = 0;
 298
 299                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 300                                 lower_32_bits(evt->dma));
 301                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 302                                 upper_32_bits(evt->dma));
 303                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 304                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 305                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 306         }
 307
 308         return 0;
 309 }
 310
 311 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 312 {
 313         struct dwc3_event_buffer        *evt;
 314         int                             n;
 315
 316         for (n = 0; n < dwc->num_event_buffers; n++) {
 317                 evt = dwc->ev_buffs[n];
 318
 319                 evt->lpos = 0;
 320
 321                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 322                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 323                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 324                                 | DWC3_GEVNTSIZ_SIZE(0));
 325                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 326         }
 327 }
 328
 329 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 330 {
 331         if (!dwc->has_hibernation)
 332                 return 0;
 333
 334         if (!dwc->nr_scratch)
 335                 return 0;
 336
 337         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 338                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 339         if (!dwc->scratchbuf)
 340                 return -ENOMEM;
 341
 342         return 0;
 343 }
 344
 345 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 346 {
 347         dma_addr_t scratch_addr;
 348         u32 param;
 349         int ret;
 350
 351         if (!dwc->has_hibernation)
 352                 return 0;
 353
 354         if (!dwc->nr_scratch)
 355                 return 0;
 356
 357         scratch_addr = dma_map_single(dwc->scratchbuf,
 358                                       dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 359                                       DMA_BIDIRECTIONAL);
 360         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 361                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 362                 ret = -EFAULT;
 363                 goto err0;
 364         }
 365
 366         dwc->scratch_addr = scratch_addr;
 367
 368         param = lower_32_bits(scratch_addr);
 369
 370         ret = dwc3_send_gadget_generic_command(dwc,
 371                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 372         if (ret < 0)
 373                 goto err1;
 374
 375         param = upper_32_bits(scratch_addr);
 376
 377         ret = dwc3_send_gadget_generic_command(dwc,
 378                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 379         if (ret < 0)
 380                 goto err1;
 381
 382         return 0;
 383
 384 err1:
 385         dma_unmap_single(scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 386                          DMA_BIDIRECTIONAL);
 387
 388 err0:
 389         return ret;
 390 }
 391
 392 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 393 {
 394         if (!dwc->has_hibernation)
 395                 return;
 396
 397         if (!dwc->nr_scratch)
 398                 return;
 399
 400         dma_unmap_single(dwc->scratch_addr, dwc->nr_scratch *
 401                          DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 402         kfree(dwc->scratchbuf);
 403 }
 404
 405 static void dwc3_core_num_eps(struct dwc3 *dwc)
 406 {
 407         struct dwc3_hwparams    *parms = &dwc->hwparams;
 408
 409         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 410         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 411
 412         dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
 413                         dwc->num_in_eps, dwc->num_out_eps);
 414 }
 415
 416 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 417 {
 418         struct dwc3_hwparams    *parms = &dwc->hwparams;
 419
 420         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 421         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 422         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 423         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 424         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 425         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 426         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 427         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 428         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 429 }
 430
 431 static void dwc3_hsphy_mode_setup(struct dwc3 *dwc)
 432 {
 433         enum usb_phy_interface hsphy_mode = dwc->hsphy_mode;
 434         u32 reg;
 435
 436         /* Set dwc3 usb2 phy config */
 437         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 438
 439         switch (hsphy_mode) {
 440         case USBPHY_INTERFACE_MODE_UTMI:
 441                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 442                         DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 443                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 444                         DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 445                 break;
 446         case USBPHY_INTERFACE_MODE_UTMIW:
 447                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 448                         DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 449                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 450                         DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 451                 break;
 452         default:
 453                 break;
 454         }
 455
 456         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 457 }
 458
 459 /**
 460  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 461  * @dwc: Pointer to our controller context structure
 462  */
 463 static void dwc3_phy_setup(struct dwc3 *dwc)
 464 {
 465         u32 reg;
 466
 467         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 468
 469         /*
 470          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 471          * to '0' during coreConsultant configuration. So default value
 472          * will be '0' when the core is reset. Application needs to set it
 473          * to '1' after the core initialization is completed.
 474          */
 475         if (dwc->revision > DWC3_REVISION_194A)
 476                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 477
 478         if (dwc->u2ss_inp3_quirk)
 479                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 480
 481         if (dwc->req_p1p2p3_quirk)
 482                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 483
 484         if (dwc->del_p1p2p3_quirk)
 485                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 486
 487         if (dwc->del_phy_power_chg_quirk)
 488                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 489
 490         if (dwc->lfps_filter_quirk)
 491                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 492
 493         if (dwc->rx_detect_poll_quirk)
 494                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 495
 496         if (dwc->tx_de_emphasis_quirk)
 497                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 498
 499         if (dwc->dis_u3_susphy_quirk)
 500                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 501
 502         if (dwc->dis_del_phy_power_chg_quirk)
 503                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 504
 505         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 506
 507         dwc3_hsphy_mode_setup(dwc);
 508
 509         mdelay(100);
 510
 511         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 512
 513         /*
 514          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 515          * '0' during coreConsultant configuration. So default value will
 516          * be '0' when the core is reset. Application needs to set it to
 517          * '1' after the core initialization is completed.
 518          */
 519         if (dwc->revision > DWC3_REVISION_194A)
 520                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 521
 522         if (dwc->dis_u2_susphy_quirk)
 523                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 524
 525         if (dwc->dis_enblslpm_quirk)
 526                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 527
 528         if (dwc->dis_u2_freeclk_exists_quirk)
 529                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 530
 531         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 532
 533         mdelay(100);
 534 }
 535
 536 /* set global incr burst type configuration registers */
 537 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 538 {
 539         struct udevice *dev = dwc->dev;
 540         u32 cfg;
 541
 542         if (!dwc->incrx_size)
 543                 return;
 544
 545         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 546
 547         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 548         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 549         if (dwc->incrx_mode)
 550                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 551         switch (dwc->incrx_size) {
 552         case 256:
 553                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 554                 break;
 555         case 128:
 556                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 557                 break;
 558         case 64:
 559                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 560                 break;
 561         case 32:
 562                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 563                 break;
 564         case 16:
 565                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 566                 break;
 567         case 8:
 568                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 569                 break;
 570         case 4:
 571                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 572                 break;
 573         case 1:
 574                 break;
 575         default:
 576                 dev_err(dev, "Invalid property\n");
 577                 break;
 578         }
 579
 580         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 581 }
 582
 583 /**
 584  * dwc3_core_init - Low-level initialization of DWC3 Core
 585  * @dwc: Pointer to our controller context structure
 586  *
 587  * Returns 0 on success otherwise negative errno.
 588  */
 589 static int dwc3_core_init(struct dwc3 *dwc)
 590 {
 591         unsigned long           timeout;
 592         u32                     hwparams4 = dwc->hwparams.hwparams4;
 593         u32                     reg;
 594         int                     ret;
 595
 596         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 597         /* This should read as U3 followed by revision number */
 598         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
 599                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 600                 ret = -ENODEV;
 601                 goto err0;
 602         }
 603         dwc->revision = reg;
 604
 605         /* Handle USB2.0-only core configuration */
 606         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 607                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 608                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 609                         dwc->maximum_speed = USB_SPEED_HIGH;
 610         }
 611
 612         /* issue device SoftReset too */
 613         timeout = 5000;
 614         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 615         while (timeout--) {
 616                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 617                 if (!(reg & DWC3_DCTL_CSFTRST))
 618                         break;
 619         };
 620
 621         if (!timeout) {
 622                 dev_err(dwc->dev, "Reset Timed Out\n");
 623                 ret = -ETIMEDOUT;
 624                 goto err0;
 625         }
 626
 627         dwc3_phy_setup(dwc);
 628
 629         ret = dwc3_core_soft_reset(dwc);
 630         if (ret)
 631                 goto err0;
 632
 633         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 634         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 635
 636         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 637         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 638                 /**
 639                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 640                  * issue which would cause xHCI compliance tests to fail.
 641                  *
 642                  * Because of that we cannot enable clock gating on such
 643                  * configurations.
 644                  *
 645                  * Refers to:
 646                  *
 647                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 648                  * SOF/ITP Mode Used
 649                  */
 650                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 651                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 652                                 (dwc->revision >= DWC3_REVISION_210A &&
 653                                 dwc->revision <= DWC3_REVISION_250A))
 654                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 655                 else
 656                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 657                 break;
 658         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 659                 /* enable hibernation here */
 660                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 661
 662                 /*
 663                  * REVISIT Enabling this bit so that host-mode hibernation
 664                  * will work. Device-mode hibernation is not yet implemented.
 665                  */
 666                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 667                 break;
 668         default:
 669                 dev_dbg(dwc->dev, "No power optimization available\n");
 670         }
 671
 672         /* check if current dwc3 is on simulation board */
 673         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 674                 dev_dbg(dwc->dev, "it is on FPGA board\n");
 675                 dwc->is_fpga = true;
 676         }
 677
 678         if(dwc->disable_scramble_quirk && !dwc->is_fpga)
 679                 WARN(true,
 680                      "disable_scramble cannot be used on non-FPGA builds\n");
 681
 682         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 683                 reg |= DWC3_GCTL_DISSCRAMBLE;
 684         else
 685                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 686
 687         if (dwc->u2exit_lfps_quirk)
 688                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 689
 690         /*
 691          * WORKAROUND: DWC3 revisions <1.90a have a bug
 692          * where the device can fail to connect at SuperSpeed
 693          * and falls back to high-speed mode which causes
 694          * the device to enter a Connect/Disconnect loop
 695          */
 696         if (dwc->revision < DWC3_REVISION_190A)
 697                 reg |= DWC3_GCTL_U2RSTECN;
 698
 699         dwc3_core_num_eps(dwc);
 700
 701         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 702
 703         ret = dwc3_alloc_scratch_buffers(dwc);
 704         if (ret)
 705                 goto err0;
 706
 707         ret = dwc3_setup_scratch_buffers(dwc);
 708         if (ret)
 709                 goto err1;
 710
 711         /* Adjust Frame Length */
 712         dwc3_frame_length_adjustment(dwc, dwc->fladj);
 713
 714         /* Adjust Reference Clock Period */
 715         dwc3_ref_clk_period(dwc);
 716
 717         dwc3_set_incr_burst_type(dwc);
 718
 719         return 0;
 720
 721 err1:
 722         dwc3_free_scratch_buffers(dwc);
 723
 724 err0:
 725         return ret;
 726 }
 727
 728 static void dwc3_core_exit(struct dwc3 *dwc)
 729 {
 730         dwc3_free_scratch_buffers(dwc);
 731 }
 732
 733 static int dwc3_core_init_mode(struct dwc3 *dwc)
 734 {
 735         int ret;
 736
 737         switch (dwc->dr_mode) {
 738         case USB_DR_MODE_PERIPHERAL:
 739                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 740                 ret = dwc3_gadget_init(dwc);
 741                 if (ret) {
 742                         dev_err(dwc->dev, "failed to initialize gadget\n");
 743                         return ret;
 744                 }
 745                 break;
 746         case USB_DR_MODE_HOST:
 747                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 748                 ret = dwc3_host_init(dwc);
 749                 if (ret) {
 750                         dev_err(dwc->dev, "failed to initialize host\n");
 751                         return ret;
 752                 }
 753                 break;
 754         case USB_DR_MODE_OTG:
 755                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 756                 ret = dwc3_host_init(dwc);
 757                 if (ret) {
 758                         dev_err(dwc->dev, "failed to initialize host\n");
 759                         return ret;
 760                 }
 761
 762                 ret = dwc3_gadget_init(dwc);
 763                 if (ret) {
 764                         dev_err(dwc->dev, "failed to initialize gadget\n");
 765                         return ret;
 766                 }
 767                 break;
 768         default:
 769                 dev_err(dwc->dev,
 770                         "Unsupported mode of operation %d\n", dwc->dr_mode);
 771                 return -EINVAL;
 772         }
 773
 774         return 0;
 775 }
 776
 777 static void dwc3_gadget_run(struct dwc3 *dwc)
 778 {
 779         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
 780         mdelay(100);
 781 }
 782
 783 static void dwc3_core_stop(struct dwc3 *dwc)
 784 {
 785         u32 reg;
 786
 787         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 788         dwc3_writel(dwc->regs, DWC3_DCTL, reg & ~(DWC3_DCTL_RUN_STOP));
 789 }
 790
 791 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 792 {
 793         switch (dwc->dr_mode) {
 794         case USB_DR_MODE_PERIPHERAL:
 795                 dwc3_gadget_exit(dwc);
 796                 break;
 797         case USB_DR_MODE_HOST:
 798                 dwc3_host_exit(dwc);
 799                 break;
 800         case USB_DR_MODE_OTG:
 801                 dwc3_host_exit(dwc);
 802                 dwc3_gadget_exit(dwc);
 803                 break;
 804         default:
 805                 /* do nothing */
 806                 break;
 807         }
 808
 809         /*
 810          * switch back to peripheral mode
 811          * This enables the phy to enter idle and then, if enabled, suspend.
 812          */
 813         dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 814         dwc3_gadget_run(dwc);
 815 }
 816
 817 #define DWC3_ALIGN_MASK         (16 - 1)
 818
 819 /**
 820  * dwc3_uboot_init - dwc3 core uboot initialization code
 821  * @dwc3_dev: struct dwc3_device containing initialization data
 822  *
 823  * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
 824  * kernel driver). Pointer to dwc3_device should be passed containing
 825  * base address and other initialization data. Returns '0' on success and
 826  * a negative value on failure.
 827  *
 828  * Generally called from board_usb_init() implemented in board file.
 829  */
 830 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 831 {
 832         struct dwc3             *dwc;
 833         struct device           *dev = NULL;
 834         u8                      lpm_nyet_threshold;
 835         u8                      tx_de_emphasis;
 836         u8                      hird_threshold;
 837
 838         int                     ret;
 839
 840         void                    *mem;
 841
 842         mem = devm_kzalloc((struct udevice *)dev,
 843                            sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 844         if (!mem)
 845                 return -ENOMEM;
 846
 847         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 848         dwc->mem = mem;
 849
 850         dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
 851                                         DWC3_GLOBALS_REGS_START);
 852
 853         /* default to highest possible threshold */
 854         lpm_nyet_threshold = 0xff;
 855
 856         /* default to -3.5dB de-emphasis */
 857         tx_de_emphasis = 1;
 858
 859         /*
 860          * default to assert utmi_sleep_n and use maximum allowed HIRD
 861          * threshold value of 0b1100
 862          */
 863         hird_threshold = 12;
 864
 865         dwc->maximum_speed = dwc3_dev->maximum_speed;
 866         dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
 867         if (dwc3_dev->lpm_nyet_threshold)
 868                 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
 869         dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
 870         if (dwc3_dev->hird_threshold)
 871                 hird_threshold = dwc3_dev->hird_threshold;
 872
 873         dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
 874         dwc->dr_mode = dwc3_dev->dr_mode;
 875
 876         dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
 877         dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
 878         dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
 879         dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
 880         dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
 881         dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
 882         dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
 883         dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
 884         dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
 885         dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
 886         dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
 887         dwc->dis_tx_ipgap_linecheck_quirk = dwc3_dev->dis_tx_ipgap_linecheck_quirk;
 888         dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
 889         dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
 890
 891         dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
 892         if (dwc3_dev->tx_de_emphasis)
 893                 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
 894
 895         /* default to superspeed if no maximum_speed passed */
 896         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 897                 dwc->maximum_speed = USB_SPEED_SUPER;
 898
 899         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 900         dwc->tx_de_emphasis = tx_de_emphasis;
 901
 902         dwc->hird_threshold = hird_threshold
 903                 | (dwc->is_utmi_l1_suspend << 4);
 904
 905         dwc->hsphy_mode = dwc3_dev->hsphy_mode;
 906
 907         dwc->index = dwc3_dev->index;
 908
 909         dwc3_cache_hwparams(dwc);
 910
 911         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 912         if (ret) {
 913                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 914                 return -ENOMEM;
 915         }
 916
 917         if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 918                 dwc->dr_mode = USB_DR_MODE_HOST;
 919         else if (!IS_ENABLED(CONFIG_USB_HOST))
 920                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
 921
 922         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
 923                 dwc->dr_mode = USB_DR_MODE_OTG;
 924
 925         ret = dwc3_core_init(dwc);
 926         if (ret) {
 927                 dev_err(dwc->dev, "failed to initialize core\n");
 928                 goto err0;
 929         }
 930
 931         ret = dwc3_event_buffers_setup(dwc);
 932         if (ret) {
 933                 dev_err(dwc->dev, "failed to setup event buffers\n");
 934                 goto err1;
 935         }
 936
 937         ret = dwc3_core_init_mode(dwc);
 938         if (ret)
 939                 goto err2;
 940
 941         list_add_tail(&dwc->list, &dwc3_list);
 942
 943         return 0;
 944
 945 err2:
 946         dwc3_event_buffers_cleanup(dwc);
 947
 948 err1:
 949         dwc3_core_exit(dwc);
 950
 951 err0:
 952         dwc3_free_event_buffers(dwc);
 953
 954         return ret;
 955 }
 956
 957 /**
 958  * dwc3_uboot_exit - dwc3 core uboot cleanup code
 959  * @index: index of this controller
 960  *
 961  * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
 962  * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
 963  * should be passed and should match with the index passed in
 964  * dwc3_device during init.
 965  *
 966  * Generally called from board file.
 967  */
 968 void dwc3_uboot_exit(int index)
 969 {
 970         struct dwc3 *dwc;
 971
 972         list_for_each_entry(dwc, &dwc3_list, list) {
 973                 if (dwc->index != index)
 974                         continue;
 975
 976                 dwc3_core_exit_mode(dwc);
 977                 dwc3_event_buffers_cleanup(dwc);
 978                 dwc3_free_event_buffers(dwc);
 979                 dwc3_core_exit(dwc);
 980                 list_del(&dwc->list);
 981                 kfree(dwc->mem);
 982                 break;
 983         }
 984 }
 985
 986 /**
 987  * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
 988  * @dev: device of this controller
 989  *
 990  * Invokes dwc3 gadget interrupts.
 991  *
 992  * Generally called from board file.
 993  */
 994 void dwc3_uboot_handle_interrupt(struct udevice *dev)
 995 {
 996         struct dwc3 *dwc = NULL;
 997
 998         list_for_each_entry(dwc, &dwc3_list, list) {
 999                 if (dwc->dev != dev)
1000                         continue;
1001
1002                 dwc3_gadget_uboot_handle_interrupt(dwc);
1003                 break;
1004         }
1005 }
1006
1007 MODULE_ALIAS("platform:dwc3");
1008 MODULE_AUTHOR("Felipe Balbi <[email protected]>");
1009 MODULE_LICENSE("GPL v2");
1010 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
1011
1012 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
1013 int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
1014 {
1015         int ret;
1016
1017         ret = generic_phy_get_bulk(dev, phys);
1018         if (ret)
1019                 return ret;
1020
1021         ret = generic_phy_init_bulk(phys);
1022         if (ret)
1023                 return ret;
1024
1025         ret = generic_phy_power_on_bulk(phys);
1026         if (ret)
1027                 generic_phy_exit_bulk(phys);
1028
1029         return ret;
1030 }
1031
1032 int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys)
1033 {
1034         int ret;
1035
1036         ret = generic_phy_power_off_bulk(phys);
1037         ret |= generic_phy_exit_bulk(phys);
1038         return ret;
1039 }
1040 #endif
1041
1042 #if CONFIG_IS_ENABLED(DM_USB)
1043 void dwc3_of_parse(struct dwc3 *dwc)
1044 {
1045         const u8 *tmp;
1046         struct udevice *dev = dwc->dev;
1047         u8 lpm_nyet_threshold;
1048         u8 tx_de_emphasis;
1049         u8 hird_threshold;
1050         u32 val;
1051         int i;
1052
1053         /* default to highest possible threshold */
1054         lpm_nyet_threshold = 0xff;
1055
1056         /* default to -3.5dB de-emphasis */
1057         tx_de_emphasis = 1;
1058
1059         /*
1060          * default to assert utmi_sleep_n and use maximum allowed HIRD
1061          * threshold value of 0b1100
1062          */
1063         hird_threshold = 12;
1064
1065         dwc->hsphy_mode = usb_get_phy_mode(dev_ofnode(dev));
1066
1067         dwc->has_lpm_erratum = dev_read_bool(dev,
1068                                 "snps,has-lpm-erratum");
1069         tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
1070         if (tmp)
1071                 lpm_nyet_threshold = *tmp;
1072
1073         dwc->is_utmi_l1_suspend = dev_read_bool(dev,
1074                                 "snps,is-utmi-l1-suspend");
1075         tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
1076         if (tmp)
1077                 hird_threshold = *tmp;
1078
1079         dwc->disable_scramble_quirk = dev_read_bool(dev,
1080                                 "snps,disable_scramble_quirk");
1081         dwc->u2exit_lfps_quirk = dev_read_bool(dev,
1082                                 "snps,u2exit_lfps_quirk");
1083         dwc->u2ss_inp3_quirk = dev_read_bool(dev,
1084                                 "snps,u2ss_inp3_quirk");
1085         dwc->req_p1p2p3_quirk = dev_read_bool(dev,
1086                                 "snps,req_p1p2p3_quirk");
1087         dwc->del_p1p2p3_quirk = dev_read_bool(dev,
1088                                 "snps,del_p1p2p3_quirk");
1089         dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
1090                                 "snps,del_phy_power_chg_quirk");
1091         dwc->lfps_filter_quirk = dev_read_bool(dev,
1092                                 "snps,lfps_filter_quirk");
1093         dwc->rx_detect_poll_quirk = dev_read_bool(dev,
1094                                 "snps,rx_detect_poll_quirk");
1095         dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
1096                                 "snps,dis_u3_susphy_quirk");
1097         dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
1098                                 "snps,dis_u2_susphy_quirk");
1099         dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
1100                                 "snps,dis-del-phy-power-chg-quirk");
1101         dwc->dis_tx_ipgap_linecheck_quirk = dev_read_bool(dev,
1102                                 "snps,dis-tx-ipgap-linecheck-quirk");
1103         dwc->dis_enblslpm_quirk = dev_read_bool(dev,
1104                                 "snps,dis_enblslpm_quirk");
1105         dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
1106                                 "snps,dis-u2-freeclk-exists-quirk");
1107         dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
1108                                 "snps,tx_de_emphasis_quirk");
1109         tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
1110         if (tmp)
1111                 tx_de_emphasis = *tmp;
1112
1113         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1114         dwc->tx_de_emphasis = tx_de_emphasis;
1115
1116         dwc->hird_threshold = hird_threshold
1117                 | (dwc->is_utmi_l1_suspend << 4);
1118
1119         dev_read_u32(dev, "snps,quirk-frame-length-adjustment", &dwc->fladj);
1120
1121         /*
1122          * Handle property "snps,incr-burst-type-adjustment".
1123          * Get the number of value from this property:
1124          * result <= 0, means this property is not supported.
1125          * result = 1, means INCRx burst mode supported.
1126          * result > 1, means undefined length burst mode supported.
1127          */
1128         dwc->incrx_mode = INCRX_BURST_MODE;
1129         dwc->incrx_size = 0;
1130         for (i = 0; i < 8; i++) {
1131                 if (dev_read_u32_index(dev, "snps,incr-burst-type-adjustment",
1132                                        i, &val))
1133                         break;
1134
1135                 dwc->incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
1136                 dwc->incrx_size = max(dwc->incrx_size, val);
1137         }
1138 }
1139
1140 int dwc3_init(struct dwc3 *dwc)
1141 {
1142         int ret;
1143         u32 reg;
1144
1145         dwc3_cache_hwparams(dwc);
1146
1147         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1148         if (ret) {
1149                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1150                 return -ENOMEM;
1151         }
1152
1153         ret = dwc3_core_init(dwc);
1154         if (ret) {
1155                 dev_err(dwc->dev, "failed to initialize core\n");
1156                 goto core_fail;
1157         }
1158
1159         ret = dwc3_event_buffers_setup(dwc);
1160         if (ret) {
1161                 dev_err(dwc->dev, "failed to setup event buffers\n");
1162                 goto event_fail;
1163         }
1164
1165         if (dwc->revision >= DWC3_REVISION_250A) {
1166                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1167
1168                 /*
1169                  * Enable hardware control of sending remote wakeup
1170                  * in HS when the device is in the L1 state.
1171                  */
1172                 if (dwc->revision >= DWC3_REVISION_290A)
1173                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1174
1175                 if (dwc->dis_tx_ipgap_linecheck_quirk)
1176                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1177
1178                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1179         }
1180
1181         if (dwc->dr_mode == USB_DR_MODE_HOST ||
1182             dwc->dr_mode == USB_DR_MODE_OTG) {
1183                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1184
1185                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1186
1187                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1188         }
1189
1190         ret = dwc3_core_init_mode(dwc);
1191         if (ret)
1192                 goto mode_fail;
1193
1194         return 0;
1195
1196 mode_fail:
1197         dwc3_event_buffers_cleanup(dwc);
1198
1199 event_fail:
1200         dwc3_core_exit(dwc);
1201
1202 core_fail:
1203         dwc3_free_event_buffers(dwc);
1204
1205         return ret;
1206 }
1207
1208 void dwc3_remove(struct dwc3 *dwc)
1209 {
1210         dwc3_core_exit_mode(dwc);
1211         dwc3_event_buffers_cleanup(dwc);
1212         dwc3_free_event_buffers(dwc);
1213         dwc3_core_stop(dwc);
1214         dwc3_core_exit(dwc);
1215         kfree(dwc->mem);
1216 }
1217 #endif