drivers/mtd/nand/raw/atmel/nand-controller.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2022 ATMEL
   4  * Copyright 2017 Free Electrons
   5  *
   6  * Author: Boris Brezillon <[email protected]>
   7  *
   8  * Derived from the atmel_nand.c driver which contained the following
   9  * copyrights:
  10  *
  11  *   Copyright 2003 Rick Bronson
  12  *
  13  *   Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
  14  *      Copyright 2001 Thomas Gleixner ([email protected])
  15  *
  16  *   Derived from drivers/mtd/spia.c (removed in v3.8)
  17  *      Copyright 2000 Steven J. Hill ([email protected])
  18  *
  19  *
  20  *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  21  *      Richard Genoud ([email protected]), Adeneo Copyright 2007
  22  *
  23  *   Derived from Das U-Boot source code
  24  *      (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  25  *      Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  26  *
  27  *   Add Programmable Multibit ECC support for various AT91 SoC
  28  *      Copyright 2012 ATMEL, Hong Xu
  29  *
  30  *   Add Nand Flash Controller support for SAMA5 SoC
  31  *      Copyright 2013 ATMEL, Josh Wu ([email protected])
  32  *
  33  *   Port from Linux
  34  *      Balamanikandan Gunasundar([email protected])
  35  *      Copyright (C) 2022 Microchip Technology Inc.
  36  *
  37  * A few words about the naming convention in this file. This convention
  38  * applies to structure and function names.
  39  *
  40  * Prefixes:
  41  *
  42  * - atmel_nand_: all generic structures/functions
  43  * - atmel_smc_nand_: all structures/functions specific to the SMC interface
  44  *                    (at91sam9 and avr32 SoCs)
  45  * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
  46  *                     (sama5 SoCs and later)
  47  * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
  48  *               that is available in the HSMC block
  49  * - <soc>_nand_: all SoC specific structures/functions
  50  */
  51
  52 #include <asm-generic/gpio.h>
  53 #include <clk.h>
  54 #include <dm/device_compat.h>
  55 #include <dm/devres.h>
  56 #include <dm/of_addr.h>
  57 #include <dm/of_access.h>
  58 #include <dm/uclass.h>
  59 #include <linux/completion.h>
  60 #include <linux/io.h>
  61 #include <linux/iopoll.h>
  62 #include <linux/ioport.h>
  63 #include <linux/mfd/syscon/atmel-matrix.h>
  64 #include <linux/mfd/syscon/atmel-smc.h>
  65 #include <linux/mtd/rawnand.h>
  66 #include <linux/mtd/mtd.h>
  67 #include <linux/time.h>
  68 #include <mach/at91_sfr.h>
  69 #include <nand.h>
  70 #include <regmap.h>
  71 #include <syscon.h>
  72
  73 #include "pmecc.h"
  74
  75 #define ATMEL_HSMC_NFC_CFG                      0x0
  76 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)         (((x) / 4) << 24)
  77 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK       GENMASK(30, 24)
  78 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul)        (((cyc) << 16) | ((mul) << 20))
  79 #define ATMEL_HSMC_NFC_CFG_DTO_MAX              GENMASK(22, 16)
  80 #define ATMEL_HSMC_NFC_CFG_RBEDGE               BIT(13)
  81 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE         BIT(12)
  82 #define ATMEL_HSMC_NFC_CFG_RSPARE               BIT(9)
  83 #define ATMEL_HSMC_NFC_CFG_WSPARE               BIT(8)
  84 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK        GENMASK(2, 0)
  85 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x)          (fls((x) / 512) - 1)
  86
  87 #define ATMEL_HSMC_NFC_CTRL                     0x4
  88 #define ATMEL_HSMC_NFC_CTRL_EN                  BIT(0)
  89 #define ATMEL_HSMC_NFC_CTRL_DIS                 BIT(1)
  90
  91 #define ATMEL_HSMC_NFC_SR                       0x8
  92 #define ATMEL_HSMC_NFC_IER                      0xc
  93 #define ATMEL_HSMC_NFC_IDR                      0x10
  94 #define ATMEL_HSMC_NFC_IMR                      0x14
  95 #define ATMEL_HSMC_NFC_SR_ENABLED               BIT(1)
  96 #define ATMEL_HSMC_NFC_SR_RB_RISE               BIT(4)
  97 #define ATMEL_HSMC_NFC_SR_RB_FALL               BIT(5)
  98 #define ATMEL_HSMC_NFC_SR_BUSY                  BIT(8)
  99 #define ATMEL_HSMC_NFC_SR_WR                    BIT(11)
 100 #define ATMEL_HSMC_NFC_SR_CSID                  GENMASK(14, 12)
 101 #define ATMEL_HSMC_NFC_SR_XFRDONE               BIT(16)
 102 #define ATMEL_HSMC_NFC_SR_CMDDONE               BIT(17)
 103 #define ATMEL_HSMC_NFC_SR_DTOE                  BIT(20)
 104 #define ATMEL_HSMC_NFC_SR_UNDEF                 BIT(21)
 105 #define ATMEL_HSMC_NFC_SR_AWB                   BIT(22)
 106 #define ATMEL_HSMC_NFC_SR_NFCASE                BIT(23)
 107 #define ATMEL_HSMC_NFC_SR_ERRORS                (ATMEL_HSMC_NFC_SR_DTOE | \
 108                                                  ATMEL_HSMC_NFC_SR_UNDEF | \
 109                                                  ATMEL_HSMC_NFC_SR_AWB | \
 110                                                  ATMEL_HSMC_NFC_SR_NFCASE)
 111 #define ATMEL_HSMC_NFC_SR_RBEDGE(x)             BIT((x) + 24)
 112
 113 #define ATMEL_HSMC_NFC_ADDR                     0x18
 114 #define ATMEL_HSMC_NFC_BANK                     0x1c
 115
 116 #define ATMEL_NFC_MAX_RB_ID                     7
 117
 118 #define ATMEL_NFC_SRAM_SIZE                     0x2400
 119
 120 #define ATMEL_NFC_CMD(pos, cmd)                 ((cmd) << (((pos) * 8) + 2))
 121 #define ATMEL_NFC_VCMD2                         BIT(18)
 122 #define ATMEL_NFC_ACYCLE(naddrs)                ((naddrs) << 19)
 123 #define ATMEL_NFC_CSID(cs)                      ((cs) << 22)
 124 #define ATMEL_NFC_DATAEN                        BIT(25)
 125 #define ATMEL_NFC_NFCWR                         BIT(26)
 126
 127 #define ATMEL_NFC_MAX_ADDR_CYCLES               5
 128
 129 #define ATMEL_NAND_ALE_OFFSET                   BIT(21)
 130 #define ATMEL_NAND_CLE_OFFSET                   BIT(22)
 131
 132 #define DEFAULT_TIMEOUT_MS                      1000
 133 #define MIN_DMA_LEN                             128
 134
 135 static struct nand_ecclayout atmel_pmecc_oobinfo;
 136
 137 struct nand_controller_ops {
 138         int (*attach_chip)(struct nand_chip *chip);
 139         int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
 140                                     const struct nand_data_interface *conf);
 141 };
 142
 143 struct nand_controller {
 144         const struct nand_controller_ops *ops;
 145 };
 146
 147 enum atmel_nand_rb_type {
 148         ATMEL_NAND_NO_RB,
 149         ATMEL_NAND_NATIVE_RB,
 150         ATMEL_NAND_GPIO_RB,
 151 };
 152
 153 struct atmel_nand_rb {
 154         enum atmel_nand_rb_type type;
 155         union {
 156                 struct gpio_desc gpio;
 157                 int id;
 158         };
 159 };
 160
 161 struct atmel_nand_cs {
 162         int id;
 163         struct atmel_nand_rb rb;
 164         struct gpio_desc csgpio;
 165         struct {
 166                 void __iomem *virt;
 167                 dma_addr_t dma;
 168         } io;
 169
 170         struct atmel_smc_cs_conf smcconf;
 171 };
 172
 173 struct atmel_nand {
 174         struct list_head node;
 175         struct udevice *dev;
 176         struct nand_chip base;
 177         struct atmel_nand_cs *activecs;
 178         struct atmel_pmecc_user *pmecc;
 179         struct gpio_desc cdgpio;
 180         int numcs;
 181         struct nand_controller *controller;
 182         struct atmel_nand_cs cs[];
 183 };
 184
 185 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
 186 {
 187         return container_of(chip, struct atmel_nand, base);
 188 }
 189
 190 enum atmel_nfc_data_xfer {
 191         ATMEL_NFC_NO_DATA,
 192         ATMEL_NFC_READ_DATA,
 193         ATMEL_NFC_WRITE_DATA,
 194 };
 195
 196 struct atmel_nfc_op {
 197         u8 cs;
 198         u8 ncmds;
 199         u8 cmds[2];
 200         u8 naddrs;
 201         u8 addrs[5];
 202         enum atmel_nfc_data_xfer data;
 203         u32 wait;
 204         u32 errors;
 205 };
 206
 207 struct atmel_nand_controller;
 208 struct atmel_nand_controller_caps;
 209
 210 struct atmel_nand_controller_ops {
 211         int (*probe)(struct udevice *udev,
 212                      const struct atmel_nand_controller_caps *caps);
 213         int (*remove)(struct atmel_nand_controller *nc);
 214         void (*nand_init)(struct atmel_nand_controller *nc,
 215                           struct atmel_nand *nand);
 216         int (*ecc_init)(struct nand_chip *chip);
 217         int (*setup_data_interface)(struct atmel_nand *nand, int csline,
 218                                     const struct nand_data_interface *conf);
 219 };
 220
 221 struct atmel_nand_controller_caps {
 222         bool has_dma;
 223         bool legacy_of_bindings;
 224         u32 ale_offs;
 225         u32 cle_offs;
 226         const char *ebi_csa_regmap_name;
 227         const struct atmel_nand_controller_ops *ops;
 228 };
 229
 230 struct atmel_nand_controller {
 231         struct nand_controller base;
 232         const struct atmel_nand_controller_caps *caps;
 233         struct udevice *dev;
 234         struct regmap *smc;
 235         struct dma_chan *dmac;
 236         struct atmel_pmecc *pmecc;
 237         struct list_head chips;
 238         struct clk *mck;
 239 };
 240
 241 static inline struct atmel_nand_controller *
 242 to_nand_controller(struct nand_controller *ctl)
 243 {
 244         return container_of(ctl, struct atmel_nand_controller, base);
 245 }
 246
 247 struct atmel_smc_nand_ebi_csa_cfg {
 248         u32 offs;
 249         u32 nfd0_on_d16;
 250 };
 251
 252 struct atmel_smc_nand_controller {
 253         struct atmel_nand_controller base;
 254         struct regmap *ebi_csa_regmap;
 255         struct atmel_smc_nand_ebi_csa_cfg *ebi_csa;
 256 };
 257
 258 static inline struct atmel_smc_nand_controller *
 259 to_smc_nand_controller(struct nand_controller *ctl)
 260 {
 261         return container_of(to_nand_controller(ctl),
 262                             struct atmel_smc_nand_controller, base);
 263 }
 264
 265 struct atmel_hsmc_nand_controller {
 266         struct atmel_nand_controller base;
 267         struct {
 268                 struct gen_pool *pool;
 269                 void __iomem *virt;
 270                 dma_addr_t dma;
 271         } sram;
 272         const struct atmel_hsmc_reg_layout *hsmc_layout;
 273         struct regmap *io;
 274         struct atmel_nfc_op op;
 275         struct completion complete;
 276         int irq;
 277
 278         /* Only used when instantiating from legacy DT bindings. */
 279         struct clk *clk;
 280 };
 281
 282 static inline struct atmel_hsmc_nand_controller *
 283 to_hsmc_nand_controller(struct nand_controller *ctl)
 284 {
 285         return container_of(to_nand_controller(ctl),
 286                             struct atmel_hsmc_nand_controller, base);
 287 }
 288
 289 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
 290                                     int oobsize, int ecc_len)
 291 {
 292         int i;
 293
 294         layout->eccbytes = ecc_len;
 295
 296         /* ECC will occupy the last ecc_len bytes continuously */
 297         for (i = 0; i < ecc_len; i++)
 298                 layout->eccpos[i] = oobsize - ecc_len + i;
 299
 300         layout->oobfree[0].offset = 2;
 301         layout->oobfree[0].length =
 302                 oobsize - ecc_len - layout->oobfree[0].offset;
 303 }
 304
 305 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
 306 {
 307         op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
 308         op->wait ^= status & op->wait;
 309
 310         return !op->wait || op->errors;
 311 }
 312
 313 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
 314                           unsigned int timeout_ms)
 315 {
 316         int ret;
 317         u32 status;
 318
 319         if (!timeout_ms)
 320                 timeout_ms = DEFAULT_TIMEOUT_MS;
 321
 322         if (poll)
 323                 ret = regmap_read_poll_timeout(nc->base.smc,
 324                                                ATMEL_HSMC_NFC_SR, status,
 325                                                atmel_nfc_op_done(&nc->op,
 326                                                                  status),
 327                                                0, timeout_ms);
 328         else
 329                 return -EOPNOTSUPP;
 330
 331         if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
 332                 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
 333                 ret = -ETIMEDOUT;
 334         }
 335
 336         if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
 337                 dev_err(nc->base.dev, "Access to an undefined area\n");
 338                 ret = -EIO;
 339         }
 340
 341         if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
 342                 dev_err(nc->base.dev, "Access while busy\n");
 343                 ret = -EIO;
 344         }
 345
 346         if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
 347                 dev_err(nc->base.dev, "Wrong access size\n");
 348                 ret = -EIO;
 349         }
 350
 351         return ret;
 352 }
 353
 354 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
 355 {
 356         int i;
 357
 358         for (i = 0; i < len; i++)
 359                 writeb(buf[i], addr);
 360 }
 361
 362 static void ioread8_rep(void *addr, uint8_t *buf, int len)
 363 {
 364         int i;
 365
 366         for (i = 0; i < len; i++)
 367                 buf[i] = readb(addr);
 368 }
 369
 370 static void ioread16_rep(void *addr, void *buf, int len)
 371 {
 372         int i;
 373         u16 *p = (u16 *)buf;
 374
 375         for (i = 0; i < len; i++)
 376                 p[i] = readw(addr);
 377 }
 378
 379 static void iowrite16_rep(void *addr, const void *buf, int len)
 380 {
 381         int i;
 382         u16 *p = (u16 *)buf;
 383
 384         for (i = 0; i < len; i++)
 385                 writew(p[i], addr);
 386 }
 387
 388 static u8 atmel_nand_read_byte(struct mtd_info *mtd)
 389 {
 390         struct nand_chip *chip = mtd_to_nand(mtd);
 391         struct atmel_nand *nand = to_atmel_nand(chip);
 392
 393         return ioread8(nand->activecs->io.virt);
 394 }
 395
 396 static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
 397 {
 398         struct nand_chip *chip = mtd_to_nand(mtd);
 399         struct atmel_nand *nand = to_atmel_nand(chip);
 400
 401         if (chip->options & NAND_BUSWIDTH_16)
 402                 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
 403         else
 404                 iowrite8(byte, nand->activecs->io.virt);
 405 }
 406
 407 static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 408 {
 409         struct nand_chip *chip = mtd_to_nand(mtd);
 410         struct atmel_nand *nand = to_atmel_nand(chip);
 411
 412         if (chip->options & NAND_BUSWIDTH_16)
 413                 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
 414         else
 415                 ioread8_rep(nand->activecs->io.virt, buf, len);
 416 }
 417
 418 static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 419 {
 420         struct nand_chip *chip = mtd_to_nand(mtd);
 421         struct atmel_nand *nand = to_atmel_nand(chip);
 422
 423         if (chip->options & NAND_BUSWIDTH_16)
 424                 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
 425         else
 426                 iowrite8_rep(nand->activecs->io.virt, buf, len);
 427 }
 428
 429 static int atmel_nand_dev_ready(struct mtd_info *mtd)
 430 {
 431         struct nand_chip  *chip = mtd_to_nand(mtd);
 432         struct atmel_nand *nand = to_atmel_nand(chip);
 433
 434         return dm_gpio_get_value(&nand->activecs->rb.gpio);
 435 }
 436
 437 static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
 438 {
 439         struct nand_chip *chip =  mtd_to_nand(mtd);
 440         struct atmel_nand *nand = to_atmel_nand(chip);
 441
 442         if (cs < 0 || cs >= nand->numcs) {
 443                 nand->activecs = NULL;
 444                 chip->dev_ready = NULL;
 445                 return;
 446         }
 447
 448         nand->activecs = &nand->cs[cs];
 449
 450         if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
 451                 chip->dev_ready = atmel_nand_dev_ready;
 452 }
 453
 454 static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
 455 {
 456         struct nand_chip *chip = mtd_to_nand(mtd);
 457         struct atmel_nand *nand = to_atmel_nand(chip);
 458         struct atmel_hsmc_nand_controller *nc;
 459         u32 status;
 460
 461         nc = to_hsmc_nand_controller(nand->controller);
 462
 463         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
 464
 465         return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
 466 }
 467
 468 static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
 469 {
 470         struct nand_chip *chip = mtd_to_nand(mtd);
 471         struct atmel_nand *nand = to_atmel_nand(chip);
 472         struct atmel_hsmc_nand_controller *nc;
 473
 474         nc = to_hsmc_nand_controller(nand->controller);
 475
 476         atmel_nand_select_chip(mtd, cs);
 477
 478         if (!nand->activecs) {
 479                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 480                              ATMEL_HSMC_NFC_CTRL_DIS);
 481                 return;
 482         }
 483
 484         if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
 485                 chip->dev_ready = atmel_hsmc_nand_dev_ready;
 486
 487         regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
 488                            ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
 489                            ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
 490                            ATMEL_HSMC_NFC_CFG_RSPARE |
 491                            ATMEL_HSMC_NFC_CFG_WSPARE,
 492                            ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
 493                            ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
 494                            ATMEL_HSMC_NFC_CFG_RSPARE);
 495         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 496                      ATMEL_HSMC_NFC_CTRL_EN);
 497 }
 498
 499 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
 500 {
 501         u8 *addrs = nc->op.addrs;
 502         unsigned int op = 0;
 503         u32 addr, val;
 504         int i, ret;
 505
 506         nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
 507
 508         for (i = 0; i < nc->op.ncmds; i++)
 509                 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
 510
 511         if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 512                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
 513
 514         op |= ATMEL_NFC_CSID(nc->op.cs) |
 515               ATMEL_NFC_ACYCLE(nc->op.naddrs);
 516
 517         if (nc->op.ncmds > 1)
 518                 op |= ATMEL_NFC_VCMD2;
 519
 520         addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
 521                (addrs[3] << 24);
 522
 523         if (nc->op.data != ATMEL_NFC_NO_DATA) {
 524                 op |= ATMEL_NFC_DATAEN;
 525                 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
 526
 527                 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
 528                         op |= ATMEL_NFC_NFCWR;
 529         }
 530
 531         /* Clear all flags. */
 532         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
 533
 534         /* Send the command. */
 535         regmap_write(nc->io, op, addr);
 536
 537         ret = atmel_nfc_wait(nc, poll, 0);
 538         if (ret)
 539                 dev_err(nc->base.dev,
 540                         "Failed to send NAND command (err = %d)!",
 541                         ret);
 542
 543         /* Reset the op state. */
 544         memset(&nc->op, 0, sizeof(nc->op));
 545
 546         return ret;
 547 }
 548
 549 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
 550                                      unsigned int ctrl)
 551 {
 552         struct nand_chip *chip = mtd_to_nand(mtd);
 553         struct atmel_nand *nand = to_atmel_nand(chip);
 554         struct atmel_hsmc_nand_controller *nc;
 555
 556         nc = to_hsmc_nand_controller(nand->controller);
 557
 558         if (ctrl & NAND_ALE) {
 559                 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 560                         return;
 561
 562                 nc->op.addrs[nc->op.naddrs++] = dat;
 563         } else if (ctrl & NAND_CLE) {
 564                 if (nc->op.ncmds > 1)
 565                         return;
 566
 567                 nc->op.cmds[nc->op.ncmds++] = dat;
 568         }
 569
 570         if (dat == NAND_CMD_NONE) {
 571                 nc->op.cs = nand->activecs->id;
 572                 atmel_nfc_exec_op(nc, true);
 573         }
 574 }
 575
 576 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 577                                 unsigned int ctrl)
 578 {
 579         struct nand_chip *chip = mtd_to_nand(mtd);
 580         struct atmel_nand *nand = to_atmel_nand(chip);
 581         struct atmel_nand_controller *nc;
 582
 583         nc = to_nand_controller(nand->controller);
 584
 585         if ((ctrl & NAND_CTRL_CHANGE) &&
 586             dm_gpio_is_valid(&nand->activecs->csgpio)) {
 587                 if (ctrl & NAND_NCE)
 588                         dm_gpio_set_value(&nand->activecs->csgpio, 0);
 589                 else
 590                         dm_gpio_set_value(&nand->activecs->csgpio, 1);
 591         }
 592
 593         if (ctrl & NAND_ALE)
 594                 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
 595         else if (ctrl & NAND_CLE)
 596                 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
 597 }
 598
 599 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
 600                                    bool oob_required)
 601 {
 602         struct mtd_info *mtd = nand_to_mtd(chip);
 603         struct atmel_nand *nand = to_atmel_nand(chip);
 604         struct atmel_hsmc_nand_controller *nc;
 605         int ret = -EIO;
 606
 607         nc = to_hsmc_nand_controller(nand->controller);
 608
 609         if (ret)
 610                 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
 611
 612         if (oob_required)
 613                 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
 614                             mtd->oobsize);
 615 }
 616
 617 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
 618                                      bool oob_required)
 619 {
 620         struct mtd_info *mtd = nand_to_mtd(chip);
 621         struct atmel_nand *nand = to_atmel_nand(chip);
 622         struct atmel_hsmc_nand_controller *nc;
 623         int ret = -EIO;
 624
 625         nc = to_hsmc_nand_controller(nand->controller);
 626
 627         if (ret)
 628                 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
 629
 630         if (oob_required)
 631                 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
 632                               mtd->oobsize);
 633 }
 634
 635 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
 636 {
 637         struct mtd_info *mtd = nand_to_mtd(chip);
 638         struct atmel_nand *nand = to_atmel_nand(chip);
 639         struct atmel_hsmc_nand_controller *nc;
 640
 641         nc = to_hsmc_nand_controller(nand->controller);
 642
 643         if (column >= 0) {
 644                 nc->op.addrs[nc->op.naddrs++] = column;
 645
 646                 /*
 647                  * 2 address cycles for the column offset on large page NANDs.
 648                  */
 649                 if (mtd->writesize > 512)
 650                         nc->op.addrs[nc->op.naddrs++] = column >> 8;
 651         }
 652
 653         if (page >= 0) {
 654                 nc->op.addrs[nc->op.naddrs++] = page;
 655                 nc->op.addrs[nc->op.naddrs++] = page >> 8;
 656
 657                 if (chip->options & NAND_ROW_ADDR_3)
 658                         nc->op.addrs[nc->op.naddrs++] = page >> 16;
 659         }
 660 }
 661
 662 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
 663 {
 664         struct atmel_nand *nand = to_atmel_nand(chip);
 665         struct atmel_nand_controller *nc;
 666         int ret;
 667
 668         nc = to_nand_controller(nand->controller);
 669
 670         if (raw)
 671                 return 0;
 672
 673         ret = atmel_pmecc_enable(nand->pmecc, op);
 674         if (ret)
 675                 dev_err(nc->dev,
 676                         "Failed to enable ECC engine (err = %d)\n", ret);
 677
 678         return ret;
 679 }
 680
 681 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
 682 {
 683         struct atmel_nand *nand = to_atmel_nand(chip);
 684
 685         if (!raw)
 686                 atmel_pmecc_disable(nand->pmecc);
 687 }
 688
 689 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
 690 {
 691         struct atmel_nand *nand = to_atmel_nand(chip);
 692         struct mtd_info *mtd = nand_to_mtd(chip);
 693         struct atmel_nand_controller *nc;
 694         struct mtd_oob_region oobregion;
 695         void *eccbuf;
 696         int ret, i;
 697
 698         nc = to_nand_controller(nand->controller);
 699
 700         if (raw)
 701                 return 0;
 702
 703         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 704         if (ret) {
 705                 dev_err(nc->dev,
 706                         "Failed to transfer NAND page data (err = %d)\n",
 707                         ret);
 708                 return ret;
 709         }
 710
 711         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 712         eccbuf = chip->oob_poi + oobregion.offset;
 713
 714         for (i = 0; i < chip->ecc.steps; i++) {
 715                 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
 716                                                    eccbuf);
 717                 eccbuf += chip->ecc.bytes;
 718         }
 719
 720         return 0;
 721 }
 722
 723 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
 724                                          bool raw)
 725 {
 726         struct atmel_nand *nand = to_atmel_nand(chip);
 727         struct mtd_info *mtd = nand_to_mtd(chip);
 728         struct atmel_nand_controller *nc;
 729         struct mtd_oob_region oobregion;
 730         int ret, i, max_bitflips = 0;
 731         void *databuf, *eccbuf;
 732
 733         nc = to_nand_controller(nand->controller);
 734
 735         if (raw)
 736                 return 0;
 737
 738         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 739         if (ret) {
 740                 dev_err(nc->dev,
 741                         "Failed to read NAND page data (err = %d)\n", ret);
 742                 return ret;
 743         }
 744
 745         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 746         eccbuf = chip->oob_poi + oobregion.offset;
 747         databuf = buf;
 748
 749         for (i = 0; i < chip->ecc.steps; i++) {
 750                 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
 751                                                  eccbuf);
 752                 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
 753                         ret = nand_check_erased_ecc_chunk(databuf,
 754                                                           chip->ecc.size,
 755                                                           eccbuf,
 756                                                           chip->ecc.bytes,
 757                                                           NULL, 0,
 758                                                           chip->ecc.strength);
 759
 760                 if (ret >= 0)
 761                         max_bitflips = max(ret, max_bitflips);
 762                 else
 763                         mtd->ecc_stats.failed++;
 764
 765                 databuf += chip->ecc.size;
 766                 eccbuf += chip->ecc.bytes;
 767         }
 768
 769         return max_bitflips;
 770 }
 771
 772 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
 773                                      bool oob_required, int page, bool raw)
 774 {
 775         struct mtd_info *mtd = nand_to_mtd(chip);
 776         struct atmel_nand *nand = to_atmel_nand(chip);
 777         int ret;
 778
 779         nand_prog_page_begin_op(chip, page, 0, NULL, 0);
 780
 781         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 782         if (ret)
 783                 return ret;
 784
 785         atmel_nand_write_buf(mtd, buf, mtd->writesize);
 786
 787         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 788         if (ret) {
 789                 atmel_pmecc_disable(nand->pmecc);
 790                 return ret;
 791         }
 792
 793         atmel_nand_pmecc_disable(chip, raw);
 794
 795         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 796
 797         return nand_prog_page_end_op(chip);
 798 }
 799
 800 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 801                                        struct nand_chip *chip, const u8 *buf,
 802                                        int oob_required, int page)
 803 {
 804         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
 805 }
 806
 807 static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
 808                                            struct nand_chip *chip,
 809                                            const u8 *buf, int oob_required,
 810                                            int page)
 811 {
 812         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
 813 }
 814
 815 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 816                                     bool oob_required, int page, bool raw)
 817 {
 818         struct mtd_info *mtd = nand_to_mtd(chip);
 819         int ret;
 820
 821         nand_read_page_op(chip, page, 0, NULL, 0);
 822
 823         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
 824         if (ret)
 825                 return ret;
 826
 827         atmel_nand_read_buf(mtd, buf, mtd->writesize);
 828         atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 829
 830         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 831
 832         atmel_nand_pmecc_disable(chip, raw);
 833
 834         return ret;
 835 }
 836
 837 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 838                                       struct nand_chip *chip, u8 *buf,
 839                                       int oob_required, int page)
 840 {
 841         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
 842 }
 843
 844 static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
 845                                           struct nand_chip *chip, u8 *buf,
 846                                           int oob_required, int page)
 847 {
 848         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
 849 }
 850
 851 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
 852                                           const u8 *buf, bool oob_required,
 853                                           int page, bool raw)
 854 {
 855         struct mtd_info *mtd = nand_to_mtd(chip);
 856         struct atmel_nand *nand = to_atmel_nand(chip);
 857         struct atmel_hsmc_nand_controller *nc;
 858         int ret, status;
 859
 860         nc = to_hsmc_nand_controller(nand->controller);
 861
 862         atmel_nfc_copy_to_sram(chip, buf, false);
 863
 864         nc->op.cmds[0] = NAND_CMD_SEQIN;
 865         nc->op.ncmds = 1;
 866         atmel_nfc_set_op_addr(chip, page, 0x0);
 867         nc->op.cs = nand->activecs->id;
 868         nc->op.data = ATMEL_NFC_WRITE_DATA;
 869
 870         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 871         if (ret)
 872                 return ret;
 873
 874         ret = atmel_nfc_exec_op(nc, true);
 875         if (ret) {
 876                 atmel_nand_pmecc_disable(chip, raw);
 877                 dev_err(nc->base.dev,
 878                         "Failed to transfer NAND page data (err = %d)\n",
 879                         ret);
 880                 return ret;
 881         }
 882
 883         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 884
 885         atmel_nand_pmecc_disable(chip, raw);
 886
 887         if (ret)
 888                 return ret;
 889
 890         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 891
 892         nc->op.cmds[0] = NAND_CMD_PAGEPROG;
 893         nc->op.ncmds = 1;
 894         nc->op.cs = nand->activecs->id;
 895         ret = atmel_nfc_exec_op(nc, true);
 896         if (ret)
 897                 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
 898                         ret);
 899
 900         status = chip->waitfunc(mtd, chip);
 901         if (status & NAND_STATUS_FAIL)
 902                 return -EIO;
 903
 904         return ret;
 905 }
 906
 907 static int
 908 atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 909                                  const u8 *buf, int oob_required,
 910                                  int page)
 911 {
 912         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 913                                               false);
 914 }
 915
 916 static int
 917 atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 918                                      const u8 *buf,
 919                                      int oob_required, int page)
 920 {
 921         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 922                                               true);
 923 }
 924
 925 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 926                                          bool oob_required, int page,
 927                                          bool raw)
 928 {
 929         struct mtd_info *mtd = nand_to_mtd(chip);
 930         struct atmel_nand *nand = to_atmel_nand(chip);
 931         struct atmel_hsmc_nand_controller *nc;
 932         int ret;
 933
 934         nc = to_hsmc_nand_controller(nand->controller);
 935
 936         /*
 937          * Optimized read page accessors only work when the NAND R/B pin is
 938          * connected to a native SoC R/B pin. If that's not the case, fallback
 939          * to the non-optimized one.
 940          */
 941         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
 942                 nand_read_page_op(chip, page, 0, NULL, 0);
 943
 944                 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
 945                                                 raw);
 946         }
 947
 948         nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
 949
 950         if (mtd->writesize > 512)
 951                 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
 952
 953         atmel_nfc_set_op_addr(chip, page, 0x0);
 954         nc->op.cs = nand->activecs->id;
 955         nc->op.data = ATMEL_NFC_READ_DATA;
 956
 957         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
 958         if (ret)
 959                 return ret;
 960
 961         ret = atmel_nfc_exec_op(nc, true);
 962         if (ret) {
 963                 atmel_nand_pmecc_disable(chip, raw);
 964                 dev_err(nc->base.dev,
 965                         "Failed to load NAND page data (err = %d)\n",
 966                         ret);
 967                 return ret;
 968         }
 969
 970         atmel_nfc_copy_from_sram(chip, buf, true);
 971
 972         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 973
 974         atmel_nand_pmecc_disable(chip, raw);
 975
 976         return ret;
 977 }
 978
 979 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
 980                                            struct nand_chip *chip, u8 *buf,
 981                                            int oob_required, int page)
 982 {
 983         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
 984                                              false);
 985 }
 986
 987 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
 988                                                struct nand_chip *chip,
 989                                                u8 *buf, int oob_required,
 990                                                int page)
 991 {
 992         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
 993                                              true);
 994 }
 995
 996 static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
 997                                  struct mtd_oob_region *oobregion)
 998 {
 999         struct nand_chip *chip = mtd_to_nand(mtd);
1000         struct nand_ecc_ctrl *ecc = &chip->ecc;
1001
1002         if (section || !ecc->total)
1003                 return -ERANGE;
1004
1005         oobregion->length = ecc->total;
1006         oobregion->offset = mtd->oobsize - oobregion->length;
1007
1008         return 0;
1009 }
1010
1011 static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
1012                                   struct mtd_oob_region *oobregion)
1013 {
1014         struct nand_chip *chip = mtd_to_nand(mtd);
1015         struct nand_ecc_ctrl *ecc = &chip->ecc;
1016
1017         if (section)
1018                 return -ERANGE;
1019
1020         oobregion->length = mtd->oobsize - ecc->total - 2;
1021         oobregion->offset = 2;
1022
1023         return 0;
1024 }
1025
1026 static const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
1027         .ecc = nand_ooblayout_ecc_lp,
1028         .rfree = nand_ooblayout_free_lp,
1029 };
1030
1031 const struct mtd_ooblayout_ops *nand_get_large_page_ooblayout(void)
1032 {
1033         return &nand_ooblayout_lp_ops;
1034 }
1035
1036 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1037 {
1038         struct mtd_info *mtd = nand_to_mtd(chip);
1039         struct atmel_nand *nand = to_atmel_nand(chip);
1040         struct atmel_nand_controller *nc;
1041         struct atmel_pmecc_user_req req;
1042
1043         nc = to_nand_controller(nand->controller);
1044
1045         if (!nc->pmecc) {
1046                 dev_err(nc->dev, "HW ECC not supported\n");
1047                 return -EOPNOTSUPP;
1048         }
1049
1050         if (nc->caps->legacy_of_bindings) {
1051                 u32 val;
1052
1053                 if (!ofnode_read_u32(nc->dev->node_, "atmel,pmecc-cap", &val))
1054                         chip->ecc.strength = val;
1055
1056                 if (!ofnode_read_u32(nc->dev->node_,
1057                                      "atmel,pmecc-sector-size",
1058                                      &val))
1059                         chip->ecc.size = val;
1060         }
1061
1062         if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1063                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1064         else if (chip->ecc.strength)
1065                 req.ecc.strength = chip->ecc.strength;
1066         else
1067                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1068
1069         if (chip->ecc.size)
1070                 req.ecc.sectorsize = chip->ecc.size;
1071         else
1072                 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1073
1074         req.pagesize = mtd->writesize;
1075         req.oobsize = mtd->oobsize;
1076
1077         if (mtd->writesize <= 512) {
1078                 req.ecc.bytes = 4;
1079                 req.ecc.ooboffset = 0;
1080         } else {
1081                 req.ecc.bytes = mtd->oobsize - 2;
1082                 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1083         }
1084
1085         nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1086         if (IS_ERR(nand->pmecc))
1087                 return PTR_ERR(nand->pmecc);
1088
1089         chip->ecc.algo = NAND_ECC_BCH;
1090         chip->ecc.size = req.ecc.sectorsize;
1091         chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1092         chip->ecc.strength = req.ecc.strength;
1093
1094         chip->options |= NAND_NO_SUBPAGE_WRITE;
1095
1096         mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
1097         pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1098                                 mtd->oobsize,
1099                                 chip->ecc.bytes);
1100         chip->ecc.layout = &atmel_pmecc_oobinfo;
1101
1102         return 0;
1103 }
1104
1105 static int atmel_nand_ecc_init(struct nand_chip *chip)
1106 {
1107         struct atmel_nand_controller *nc;
1108         struct atmel_nand *nand = to_atmel_nand(chip);
1109         int ret;
1110
1111         nc = to_nand_controller(nand->controller);
1112
1113         switch (chip->ecc.mode) {
1114         case NAND_ECC_NONE:
1115         case NAND_ECC_SOFT:
1116                 /*
1117                  * Nothing to do, the core will initialize everything for us.
1118                  */
1119                 break;
1120
1121         case NAND_ECC_HW:
1122                 ret = atmel_nand_pmecc_init(chip);
1123                 if (ret)
1124                         return ret;
1125
1126                 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1127                 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1128                 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1129                 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1130                 break;
1131
1132         default:
1133                 /* Other modes are not supported. */
1134                 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1135                         chip->ecc.mode);
1136                 return -EOPNOTSUPP;
1137         }
1138
1139         return 0;
1140 }
1141
1142 static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
1143 {
1144         int ret;
1145
1146         ret = atmel_nand_ecc_init(chip);
1147         if (ret)
1148                 return ret;
1149
1150         if (chip->ecc.mode != NAND_ECC_HW)
1151                 return 0;
1152
1153         /* Adjust the ECC operations for the HSMC IP. */
1154         chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1155         chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1156         chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1157         chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1158
1159         return 0;
1160 }
1161
1162 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1163                                           const struct nand_data_interface *conf,
1164                                           struct atmel_smc_cs_conf *smcconf)
1165 {
1166         u32 ncycles, totalcycles, timeps, mckperiodps;
1167         struct atmel_nand_controller *nc;
1168         int ret;
1169
1170         nc = to_nand_controller(nand->controller);
1171
1172         /* DDR interface not supported. */
1173         if (conf->type != NAND_SDR_IFACE)
1174                 return -EOPNOTSUPP;
1175
1176         /*
1177          * tRC < 30ns implies EDO mode. This controller does not support this
1178          * mode.
1179          */
1180         if (conf->timings.sdr.tRC_min < 30000)
1181                 return -EOPNOTSUPP;
1182
1183         atmel_smc_cs_conf_init(smcconf);
1184
1185         mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1186         mckperiodps *= 1000;
1187
1188         /*
1189          * Set write pulse timing. This one is easy to extract:
1190          *
1191          * NWE_PULSE = tWP
1192          */
1193         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1194         totalcycles = ncycles;
1195         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1196                                           ncycles);
1197         if (ret)
1198                 return ret;
1199
1200         /*
1201          * The write setup timing depends on the operation done on the NAND.
1202          * All operations goes through the same data bus, but the operation
1203          * type depends on the address we are writing to (ALE/CLE address
1204          * lines).
1205          * Since we have no way to differentiate the different operations at
1206          * the SMC level, we must consider the worst case (the biggest setup
1207          * time among all operation types):
1208          *
1209          * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1210          */
1211         timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1212                       conf->timings.sdr.tALS_min);
1213         timeps = max(timeps, conf->timings.sdr.tDS_min);
1214         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1215         ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1216         totalcycles += ncycles;
1217         ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1218                                           ncycles);
1219         if (ret)
1220                 return ret;
1221
1222         /*
1223          * As for the write setup timing, the write hold timing depends on the
1224          * operation done on the NAND:
1225          *
1226          * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1227          */
1228         timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1229                       conf->timings.sdr.tALH_min);
1230         timeps = max3(timeps, conf->timings.sdr.tDH_min,
1231                       conf->timings.sdr.tWH_min);
1232         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1233         totalcycles += ncycles;
1234
1235         /*
1236          * The write cycle timing is directly matching tWC, but is also
1237          * dependent on the other timings on the setup and hold timings we
1238          * calculated earlier, which gives:
1239          *
1240          * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1241          */
1242         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1243         ncycles = max(totalcycles, ncycles);
1244         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1245                                           ncycles);
1246         if (ret)
1247                 return ret;
1248
1249         /*
1250          * We don't want the CS line to be toggled between each byte/word
1251          * transfer to the NAND. The only way to guarantee that is to have the
1252          * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1253          *
1254          * NCS_WR_PULSE = NWE_CYCLE
1255          */
1256         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1257                                           ncycles);
1258         if (ret)
1259                 return ret;
1260
1261         /*
1262          * As for the write setup timing, the read hold timing depends on the
1263          * operation done on the NAND:
1264          *
1265          * NRD_HOLD = max(tREH, tRHOH)
1266          */
1267         timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1268         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1269         totalcycles = ncycles;
1270
1271         /*
1272          * TDF = tRHZ - NRD_HOLD
1273          */
1274         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1275         ncycles -= totalcycles;
1276
1277         /*
1278          * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1279          * we might end up with a config that does not fit in the TDF field.
1280          * Just take the max value in this case and hope that the NAND is more
1281          * tolerant than advertised.
1282          */
1283         if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1284                 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1285         else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1286                 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1287
1288         smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1289                          ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1290
1291         /*
1292          * Read pulse timing directly matches tRP:
1293          *
1294          * NRD_PULSE = tRP
1295          */
1296         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1297         totalcycles += ncycles;
1298         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1299                                           ncycles);
1300         if (ret)
1301                 return ret;
1302
1303         /*
1304          * The write cycle timing is directly matching tWC, but is also
1305          * dependent on the setup and hold timings we calculated earlier,
1306          * which gives:
1307          *
1308          * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1309          *
1310          * NRD_SETUP is always 0.
1311          */
1312         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1313         ncycles = max(totalcycles, ncycles);
1314         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1315                                           ncycles);
1316         if (ret)
1317                 return ret;
1318
1319         /*
1320          * We don't want the CS line to be toggled between each byte/word
1321          * transfer from the NAND. The only way to guarantee that is to have
1322          * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1323          *
1324          * NCS_RD_PULSE = NRD_CYCLE
1325          */
1326         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1327                                           ncycles);
1328         if (ret)
1329                 return ret;
1330
1331         /* Txxx timings are directly matching tXXX ones. */
1332         ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1333         ret = atmel_smc_cs_conf_set_timing(smcconf,
1334                                            ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1335                                            ncycles);
1336         if (ret)
1337                 return ret;
1338
1339         ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1340         ret = atmel_smc_cs_conf_set_timing(smcconf,
1341                                            ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1342                                            ncycles);
1343         /*
1344          * Version 4 of the ONFI spec mandates that tADL be at least 400
1345          * nanoseconds, but, depending on the master clock rate, 400 ns may not
1346          * fit in the tADL field of the SMC reg. We need to relax the check and
1347          * accept the -ERANGE return code.
1348          *
1349          * Note that previous versions of the ONFI spec had a lower tADL_min
1350          * (100 or 200 ns). It's not clear why this timing constraint got
1351          * increased but it seems most NANDs are fine with values lower than
1352          * 400ns, so we should be safe.
1353          */
1354         if (ret && ret != -ERANGE)
1355                 return ret;
1356
1357         ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1358         ret = atmel_smc_cs_conf_set_timing(smcconf,
1359                                            ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1360                                            ncycles);
1361         if (ret)
1362                 return ret;
1363
1364         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1365         ret = atmel_smc_cs_conf_set_timing(smcconf,
1366                                            ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1367                                            ncycles);
1368         if (ret)
1369                 return ret;
1370
1371         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1372         ret = atmel_smc_cs_conf_set_timing(smcconf,
1373                                            ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1374                                            ncycles);
1375         if (ret)
1376                 return ret;
1377
1378         /* Attach the CS line to the NFC logic. */
1379         smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1380
1381         /* Set the appropriate data bus width. */
1382         if (nand->base.options & NAND_BUSWIDTH_16)
1383                 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1384
1385         /* Operate in NRD/NWE READ/WRITEMODE. */
1386         smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1387                          ATMEL_SMC_MODE_WRITEMODE_NWE;
1388
1389         return 0;
1390 }
1391
1392 static int
1393 atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1394                                     int csline,
1395                                     const struct nand_data_interface *conf)
1396 {
1397         struct atmel_nand_controller *nc;
1398         struct atmel_smc_cs_conf smcconf;
1399         struct atmel_nand_cs *cs;
1400         int ret;
1401
1402         nc = to_nand_controller(nand->controller);
1403
1404         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1405         if (ret)
1406                 return ret;
1407
1408         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1409                 return 0;
1410
1411         cs = &nand->cs[csline];
1412         cs->smcconf = smcconf;
1413
1414         atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1415
1416         return 0;
1417 }
1418
1419 static int
1420 atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1421                                      int csline,
1422                                      const struct nand_data_interface *conf)
1423 {
1424         struct atmel_hsmc_nand_controller *nc;
1425         struct atmel_smc_cs_conf smcconf;
1426         struct atmel_nand_cs *cs;
1427         int ret;
1428
1429         nc = to_hsmc_nand_controller(nand->controller);
1430
1431         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1432         if (ret)
1433                 return ret;
1434
1435         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1436                 return 0;
1437
1438         cs = &nand->cs[csline];
1439         cs->smcconf = smcconf;
1440
1441         if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1442                 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1443
1444         atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1445                                  &cs->smcconf);
1446
1447         return 0;
1448 }
1449
1450 static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
1451                                            const struct nand_data_interface *conf)
1452 {
1453         struct nand_chip *chip = mtd_to_nand(mtd);
1454         struct atmel_nand *nand = to_atmel_nand(chip);
1455         struct atmel_nand_controller *nc;
1456
1457         nc = to_nand_controller(nand->controller);
1458
1459         if (csline >= nand->numcs ||
1460             (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1461                 return -EINVAL;
1462
1463         return nc->caps->ops->setup_data_interface(nand, csline, conf);
1464 }
1465
1466 #define NAND_KEEP_TIMINGS       0x00800000
1467
1468 static void atmel_nand_init(struct atmel_nand_controller *nc,
1469                             struct atmel_nand *nand)
1470 {
1471         struct nand_chip *chip = &nand->base;
1472         struct mtd_info *mtd = nand_to_mtd(chip);
1473
1474         mtd->dev->parent = nc->dev;
1475         nand->controller = &nc->base;
1476
1477         chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1478         chip->read_byte = atmel_nand_read_byte;
1479         chip->write_byte = atmel_nand_write_byte;
1480         chip->read_buf = atmel_nand_read_buf;
1481         chip->write_buf = atmel_nand_write_buf;
1482         chip->select_chip = atmel_nand_select_chip;
1483         chip->setup_data_interface = atmel_nand_setup_data_interface;
1484
1485         if (!nc->mck || !nc->caps->ops->setup_data_interface)
1486                 chip->options |= NAND_KEEP_TIMINGS;
1487
1488         /* Some NANDs require a longer delay than the default one (20us). */
1489         chip->chip_delay = 40;
1490
1491         /* Default to HW ECC if pmecc is available. */
1492         if (nc->pmecc)
1493                 chip->ecc.mode = NAND_ECC_HW;
1494 }
1495
1496 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1497                                 struct atmel_nand *nand)
1498 {
1499         struct atmel_smc_nand_controller *smc_nc;
1500         int i;
1501
1502         atmel_nand_init(nc, nand);
1503
1504         smc_nc = to_smc_nand_controller(nand->controller);
1505         if (!smc_nc->ebi_csa_regmap)
1506                 return;
1507
1508         /* Attach the CS to the NAND Flash logic. */
1509         for (i = 0; i < nand->numcs; i++)
1510                 regmap_update_bits(smc_nc->ebi_csa_regmap,
1511                                    smc_nc->ebi_csa->offs,
1512                                    BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1513
1514         if (smc_nc->ebi_csa->nfd0_on_d16)
1515                 regmap_update_bits(smc_nc->ebi_csa_regmap,
1516                                    smc_nc->ebi_csa->offs,
1517                                    smc_nc->ebi_csa->nfd0_on_d16,
1518                                    smc_nc->ebi_csa->nfd0_on_d16);
1519 }
1520
1521 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1522                                  struct atmel_nand *nand)
1523 {
1524         struct nand_chip *chip = &nand->base;
1525
1526         atmel_nand_init(nc, nand);
1527
1528         /* Overload some methods for the HSMC controller. */
1529         chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1530         chip->select_chip = atmel_hsmc_nand_select_chip;
1531 }
1532
1533 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
1534 {
1535         list_del(&nand->node);
1536
1537         return 0;
1538 }
1539
1540 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1541                                             ofnode np,
1542                                             int reg_cells)
1543 {
1544         struct atmel_nand *nand;
1545         ofnode n;
1546         int numcs = 0;
1547         int ret, i;
1548         u32 val;
1549         fdt32_t faddr;
1550         phys_addr_t base;
1551
1552         /* Count num of nand nodes */
1553         ofnode_for_each_subnode(n, ofnode_get_parent(np))
1554                 numcs++;
1555         if (numcs < 1) {
1556                 dev_err(nc->dev, "Missing or invalid reg property\n");
1557                 return ERR_PTR(-EINVAL);
1558         }
1559
1560         nand = devm_kzalloc(nc->dev,
1561                             sizeof(struct atmel_nand) +
1562                             (numcs * sizeof(struct atmel_nand_cs)),
1563                             GFP_KERNEL);
1564         if (!nand) {
1565                 dev_err(nc->dev, "Failed to allocate NAND object\n");
1566                 return ERR_PTR(-ENOMEM);
1567         }
1568
1569         nand->numcs = numcs;
1570
1571         gpio_request_by_name_nodev(np, "det-gpios", 0, &nand->cdgpio,
1572                                    GPIOD_IS_IN);
1573
1574         for (i = 0; i < numcs; i++) {
1575                 ret = ofnode_read_u32(np, "reg", &val);
1576                 if (ret) {
1577                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1578                                 ret);
1579                         return ERR_PTR(ret);
1580                 }
1581                 nand->cs[i].id = val;
1582
1583                 /* Read base address */
1584                 struct resource res;
1585
1586                 if (ofnode_read_resource(np, 0, &res)) {
1587                         dev_err(nc->dev, "Unable to read resource\n");
1588                         return ERR_PTR(-ENOMEM);
1589                 }
1590
1591                 faddr = cpu_to_fdt32(val);
1592                 base = ofnode_translate_address(np, &faddr);
1593                 nand->cs[i].io.virt = (void *)base;
1594
1595                 if (!ofnode_read_u32(np, "atmel,rb", &val)) {
1596                         if (val > ATMEL_NFC_MAX_RB_ID)
1597                                 return ERR_PTR(-EINVAL);
1598
1599                         nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1600                         nand->cs[i].rb.id = val;
1601                 } else {
1602                         ret = gpio_request_by_name_nodev(np, "rb-gpios", 0,
1603                                                          &nand->cs[i].rb.gpio,
1604                                                          GPIOD_IS_IN);
1605                         if (ret && ret != -ENOENT)
1606                                 dev_err(nc->dev, "Failed to get R/B gpio (err = %d)\n", ret);
1607                         if (!ret)
1608                                 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1609                 }
1610
1611                 gpio_request_by_name_nodev(np, "cs-gpios", 0,
1612                                            &nand->cs[i].csgpio,
1613                                            GPIOD_IS_OUT);
1614         }
1615
1616         nand_set_flash_node(&nand->base, np);
1617
1618         return nand;
1619 }
1620
1621 static int nand_attach(struct nand_chip *chip)
1622 {
1623         struct atmel_nand *nand = to_atmel_nand(chip);
1624
1625         if (nand->controller->ops && nand->controller->ops->attach_chip)
1626                 return nand->controller->ops->attach_chip(chip);
1627
1628         return 0;
1629 }
1630
1631 int atmel_nand_scan(struct mtd_info *mtd, int maxchips)
1632 {
1633         int ret;
1634
1635         ret = nand_scan_ident(mtd, maxchips, NULL);
1636         if (ret)
1637                 return ret;
1638
1639         ret = nand_attach(mtd_to_nand(mtd));
1640         if (ret)
1641                 return ret;
1642
1643         ret = nand_scan_tail(mtd);
1644         return ret;
1645 }
1646
1647 static int
1648 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1649                                struct atmel_nand *nand)
1650 {
1651         struct nand_chip *chip = &nand->base;
1652         struct mtd_info *mtd = nand_to_mtd(chip);
1653         int ret;
1654
1655         /* No card inserted, skip this NAND. */
1656         if (dm_gpio_is_valid(&nand->cdgpio) &&
1657             dm_gpio_get_value(&nand->cdgpio)) {
1658                 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1659                 return 0;
1660         }
1661
1662         nc->caps->ops->nand_init(nc, nand);
1663
1664         ret = atmel_nand_scan(mtd, nand->numcs);
1665         if (ret) {
1666                 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1667                 return ret;
1668         }
1669
1670         ret = nand_register(0, mtd);
1671         if (ret) {
1672                 dev_err(nc->dev, "nand register failed: %d\n", ret);
1673                 return ret;
1674         }
1675
1676         list_add_tail(&nand->node, &nc->chips);
1677
1678         return 0;
1679 }
1680
1681 static int
1682 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1683 {
1684         struct atmel_nand *nand, *tmp;
1685         int ret;
1686
1687         list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1688                 ret = atmel_nand_controller_remove_nand(nand);
1689                 if (ret)
1690                         return ret;
1691         }
1692
1693         return 0;
1694 }
1695
1696 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1697 {
1698         ofnode np;
1699         ofnode nand_np;
1700         int ret, reg_cells;
1701         u32 val;
1702
1703         /* TODO:
1704          * Add support for legacy nands
1705          */
1706
1707         np = nc->dev->node_;
1708
1709         ret = ofnode_read_u32(np, "#address-cells", &val);
1710         if (ret) {
1711                 dev_err(nc->dev, "missing #address-cells property\n");
1712                 return ret;
1713         }
1714
1715         reg_cells = val;
1716
1717         ret = ofnode_read_u32(np, "#size-cells", &val);
1718         if (ret) {
1719                 dev_err(nc->dev, "missing #size-cells property\n");
1720                 return ret;
1721         }
1722
1723         reg_cells += val;
1724
1725         ofnode_for_each_subnode(nand_np, np) {
1726                 struct atmel_nand *nand;
1727
1728                 nand = atmel_nand_create(nc, nand_np, reg_cells);
1729                 if (IS_ERR(nand)) {
1730                         ret = PTR_ERR(nand);
1731                         goto err;
1732                 }
1733
1734                 ret = atmel_nand_controller_add_nand(nc, nand);
1735                 if (ret)
1736                         goto err;
1737         }
1738
1739         return 0;
1740
1741 err:
1742         atmel_nand_controller_remove_nands(nc);
1743
1744         return ret;
1745 }
1746
1747 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = {
1748         .offs = AT91SAM9260_MATRIX_EBICSA,
1749 };
1750
1751 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = {
1752         .offs = AT91SAM9261_MATRIX_EBICSA,
1753 };
1754
1755 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = {
1756         .offs = AT91SAM9263_MATRIX_EBI0CSA,
1757 };
1758
1759 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = {
1760         .offs = AT91SAM9RL_MATRIX_EBICSA,
1761 };
1762
1763 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = {
1764         .offs = AT91SAM9G45_MATRIX_EBICSA,
1765 };
1766
1767 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = {
1768         .offs = AT91SAM9N12_MATRIX_EBICSA,
1769 };
1770
1771 static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = {
1772         .offs = AT91SAM9X5_MATRIX_EBICSA,
1773 };
1774
1775 static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = {
1776         .offs = AT91_SFR_CCFG_EBICSA,
1777         .nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,
1778 };
1779
1780 static const struct udevice_id atmel_ebi_csa_regmap_of_ids[] = {
1781         {
1782                 .compatible = "atmel,at91sam9260-matrix",
1783                 .data = (ulong)&at91sam9260_ebi_csa,
1784         },
1785         {
1786                 .compatible = "atmel,at91sam9261-matrix",
1787                 .data = (ulong)&at91sam9261_ebi_csa,
1788         },
1789         {
1790                 .compatible = "atmel,at91sam9263-matrix",
1791                 .data = (ulong)&at91sam9263_ebi_csa,
1792         },
1793         {
1794                 .compatible = "atmel,at91sam9rl-matrix",
1795                 .data = (ulong)&at91sam9rl_ebi_csa,
1796         },
1797         {
1798                 .compatible = "atmel,at91sam9g45-matrix",
1799                 .data = (ulong)&at91sam9g45_ebi_csa,
1800         },
1801         {
1802                 .compatible = "atmel,at91sam9n12-matrix",
1803                 .data = (ulong)&at91sam9n12_ebi_csa,
1804         },
1805         {
1806                 .compatible = "atmel,at91sam9x5-matrix",
1807                 .data = (ulong)&at91sam9x5_ebi_csa,
1808         },
1809         {
1810                 .compatible = "microchip,sam9x60-sfr",
1811                 .data = (ulong)&sam9x60_ebi_csa,
1812         },
1813         { /* sentinel */ },
1814 };
1815
1816 static int atmel_nand_attach_chip(struct nand_chip *chip)
1817 {
1818         struct atmel_nand *nand = to_atmel_nand(chip);
1819         struct atmel_nand_controller *nc = to_nand_controller(nand->controller);
1820         struct mtd_info *mtd = nand_to_mtd(chip);
1821         int ret;
1822
1823         ret = nc->caps->ops->ecc_init(chip);
1824         if (ret)
1825                 return ret;
1826
1827         if (nc->caps->legacy_of_bindings || !ofnode_valid(nc->dev->node_)) {
1828                 /*
1829                  * We keep the MTD name unchanged to avoid breaking platforms
1830                  * where the MTD cmdline parser is used and the bootloader
1831                  * has not been updated to use the new naming scheme.
1832                  */
1833                 mtd->name = "atmel_nand";
1834         } else if (!mtd->name) {
1835                 /*
1836                  * If the new bindings are used and the bootloader has not been
1837                  * updated to pass a new mtdparts parameter on the cmdline, you
1838                  * should define the following property in your nand node:
1839                  *
1840                  *      label = "atmel_nand";
1841                  *
1842                  * This way, mtd->name will be set by the core when
1843                  * nand_set_flash_node() is called.
1844                  */
1845                 sprintf(mtd->name, "%s:nand.%d", nc->dev->name, nand->cs[0].id);
1846         }
1847
1848         return 0;
1849 }
1850
1851 static const struct nand_controller_ops atmel_nand_controller_ops = {
1852         .attach_chip = atmel_nand_attach_chip,
1853 };
1854
1855 static int
1856 atmel_nand_controller_init(struct atmel_nand_controller *nc,
1857                            struct udevice *dev,
1858                            const struct atmel_nand_controller_caps *caps)
1859 {
1860         struct ofnode_phandle_args args;
1861         int ret;
1862
1863         nc->base.ops = &atmel_nand_controller_ops;
1864         INIT_LIST_HEAD(&nc->chips);
1865         nc->dev = dev;
1866         nc->caps = caps;
1867
1868         nc->pmecc = devm_atmel_pmecc_get(dev);
1869         if (IS_ERR(nc->pmecc)) {
1870                 ret = PTR_ERR(nc->pmecc);
1871                 if (ret != -EPROBE_DEFER)
1872                         dev_err(dev, "Could not get PMECC object (err = %d)\n",
1873                                 ret);
1874                 return ret;
1875         }
1876
1877         /* We do not retrieve the SMC syscon when parsing old DTs. */
1878         if (nc->caps->legacy_of_bindings)
1879                 return 0;
1880
1881         nc->mck = devm_kzalloc(dev, sizeof(nc->mck), GFP_KERNEL);
1882         if (!nc->mck)
1883                 return -ENOMEM;
1884
1885         clk_get_by_index(dev->parent, 0, nc->mck);
1886         if (IS_ERR(nc->mck)) {
1887                 dev_err(dev, "Failed to retrieve MCK clk\n");
1888                 return PTR_ERR(nc->mck);
1889         }
1890
1891         ret = ofnode_parse_phandle_with_args(dev->parent->node_,
1892                                              "atmel,smc", NULL, 0, 0, &args);
1893         if (ret) {
1894                 dev_err(dev, "Missing or invalid atmel,smc property\n");
1895                 return -EINVAL;
1896         }
1897
1898         nc->smc = syscon_node_to_regmap(args.node);
1899         if (IS_ERR(nc->smc)) {
1900                 ret = PTR_ERR(nc->smc);
1901                 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
1902                 return 0;
1903         }
1904
1905         return 0;
1906 }
1907
1908 static int
1909 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
1910 {
1911         struct udevice *dev = nc->base.dev;
1912         struct ofnode_phandle_args args;
1913         const struct udevice_id *match = NULL;
1914         const char *name;
1915         int ret;
1916         int len;
1917         int i;
1918
1919         /* We do not retrieve the EBICSA regmap when parsing old DTs. */
1920         if (nc->base.caps->legacy_of_bindings)
1921                 return 0;
1922
1923         ret = ofnode_parse_phandle_with_args(dev->parent->node_,
1924                                              nc->base.caps->ebi_csa_regmap_name,
1925                                              NULL, 0, 0, &args);
1926         if (ret) {
1927                 dev_err(dev, "Unable to read ebi csa regmap\n");
1928                 return -EINVAL;
1929         }
1930
1931         name = ofnode_get_property(args.node, "compatible", &len);
1932
1933         for (i = 0; i < ARRAY_SIZE(atmel_ebi_csa_regmap_of_ids); i++) {
1934                 if (!strcmp(name, atmel_ebi_csa_regmap_of_ids[i].compatible)) {
1935                         match = &atmel_ebi_csa_regmap_of_ids[i];
1936                         break;
1937                 }
1938         }
1939
1940         if (!match) {
1941                 dev_err(dev, "Unable to find ebi csa conf");
1942                 return -EINVAL;
1943         }
1944         nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
1945
1946         nc->ebi_csa_regmap = syscon_node_to_regmap(args.node);
1947         if (IS_ERR(nc->ebi_csa_regmap)) {
1948                 ret = PTR_ERR(nc->ebi_csa_regmap);
1949                 dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret);
1950                 return ret;
1951         }
1952
1953         /* TODO:
1954          * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
1955          * add 4 to ->ebi_csa->offs.
1956          */
1957
1958         return 0;
1959 }
1960
1961 static int atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
1962 {
1963         struct udevice *dev = nc->base.dev;
1964         struct ofnode_phandle_args args;
1965         struct clk smc_clk;
1966         int ret;
1967         u32 addr;
1968
1969         ret = ofnode_parse_phandle_with_args(dev->parent->node_,
1970                                              "atmel,smc", NULL, 0, 0, &args);
1971         if (ret) {
1972                 dev_err(dev, "Missing or invalid atmel,smc property\n");
1973                 return -EINVAL;
1974         }
1975
1976         nc->hsmc_layout = atmel_hsmc_get_reg_layout(args.node);
1977         if (IS_ERR(nc->hsmc_layout)) {
1978                 dev_err(dev, "Could not get hsmc layout\n");
1979                 return -EINVAL;
1980         }
1981
1982         /* Enable smc clock */
1983         ret = clk_get_by_index_nodev(args.node, 0, &smc_clk);
1984         if (ret) {
1985                 dev_err(dev, "Unable to get smc clock (err = %d)", ret);
1986                 return ret;
1987         }
1988
1989         ret = clk_prepare_enable(&smc_clk);
1990         if (ret)
1991                 return ret;
1992
1993         ret = ofnode_parse_phandle_with_args(dev->node_,
1994                                              "atmel,nfc-io", NULL, 0, 0, &args);
1995         if (ret) {
1996                 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
1997                 return -EINVAL;
1998         }
1999
2000         nc->io = syscon_node_to_regmap(args.node);
2001         if (IS_ERR(nc->io)) {
2002                 ret = PTR_ERR(nc->io);
2003                 dev_err(dev, "Could not get NFC IO regmap\n");
2004                 return ret;
2005         }
2006
2007         ret = ofnode_parse_phandle_with_args(dev->node_,
2008                                              "atmel,nfc-sram", NULL, 0, 0, &args);
2009         if (ret) {
2010                 dev_err(dev, "Missing or invalid atmel,nfc-sram property\n");
2011                 return ret;
2012         }
2013
2014         ret = ofnode_read_u32(args.node, "reg", &addr);
2015         if (ret) {
2016                 dev_err(dev, "Could not read reg addr of nfc sram");
2017                 return ret;
2018         }
2019         nc->sram.virt = (void *)addr;
2020
2021         return 0;
2022 }
2023
2024 static int
2025 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2026 {
2027         struct atmel_hsmc_nand_controller *hsmc_nc;
2028         int ret;
2029
2030         ret = atmel_nand_controller_remove_nands(nc);
2031         if (ret)
2032                 return ret;
2033
2034         hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2035
2036         if (hsmc_nc->clk) {
2037                 clk_disable_unprepare(hsmc_nc->clk);
2038                 devm_clk_put(nc->dev, hsmc_nc->clk);
2039         }
2040
2041         return 0;
2042 }
2043
2044 static int
2045 atmel_hsmc_nand_controller_probe(struct udevice *dev,
2046                                  const struct atmel_nand_controller_caps *caps)
2047 {
2048         struct atmel_hsmc_nand_controller *nc;
2049         int ret;
2050
2051         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2052         if (!nc)
2053                 return -ENOMEM;
2054
2055         ret = atmel_nand_controller_init(&nc->base, dev, caps);
2056         if (ret)
2057                 return ret;
2058
2059         ret = atmel_hsmc_nand_controller_init(nc);
2060         if (ret)
2061                 return ret;
2062
2063         /* Make sure all irqs are masked before registering our IRQ handler. */
2064         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2065
2066         /* Initial NFC configuration. */
2067         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2068                      ATMEL_HSMC_NFC_CFG_DTO_MAX);
2069
2070         ret = atmel_nand_controller_add_nands(&nc->base);
2071         if (ret)
2072                 goto err;
2073
2074         return 0;
2075
2076 err:
2077         atmel_hsmc_nand_controller_remove(&nc->base);
2078
2079         return ret;
2080 }
2081
2082 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2083         .probe = atmel_hsmc_nand_controller_probe,
2084         .remove = atmel_hsmc_nand_controller_remove,
2085         .ecc_init = atmel_hsmc_nand_ecc_init,
2086         .nand_init = atmel_hsmc_nand_init,
2087         .setup_data_interface = atmel_hsmc_nand_setup_data_interface,
2088 };
2089
2090 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2091         .has_dma = true,
2092         .ale_offs = BIT(21),
2093         .cle_offs = BIT(22),
2094         .ops = &atmel_hsmc_nc_ops,
2095 };
2096
2097 static int
2098 atmel_smc_nand_controller_probe(struct udevice *dev,
2099                                 const struct atmel_nand_controller_caps *caps)
2100 {
2101         struct atmel_smc_nand_controller *nc;
2102         int ret;
2103
2104         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2105         if (!nc)
2106                 return -ENOMEM;
2107
2108         ret = atmel_nand_controller_init(&nc->base, dev, caps);
2109         if (ret)
2110                 return ret;
2111
2112         ret = atmel_smc_nand_controller_init(nc);
2113         if (ret)
2114                 return ret;
2115
2116         return atmel_nand_controller_add_nands(&nc->base);
2117 }
2118
2119 static int
2120 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2121 {
2122         int ret;
2123
2124         ret = atmel_nand_controller_remove_nands(nc);
2125         if (ret)
2126                 return ret;
2127
2128         return 0;
2129 }
2130
2131 /*
2132  * The SMC reg layout of at91rm9200 is completely different which prevents us
2133  * from re-using atmel_smc_nand_setup_data_interface() for the
2134  * ->setup_data_interface() hook.
2135  * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2136  * ->setup_data_interface() unassigned.
2137  */
2138 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2139         .probe = atmel_smc_nand_controller_probe,
2140         .remove = atmel_smc_nand_controller_remove,
2141         .ecc_init = atmel_nand_ecc_init,
2142         .nand_init = atmel_smc_nand_init,
2143 };
2144
2145 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2146         .ale_offs = BIT(21),
2147         .cle_offs = BIT(22),
2148         .ebi_csa_regmap_name = "atmel,matrix",
2149         .ops = &at91rm9200_nc_ops,
2150 };
2151
2152 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2153         .probe = atmel_smc_nand_controller_probe,
2154         .remove = atmel_smc_nand_controller_remove,
2155         .ecc_init = atmel_nand_ecc_init,
2156         .nand_init = atmel_smc_nand_init,
2157         .setup_data_interface = atmel_smc_nand_setup_data_interface,
2158 };
2159
2160 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2161         .ale_offs = BIT(21),
2162         .cle_offs = BIT(22),
2163         .ebi_csa_regmap_name = "atmel,matrix",
2164         .ops = &atmel_smc_nc_ops,
2165 };
2166
2167 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2168         .ale_offs = BIT(22),
2169         .cle_offs = BIT(21),
2170         .ebi_csa_regmap_name = "atmel,matrix",
2171         .ops = &atmel_smc_nc_ops,
2172 };
2173
2174 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2175         .has_dma = true,
2176         .ale_offs = BIT(21),
2177         .cle_offs = BIT(22),
2178         .ebi_csa_regmap_name = "atmel,matrix",
2179         .ops = &atmel_smc_nc_ops,
2180 };
2181
2182 static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = {
2183         .has_dma = true,
2184         .ale_offs = BIT(21),
2185         .cle_offs = BIT(22),
2186         .ebi_csa_regmap_name = "microchip,sfr",
2187         .ops = &atmel_smc_nc_ops,
2188 };
2189
2190 /* Only used to parse old bindings. */
2191 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2192         .ale_offs = BIT(21),
2193         .cle_offs = BIT(22),
2194         .ops = &atmel_smc_nc_ops,
2195         .legacy_of_bindings = true,
2196 };
2197
2198 static const struct udevice_id atmel_nand_controller_of_ids[] = {
2199         {
2200                 .compatible = "atmel,at91rm9200-nand-controller",
2201                 .data = (ulong)&atmel_rm9200_nc_caps,
2202         },
2203         {
2204                 .compatible = "atmel,at91sam9260-nand-controller",
2205                 .data = (ulong)&atmel_sam9260_nc_caps,
2206         },
2207         {
2208                 .compatible = "atmel,at91sam9261-nand-controller",
2209                 .data = (ulong)&atmel_sam9261_nc_caps,
2210         },
2211         {
2212                 .compatible = "atmel,at91sam9g45-nand-controller",
2213                 .data = (ulong)&atmel_sam9g45_nc_caps,
2214         },
2215         {
2216                 .compatible = "atmel,sama5d3-nand-controller",
2217                 .data = (ulong)&atmel_sama5_nc_caps,
2218         },
2219         {
2220                 .compatible = "microchip,sam9x60-nand-controller",
2221                 .data = (ulong)&microchip_sam9x60_nc_caps,
2222         },
2223         /* Support for old/deprecated bindings: */
2224         {
2225                 .compatible = "atmel,at91rm9200-nand",
2226                 .data = (ulong)&atmel_rm9200_nand_caps,
2227         },
2228         {
2229                 .compatible = "atmel,sama5d4-nand",
2230                 .data = (ulong)&atmel_rm9200_nand_caps,
2231         },
2232         {
2233                 .compatible = "atmel,sama5d2-nand",
2234                 .data = (ulong)&atmel_rm9200_nand_caps,
2235         },
2236         { /* sentinel */ },
2237 };
2238
2239 static int atmel_nand_controller_probe(struct udevice *dev)
2240 {
2241         const struct atmel_nand_controller_caps *caps;
2242         struct udevice *pmecc_dev;
2243
2244         caps = (struct atmel_nand_controller_caps *)dev_get_driver_data(dev);
2245         if (!caps) {
2246                 printf("Could not retrieve NFC caps\n");
2247                 return -EINVAL;
2248         }
2249
2250         /* Probe pmecc driver */
2251         if (uclass_get_device(UCLASS_MTD, 1, &pmecc_dev)) {
2252                 printf("%s: get device fail\n", __func__);
2253                 return -EINVAL;
2254         }
2255
2256         return caps->ops->probe(dev, caps);
2257 }
2258
2259 static int atmel_nand_controller_remove(struct udevice *dev)
2260 {
2261         struct atmel_nand_controller *nc;
2262
2263         nc = (struct atmel_nand_controller *)dev_get_driver_data(dev);
2264
2265         return nc->caps->ops->remove(nc);
2266 }
2267
2268 U_BOOT_DRIVER(atmel_nand_controller) = {
2269         .name = "atmel-nand-controller",
2270         .id = UCLASS_MTD,
2271         .of_match = atmel_nand_controller_of_ids,
2272         .probe = atmel_nand_controller_probe,
2273         .remove = atmel_nand_controller_remove,
2274 };
2275
2276 void board_nand_init(void)
2277 {
2278         struct udevice *dev;
2279         int ret;
2280
2281         ret = uclass_get_device_by_driver(UCLASS_MTD,
2282                                           DM_DRIVER_GET(atmel_nand_controller),
2283                                           &dev);
2284         if (ret && ret != -ENODEV)
2285                 printf("Failed to initialize NAND controller. (error %d)\n",
2286                        ret);
2287 }