2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 * Configuration settings for the MX53ARD Freescale board.
6 * SPDX-License-Identifier: GPL-2.0+
12 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_ARD
14 #include <asm/arch/imx-regs.h>
16 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
17 #define CONFIG_SETUP_MEMORY_TAGS
18 #define CONFIG_INITRD_TAG
19 #define CONFIG_REVISION_TAG
21 #define CONFIG_SYS_FSL_CLK
23 /* Size of malloc() pool */
24 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
26 #define CONFIG_MXC_GPIO
28 #define CONFIG_SYS_MAX_NAND_DEVICE 1
29 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
30 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
31 #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
32 #define CONFIG_SYS_NAND_LARGEPAGE
33 #define CONFIG_MXC_NAND_HWECC
34 #define CONFIG_SYS_NAND_USE_FLASH_BBT
36 #define CONFIG_MXC_UART
37 #define CONFIG_MXC_UART_BASE UART1_BASE
40 #define CONFIG_SYS_I2C
41 #define CONFIG_SYS_I2C_MXC
42 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
43 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
44 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
47 #define CONFIG_FSL_ESDHC
48 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
49 #define CONFIG_SYS_FSL_ESDHC_NUM 2
52 #define CONFIG_HAS_ETH1
55 /* allow to overwrite serial and ethaddr */
56 #define CONFIG_ENV_OVERWRITE
57 #define CONFIG_CONS_INDEX 1
59 /* Command definition */
61 #define CONFIG_ETHPRIME "smc911x"
63 #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
64 #define CONFIG_SYS_TEXT_BASE 0x77800000
66 #define CONFIG_EXTRA_ENV_SETTINGS \
70 "fdt_high=0xffffffff\0" \
71 "initrd_high=0xffffffff\0" \
72 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
73 "fdt_addr=0x78000000\0" \
76 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
78 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
79 "update_sd_firmware_filename=u-boot.imx\0" \
80 "update_sd_firmware=" \
81 "if test ${ip_dyn} = yes; then " \
82 "setenv get_cmd dhcp; " \
84 "setenv get_cmd tftp; " \
86 "if mmc dev ${mmcdev}; then " \
87 "if ${get_cmd} ${update_sd_firmware_filename}; then " \
88 "setexpr fw_sz ${filesize} / 0x200; " \
89 "setexpr fw_sz ${fw_sz} + 1; " \
90 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
93 "mmcargs=setenv bootargs console=${console},${baudrate} " \
96 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
97 "bootscript=echo Running bootscript from mmc ...; " \
99 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
100 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
101 "mmcboot=echo Booting from mmc ...; " \
103 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
104 "if run loadfdt; then " \
105 "bootz ${loadaddr} - ${fdt_addr}; " \
107 "if test ${boot_fdt} = try; then " \
110 "echo WARN: Cannot load the DT; " \
116 "netargs=setenv bootargs console=${console},${baudrate} " \
118 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
119 "netboot=echo Booting from net ...; " \
121 "if test ${ip_dyn} = yes; then " \
122 "setenv get_cmd dhcp; " \
124 "setenv get_cmd tftp; " \
126 "${get_cmd} ${uimage}; " \
127 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
128 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
129 "bootz ${loadaddr} - ${fdt_addr}; " \
131 "if test ${boot_fdt} = try; then " \
134 "echo WARN: Cannot load the DT; " \
141 #define CONFIG_BOOTCOMMAND \
142 "mmc dev ${mmcdev}; if mmc rescan; then " \
143 "if run loadbootscript; then " \
146 "if run loaduimage; then " \
148 "else run netboot; " \
151 "else run netboot; fi"
153 #define CONFIG_ARP_TIMEOUT 200UL
155 /* Miscellaneous configurable options */
156 #define CONFIG_SYS_LONGHELP /* undef to save memory */
157 #define CONFIG_AUTO_COMPLETE
159 #define CONFIG_SYS_MEMTEST_START 0x70000000
160 #define CONFIG_SYS_MEMTEST_END 0x70010000
162 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
164 #define CONFIG_CMDLINE_EDITING
166 /* Physical Memory Map */
167 #define CONFIG_NR_DRAM_BANKS 2
168 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
169 #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
170 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
171 #define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
172 #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
174 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
175 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
176 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
178 #define CONFIG_SYS_INIT_SP_OFFSET \
179 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
180 #define CONFIG_SYS_INIT_SP_ADDR \
181 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
183 /* environment organization */
184 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
185 #define CONFIG_ENV_SIZE (8 * 1024)
186 #define CONFIG_SYS_MMC_ENV_DEV 0
188 #define MX53ARD_CS1GCR1 (CSEN | DSZ(2))
189 #define MX53ARD_CS1RCR1 (RCSN(2) | OEN (1) | RWSC(22))
190 #define MX53ARD_CS1RCR2 RBEN(2)
191 #define MX53ARD_CS1WCR1 (WCSN(2) | WEN(2) | WBEN(2) | WWSC(22))
193 #endif /* __CONFIG_H */