include/configs/da850evm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <[email protected]>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16
  17 /*
  18  * SoC Configuration
  19  */
  20 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  21 #define CONFIG_SYS_OSCIN_FREQ           24000000
  22 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  23 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  24
  25 #ifdef CONFIG_MTD_NOR_FLASH
  26 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  27 #endif
  28
  29 /*
  30  * Memory Info
  31  */
  32 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  33 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  34 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  35 /* memtest start addr */
  36
  37 /* memtest will be run on 16MB */
  38
  39 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  40         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  41         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  42         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  43         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  44         DAVINCI_SYSCFG_SUSPSRC_I2C)
  45
  46 /*
  47  * PLL configuration
  48  */
  49
  50 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  51 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  52
  53 /*
  54  * DDR2 memory configuration
  55  */
  56 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  57                                         DV_DDR_PHY_EXT_STRBEN | \
  58                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  59
  60 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  61         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
  62         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  63         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  64         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  65         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  66         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  67         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  68
  69 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  70 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  71
  72 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  73         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  74         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  75         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  76         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  77         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  78         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
  79         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
  80         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
  81
  82 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
  83         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
  84         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
  85         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
  86         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
  87         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
  88         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
  89         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
  90
  91 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
  92 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
  93
  94 /*
  95  * Serial Driver info
  96  */
  97 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
  98
  99 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 100
 101 /*
 102  * I2C Configuration
 103  */
 104 #ifndef CONFIG_SPL_BUILD
 105 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 106 #endif
 107
 108 /*
 109  * Flash & Environment
 110  */
 111 #ifdef CONFIG_MTD_RAW_NAND
 112 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 113 #define CONFIG_SYS_NAND_PAGE_2K
 114 #define CONFIG_SYS_NAND_CS              3
 115 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 116 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 117 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 118 #undef CONFIG_SYS_NAND_HW_ECC
 119 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 120 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 121 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x40000
 122 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 123 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 124 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 125                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 126                                         CONFIG_SYS_MALLOC_LEN -       \
 127                                         GENERATED_GBL_DATA_SIZE)
 128 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 129                                 24, 25, 26, 27, 28, \
 130                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 131                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 132                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 133                                 59, 60, 61, 62, 63 }
 134 #define CONFIG_SYS_NAND_ECCSIZE         512
 135 #define CONFIG_SYS_NAND_ECCBYTES        10
 136 #endif
 137
 138 #ifdef CONFIG_MTD_NOR_FLASH
 139 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 140 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 141 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 142 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 143                + 3)
 144 #endif
 145
 146 /*
 147  * U-Boot general configuration
 148  */
 149
 150 /*
 151  * Linux Information
 152  */
 153 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 154 #define CONFIG_HWCONFIG         /* enable hwconfig */
 155
 156 #define DEFAULT_LINUX_BOOT_ENV \
 157         "loadaddr=0xc0700000\0" \
 158         "fdtaddr=0xc0600000\0" \
 159         "scriptaddr=0xc0600000\0"
 160
 161 #include <environment/ti/mmc.h>
 162
 163 #define CONFIG_EXTRA_ENV_SETTINGS \
 164         DEFAULT_LINUX_BOOT_ENV \
 165         DEFAULT_MMC_TI_ARGS \
 166         "bootpart=0:2\0" \
 167         "bootdir=/boot\0" \
 168         "bootfile=zImage\0" \
 169         "fdtfile=da850-evm.dtb\0" \
 170         "boot_fdt=yes\0" \
 171         "boot_fit=0\0" \
 172         "console=ttyS2,115200n8\0" \
 173         "hwconfig=dsp:wake=yes"
 174
 175 /* USB Configs */
 176 #define CONFIG_USB_OHCI_NEW
 177 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 178
 179 #ifdef CONFIG_SPL_BUILD
 180 /* defines for SPL */
 181
 182 #endif
 183
 184 /* Load U-Boot Image From MMC */
 185
 186 /* additions for new relocation code, must added to all boards */
 187 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 188
 189 #include <asm/arch/hardware.h>
 190
 191 #endif /* __CONFIG_H */