1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2013 Imagination Technologies
14 #include <asm/global_data.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
19 #include <mach/jz4780.h>
20 #include <mach/jz4780_dram.h>
21 #include <mach/jz4780_gpio.h>
30 static void ci20_mux_mmc(void)
32 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
35 writel(0x30f00000, gpio_regs + GPIO_PXINTC(4));
36 writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4));
37 writel(0x30f00000, gpio_regs + GPIO_PXPAT1C(4));
38 writel(0x30f00000, gpio_regs + GPIO_PXPAT0C(4));
39 writel(0x30f00000, gpio_regs + GPIO_PXPENC(4));
40 jz4780_clk_ungate_mmc();
43 #ifndef CONFIG_SPL_BUILD
45 static void ci20_mux_eth(void)
47 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
49 #ifdef CONFIG_MTD_RAW_NAND
50 /* setup pins (some already setup for NAND) */
51 writel(0x04030000, gpio_regs + GPIO_PXINTC(0));
52 writel(0x04030000, gpio_regs + GPIO_PXMASKC(0));
53 writel(0x04030000, gpio_regs + GPIO_PXPAT1C(0));
54 writel(0x04030000, gpio_regs + GPIO_PXPAT0C(0));
55 writel(0x04030000, gpio_regs + GPIO_PXPENS(0));
57 /* setup pins (as above +NAND CS +RD/WE +SDx +SAx) */
58 writel(0x0dff00ff, gpio_regs + GPIO_PXINTC(0));
59 writel(0x0dff00ff, gpio_regs + GPIO_PXMASKC(0));
60 writel(0x0dff00ff, gpio_regs + GPIO_PXPAT1C(0));
61 writel(0x0dff00ff, gpio_regs + GPIO_PXPAT0C(0));
62 writel(0x0dff00ff, gpio_regs + GPIO_PXPENS(0));
63 writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
64 writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
65 writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
66 writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
67 writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
71 static void ci20_mux_jtag(void)
74 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
77 writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
78 writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
79 writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
80 writel(3 << 30, gpio_regs + GPIO_PXPAT0C(0));
84 static void ci20_mux_nand(void)
86 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
89 writel(0x002c00ff, gpio_regs + GPIO_PXINTC(0));
90 writel(0x002c00ff, gpio_regs + GPIO_PXMASKC(0));
91 writel(0x002c00ff, gpio_regs + GPIO_PXPAT1C(0));
92 writel(0x002c00ff, gpio_regs + GPIO_PXPAT0C(0));
93 writel(0x002c00ff, gpio_regs + GPIO_PXPENS(0));
94 writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
95 writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
96 writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
97 writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
98 writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
101 jz47xx_gpio_direction_input(JZ_GPIO(0, 20));
102 writel(20, gpio_regs + GPIO_PXPENS(0));
104 /* disable write protect */
105 jz47xx_gpio_direction_output(JZ_GPIO(5, 22), 1);
108 static void ci20_mux_uart(void)
110 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
113 writel(0x9, gpio_regs + GPIO_PXINTC(5));
114 writel(0x9, gpio_regs + GPIO_PXMASKC(5));
115 writel(0x9, gpio_regs + GPIO_PXPAT1C(5));
116 writel(0x9, gpio_regs + GPIO_PXPAT0C(5));
117 writel(0x9, gpio_regs + GPIO_PXPENC(5));
118 jz4780_clk_ungate_uart(0);
121 jz4780_clk_ungate_uart(1);
122 jz4780_clk_ungate_uart(2);
126 writel(1 << 12, gpio_regs + GPIO_PXINTC(3));
127 writel(1 << 12, gpio_regs + GPIO_PXMASKS(3));
128 writel(1 << 12, gpio_regs + GPIO_PXPAT1S(3));
129 writel(1 << 12, gpio_regs + GPIO_PXPAT0C(3));
130 writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
131 writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
132 writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
133 writel(1 << 30, gpio_regs + GPIO_PXPAT0C(0));
134 writel(1 << 31, gpio_regs + GPIO_PXPAT0S(0));
135 jz4780_clk_ungate_uart(3);
139 writel(0x100400, gpio_regs + GPIO_PXINTC(2));
140 writel(0x100400, gpio_regs + GPIO_PXMASKC(2));
141 writel(0x100400, gpio_regs + GPIO_PXPAT1S(2));
142 writel(0x100400, gpio_regs + GPIO_PXPAT0C(2));
143 writel(0x100400, gpio_regs + GPIO_PXPENC(2));
144 jz4780_clk_ungate_uart(4);
147 int board_early_init_f(void)
156 /* SYS_POWER_IND high (LED blue, VBUS off) */
157 jz47xx_gpio_direction_output(JZ_GPIO(5, 15), 0);
160 jz47xx_gpio_direction_output(JZ_GPIO(2, 0), 0);
161 jz47xx_gpio_direction_output(JZ_GPIO(2, 1), 0);
162 jz47xx_gpio_direction_output(JZ_GPIO(2, 2), 0);
163 jz47xx_gpio_direction_output(JZ_GPIO(2, 3), 0);
168 int misc_init_r(void)
170 const u32 efuse_clk = jz4780_clk_get_efuse_clk();
172 char manufacturer[3];
174 /* Read the board OTP data */
175 jz4780_efuse_init(efuse_clk);
176 jz4780_efuse_read(0x18, 16, (u8 *)&otp);
178 /* Set MAC address */
179 if (!is_valid_ethaddr(otp.mac)) {
180 /* no MAC assigned, generate one from the unique chip ID */
181 jz4780_efuse_read(0x8, 4, &otp.mac[0]);
182 jz4780_efuse_read(0x12, 2, &otp.mac[4]);
183 otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01;
185 eth_env_set_enetaddr("ethaddr", otp.mac);
187 /* Put other board information into the environment */
188 env_set_ulong("serial#", otp.serial_number);
189 env_set_ulong("board_date", otp.date);
190 manufacturer[0] = otp.manufacturer[0];
191 manufacturer[1] = otp.manufacturer[1];
193 env_set("board_mfr", manufacturer);
198 #ifdef CONFIG_DRIVER_DM9000
199 int board_eth_init(struct bd_info *bis)
202 jz4780_clk_ungate_ethernet();
204 /* Enable power (PB25) */
205 jz47xx_gpio_direction_output(JZ_GPIO(1, 25), 1);
209 jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 0);
211 jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 1);
214 return dm9000_initialize(bis);
216 #endif /* CONFIG_DRIVER_DM9000 */
219 static u8 ci20_revision(void)
221 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
224 jz47xx_gpio_direction_input(JZ_GPIO(2, 18));
225 jz47xx_gpio_direction_input(JZ_GPIO(2, 19));
228 writel(BIT(18) | BIT(19), gpio_regs + GPIO_PXPENC(2));
230 /* Read PC18/19 for version */
231 val = (!!jz47xx_gpio_get_value(JZ_GPIO(2, 18))) |
232 ((!!jz47xx_gpio_get_value(JZ_GPIO(2, 19))) << 1);
234 if (val == 3) /* Rev 1 boards had no pulldowns - giving 3 */
236 if (val == 1) /* Rev 2 boards pulldown port C bit 18 giving 1 */
244 gd->ram_size = sdram_size(0) + sdram_size(1);
248 /* U-Boot common routines */
251 printf("Board: Creator CI20 (rev.%d)\n", ci20_revision());
255 #ifdef CONFIG_SPL_BUILD
257 #if defined(CONFIG_SPL_MMC)
258 int board_mmc_init(struct bd_info *bd)
261 return jz_mmc_init((void __iomem *)MSC0_BASE);
265 static const struct jz4780_ddr_config K4B2G0846Q_48_config = {
267 (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
268 (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
270 (4 << DDRC_TIMING2_TCCD_BIT) | (15 << DDRC_TIMING2_TRAS_BIT) |
271 (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
273 (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
274 (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
275 (21 << DDRC_TIMING3_TRC_BIT),
277 (31 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
278 (4 << DDRC_TIMING4_TCKE_BIT) | (9 << DDRC_TIMING4_TMINSR_BIT) |
279 (8 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
281 (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
282 (4 << DDRC_TIMING5_TWDLAT_BIT),
284 (25 << DDRC_TIMING6_TXSRD_BIT) | (12 << DDRC_TIMING6_TFAW_BIT) |
285 (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
289 /* Mode Register 0 */
291 #ifdef SDRAM_DISABLE_DLL
292 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
294 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
309 static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = {
311 (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
312 (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
314 (4 << DDRC_TIMING2_TCCD_BIT) | (16 << DDRC_TIMING2_TRAS_BIT) |
315 (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
317 (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
318 (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
319 (22 << DDRC_TIMING3_TRC_BIT),
321 (42 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
322 (4 << DDRC_TIMING4_TCKE_BIT) | (7 << DDRC_TIMING4_TMINSR_BIT) |
323 (3 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
325 (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
326 (4 << DDRC_TIMING5_TWDLAT_BIT),
328 (25 << DDRC_TIMING6_TXSRD_BIT) | (20 << DDRC_TIMING6_TFAW_BIT) |
329 (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
333 /* Mode Register 0 */
335 #ifdef SDRAM_DISABLE_DLL
336 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
338 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
353 #if (CONFIG_SYS_MHZ != 1200)
354 #error No DDR configuration for CPU speed
357 const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
359 const int board_revision = ci20_revision();
361 if (board_revision == 2)
362 return &K4B2G0846Q_48_config;
363 else /* Fall back to H5TQ2G83CFR RAM */
364 return &H5TQ2G83CFR_48_config;