include/configs/amcore.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Sysam AMCORE board configuration
   4  *
   5  * (C) Copyright 2016  Angelo Dureghello <[email protected]>
   6  */
   7
   8 #ifndef __AMCORE_CONFIG_H
   9 #define __AMCORE_CONFIG_H
  10
  11 #define CONFIG_HOSTNAME                 "AMCORE"
  12
  13 #define CONFIG_MCFTMR
  14 #define CONFIG_SYS_UART_PORT            0
  15
  16 #define CONFIG_EXTRA_ENV_SETTINGS                               \
  17         "upgrade_uboot=loady; "                                 \
  18                 "protect off 0xffc00000 0xffc1ffff; "           \
  19                 "erase 0xffc00000 0xffc1ffff; "                 \
  20                 "cp.b 0x20000 0xffc00000 ${filesize}\0"         \
  21         "upgrade_kernel=loady; "                                \
  22                 "erase 0xffc20000 0xffefffff; "                 \
  23                 "cp.b 0x20000 0xffc20000 ${filesize}\0"         \
  24         "upgrade_jffs2=loady; "                                 \
  25                 "erase 0xfff00000 0xffffffff; "                 \
  26                 "cp.b 0x20000 0xfff00000 ${filesize}\0"
  27
  28 #define CONFIG_SYS_CLK                  45000000
  29 #define CONFIG_SYS_CPU_CLK              (CONFIG_SYS_CLK * 2)
  30 /* Register Base Addrs */
  31 #define CONFIG_SYS_MBAR                 0x10000000
  32 /* Definitions for initial stack pointer and data area (in DPRAM) */
  33 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
  34 /* size of internal SRAM */
  35 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
  36 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  37                                          GENERATED_GBL_DATA_SIZE)
  38 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  39
  40 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  41 #define CONFIG_SYS_SDRAM_SIZE           0x1000000
  42 #define CONFIG_SYS_FLASH_BASE           0xffc00000
  43 #define CONFIG_SYS_MAX_FLASH_SECT       1024
  44 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
  45
  46 /* amcore design has flash data bytes wired swapped */
  47 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  48 /* reserve 128-4KB */
  49 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
  50 #define CONFIG_SYS_MONITOR_LEN          ((128 - 4) * 1024)
  51 #define CONFIG_SYS_BOOTPARAMS_LEN       (64 * 1024)
  52
  53 #define LDS_BOARD_TEXT \
  54         . = DEFINED(env_offset) ? env_offset : .; \
  55         env/embedded.o(.text*);
  56
  57 /* memory map space for linux boot data */
  58 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
  59
  60 /*
  61  * Cache Configuration
  62  *
  63  * Special 8K version 3 core cache.
  64  * This is a single unified instruction/data cache.
  65  * sdram - single region - no masks
  66  */
  67
  68 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
  69                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
  70 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
  71                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
  72 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
  73 #define CONFIG_SYS_CACHE_ACR0           (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
  74                                          CF_ACR_EN)
  75 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_DCM_P | CF_CACR_ESB | \
  76                                          CF_CACR_EC)
  77
  78 /* CS0 - AMD Flash, address 0xffc00000 */
  79 #define CONFIG_SYS_CS0_BASE             (CONFIG_SYS_FLASH_BASE>>16)
  80 /* 4MB, AA=0,V=1  C/I BIT for errata */
  81 #define CONFIG_SYS_CS0_MASK             0x003f0001
  82 /* WS=10, AA=1, PS=16bit (10) */
  83 #define CONFIG_SYS_CS0_CTRL             0x1980
  84 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
  85 #define CONFIG_SYS_CS1_BASE             0x3000
  86 #define CONFIG_SYS_CS1_MASK             0x00070001
  87 #define CONFIG_SYS_CS1_CTRL             0x0100
  88
  89 #endif  /* __AMCORE_CONFIG_H */