board/ti/am57xx/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
   4  *
   5  * Author: Felipe Balbi <[email protected]>
   6  *
   7  * Based on board/ti/dra7xx/evm.c
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <fastboot.h>
  13 #include <fdt_support.h>
  14 #include <init.h>
  15 #include <malloc.h>
  16 #include <net.h>
  17 #include <palmas.h>
  18 #include <sata.h>
  19 #include <serial.h>
  20 #include <usb.h>
  21 #include <errno.h>
  22 #include <asm/global_data.h>
  23 #include <asm/omap_common.h>
  24 #include <asm/emif.h>
  25 #include <asm/gpio.h>
  26 #include <asm/arch/gpio.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch/dra7xx_iodelay.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/arch/mmc_host_def.h>
  31 #include <asm/arch/sata.h>
  32 #include <asm/arch/gpio.h>
  33 #include <asm/arch/omap.h>
  34 #include <usb.h>
  35 #include <linux/usb/gadget.h>
  36 #include <dwc3-uboot.h>
  37 #include <dwc3-omap-uboot.h>
  38 #include <ti-usb-phy-uboot.h>
  39 #include <mmc.h>
  40 #include <dm/uclass.h>
  41 #include <hang.h>
  42
  43 #include "../common/board_detect.h"
  44 #include "../common/cape_detect.h"
  45 #include "mux_data.h"
  46
  47 #ifdef CONFIG_SUPPORT_EMMC_BOOT
  48 static int board_bootmode_has_emmc(void);
  49 #endif
  50
  51 #define board_is_x15()          board_ti_is("BBRDX15_")
  52 #define board_is_x15_revb1()    (board_ti_is("BBRDX15_") && \
  53                                  !strncmp("B.10", board_ti_get_rev(), 3))
  54 #define board_is_x15_revc()     (board_ti_is("BBRDX15_") && \
  55                                  !strncmp("C.00", board_ti_get_rev(), 3))
  56 #define board_is_am572x_evm()   board_ti_is("AM572PM_")
  57 #define board_is_am572x_evm_reva3()     \
  58                                 (board_ti_is("AM572PM_") && \
  59                                  !strncmp("A.30", board_ti_get_rev(), 3))
  60 #define board_is_am574x_idk()   board_ti_is("AM574IDK")
  61 #define board_is_am572x_idk()   board_ti_is("AM572IDK")
  62 #define board_is_am571x_idk()   board_ti_is("AM571IDK")
  63 #define board_is_bbai()         board_ti_is("BBONE-AI")
  64
  65 #define board_is_ti_idk()       board_is_am574x_idk() || \
  66                                 board_is_am572x_idk() || \
  67                                 board_is_am571x_idk()
  68
  69 #ifdef CONFIG_DRIVER_TI_CPSW
  70 #include <cpsw.h>
  71 #endif
  72
  73 DECLARE_GLOBAL_DATA_PTR;
  74
  75 #define GPIO_ETH_LCD            GPIO_TO_PIN(2, 22)
  76 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(7, 11)
  77
  78 /* Touch screen controller to identify the LCD */
  79 #define OSD_TS_FT_BUS_ADDRESS   0
  80 #define OSD_TS_FT_CHIP_ADDRESS  0x38
  81 #define OSD_TS_FT_REG_ID        0xA3
  82 /*
  83  * Touchscreen IDs for various OSD panels
  84  * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  85  */
  86 /* Used on newer osd101t2587 Panels */
  87 #define OSD_TS_FT_ID_5x46       0x54
  88 /* Used on older osd101t2045 Panels */
  89 #define OSD_TS_FT_ID_5606       0x08
  90
  91 #define SYSINFO_BOARD_NAME_MAX_LEN      45
  92
  93 #define TPS65903X_PRIMARY_SECONDARY_PAD2        0xFB
  94 #define TPS65903X_PAD2_POWERHOLD_MASK           0x20
  95
  96 const struct omap_sysinfo sysinfo = {
  97         "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  98 };
  99
 100 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
 101         .dmm_lisa_map_3 = 0x80740300,
 102         .is_ma_present  = 0x1
 103 };
 104
 105 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
 106         .dmm_lisa_map_3 = 0x80640100,
 107         .is_ma_present  = 0x1
 108 };
 109
 110 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
 111         .dmm_lisa_map_2 = 0xc0600200,
 112         .dmm_lisa_map_3 = 0x80600100,
 113         .is_ma_present  = 0x1
 114 };
 115
 116 static const struct dmm_lisa_map_regs bbai_lisa_regs = {
 117         .dmm_lisa_map_3 = 0x80640100,
 118         .is_ma_present  = 0x1
 119 };
 120
 121 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 122 {
 123         if (board_is_am571x_idk())
 124                 *dmm_lisa_regs = &am571x_idk_lisa_regs;
 125         else if (board_is_am574x_idk())
 126                 *dmm_lisa_regs = &am574x_idk_lisa_regs;
 127         else if (board_is_bbai())
 128                 *dmm_lisa_regs = &bbai_lisa_regs;
 129         else
 130                 *dmm_lisa_regs = &beagle_x15_lisa_regs;
 131 }
 132
 133 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 134         .sdram_config_init              = 0x61851b32,
 135         .sdram_config                   = 0x61851b32,
 136         .sdram_config2                  = 0x08000000,
 137         .ref_ctrl                       = 0x000040F1,
 138         .ref_ctrl_final                 = 0x00001035,
 139         .sdram_tim1                     = 0xcccf36ab,
 140         .sdram_tim2                     = 0x308f7fda,
 141         .sdram_tim3                     = 0x409f88a8,
 142         .read_idle_ctrl                 = 0x00050000,
 143         .zq_config                      = 0x5007190b,
 144         .temp_alert_config              = 0x00000000,
 145         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 146         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 147         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 148         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 149         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 150         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 151         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 152         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 153         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 154         .emif_rd_wr_lvl_ctl             = 0x00000000,
 155         .emif_rd_wr_exec_thresh         = 0x00000305
 156 };
 157
 158 /* Ext phy ctrl regs 1-35 */
 159 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 160         0x10040100,
 161         0x00910091,
 162         0x00950095,
 163         0x009B009B,
 164         0x009E009E,
 165         0x00980098,
 166         0x00340034,
 167         0x00350035,
 168         0x00340034,
 169         0x00310031,
 170         0x00340034,
 171         0x007F007F,
 172         0x007F007F,
 173         0x007F007F,
 174         0x007F007F,
 175         0x007F007F,
 176         0x00480048,
 177         0x004A004A,
 178         0x00520052,
 179         0x00550055,
 180         0x00500050,
 181         0x00000000,
 182         0x00600020,
 183         0x40011080,
 184         0x08102040,
 185         0x0,
 186         0x0,
 187         0x0,
 188         0x0,
 189         0x0,
 190         0x0,
 191         0x0,
 192         0x0,
 193         0x0,
 194         0x0
 195 };
 196
 197 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 198         .sdram_config_init              = 0x61851b32,
 199         .sdram_config                   = 0x61851b32,
 200         .sdram_config2                  = 0x08000000,
 201         .ref_ctrl                       = 0x000040F1,
 202         .ref_ctrl_final                 = 0x00001035,
 203         .sdram_tim1                     = 0xcccf36b3,
 204         .sdram_tim2                     = 0x308f7fda,
 205         .sdram_tim3                     = 0x407f88a8,
 206         .read_idle_ctrl                 = 0x00050000,
 207         .zq_config                      = 0x5007190b,
 208         .temp_alert_config              = 0x00000000,
 209         .emif_ddr_phy_ctlr_1_init       = 0x0024400b,
 210         .emif_ddr_phy_ctlr_1            = 0x0e24400b,
 211         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 212         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 213         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 214         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 215         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 216         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 217         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 218         .emif_rd_wr_lvl_ctl             = 0x00000000,
 219         .emif_rd_wr_exec_thresh         = 0x00000305
 220 };
 221
 222 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
 223         0x10040100,
 224         0x00910091,
 225         0x00950095,
 226         0x009B009B,
 227         0x009E009E,
 228         0x00980098,
 229         0x00340034,
 230         0x00350035,
 231         0x00340034,
 232         0x00310031,
 233         0x00340034,
 234         0x007F007F,
 235         0x007F007F,
 236         0x007F007F,
 237         0x007F007F,
 238         0x007F007F,
 239         0x00480048,
 240         0x004A004A,
 241         0x00520052,
 242         0x00550055,
 243         0x00500050,
 244         0x00000000,
 245         0x00600020,
 246         0x40011080,
 247         0x08102040,
 248         0x0,
 249         0x0,
 250         0x0,
 251         0x0,
 252         0x0,
 253         0x0,
 254         0x0,
 255         0x0,
 256         0x0,
 257         0x0
 258 };
 259
 260 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
 261         .sdram_config_init              = 0x61863332,
 262         .sdram_config                   = 0x61863332,
 263         .sdram_config2                  = 0x08000000,
 264         .ref_ctrl                       = 0x0000514d,
 265         .ref_ctrl_final                 = 0x0000144a,
 266         .sdram_tim1                     = 0xd333887c,
 267         .sdram_tim2                     = 0x30b37fe3,
 268         .sdram_tim3                     = 0x409f8ad8,
 269         .read_idle_ctrl                 = 0x00050000,
 270         .zq_config                      = 0x5007190b,
 271         .temp_alert_config              = 0x00000000,
 272         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 273         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 274         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 275         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 276         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 277         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 278         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 279         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 280         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 281         .emif_rd_wr_lvl_ctl             = 0x00000000,
 282         .emif_rd_wr_exec_thresh         = 0x00000305
 283 };
 284
 285 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
 286         .sdram_config_init              = 0x61863332,
 287         .sdram_config                   = 0x61863332,
 288         .sdram_config2                  = 0x08000000,
 289         .ref_ctrl                       = 0x0000514d,
 290         .ref_ctrl_final                 = 0x0000144a,
 291         .sdram_tim1                     = 0xd333887c,
 292         .sdram_tim2                     = 0x30b37fe3,
 293         .sdram_tim3                     = 0x409f8ad8,
 294         .read_idle_ctrl                 = 0x00050000,
 295         .zq_config                      = 0x5007190b,
 296         .temp_alert_config              = 0x00000000,
 297         .emif_ddr_phy_ctlr_1_init       = 0x0024400f,
 298         .emif_ddr_phy_ctlr_1            = 0x0e24400f,
 299         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 300         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 301         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 302         .emif_ddr_ext_phy_ctrl_4        = 0x009b009b,
 303         .emif_ddr_ext_phy_ctrl_5        = 0x009e009e,
 304         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 305         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 306         .emif_rd_wr_lvl_ctl             = 0x00000000,
 307         .emif_rd_wr_exec_thresh         = 0x00000305,
 308         .emif_ecc_ctrl_reg              = 0xD0000001,
 309         .emif_ecc_address_range_1       = 0x3FFF0000,
 310         .emif_ecc_address_range_2       = 0x00000000
 311 };
 312
 313 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 314 {
 315         switch (emif_nr) {
 316         case 1:
 317                 if (board_is_am571x_idk())
 318                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 319                 else if (board_is_am574x_idk())
 320                         *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
 321                 else
 322                         *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
 323                 break;
 324         case 2:
 325                 if (board_is_am574x_idk())
 326                         *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
 327                 else
 328                         *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
 329                 break;
 330         }
 331 }
 332
 333 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 334 {
 335         switch (emif_nr) {
 336         case 1:
 337                 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
 338                 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
 339                 break;
 340         case 2:
 341                 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
 342                 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
 343                 break;
 344         }
 345 }
 346
 347 struct vcores_data beagle_x15_volts = {
 348         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 349         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 350         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 351         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 352         .mpu.pmic               = &tps659038,
 353         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 354
 355         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 356         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 357         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 358         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 359         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 360         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 361         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 362         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 363         .eve.pmic               = &tps659038,
 364         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 365
 366         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 367         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 368         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 369         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 370         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 371         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 372         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 373         .gpu.addr               = TPS659038_REG_ADDR_SMPS45,
 374         .gpu.pmic               = &tps659038,
 375         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 376
 377         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 378         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 379         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 380         .core.addr              = TPS659038_REG_ADDR_SMPS6,
 381         .core.pmic              = &tps659038,
 382
 383         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 384         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 385         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 386         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 387         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 388         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 389         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 390         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 391         .iva.pmic               = &tps659038,
 392         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 393 };
 394
 395 struct vcores_data am572x_idk_volts = {
 396         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 397         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 398         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 399         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 400         .mpu.pmic               = &tps659038,
 401         .mpu.abb_tx_done_mask   = OMAP_ABB_MPU_TXDONE_MASK,
 402
 403         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 404         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 405         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 406         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 407         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 408         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 409         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 410         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 411         .eve.pmic               = &tps659038,
 412         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 413
 414         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 415         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 416         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 417         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 418         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 419         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 420         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 421         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 422         .gpu.pmic               = &tps659038,
 423         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 424
 425         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 426         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 427         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 428         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 429         .core.pmic              = &tps659038,
 430
 431         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 432         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 433         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 434         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 435         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 436         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 437         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 438         .iva.addr               = TPS659038_REG_ADDR_SMPS8,
 439         .iva.pmic               = &tps659038,
 440         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 441 };
 442
 443 struct vcores_data am571x_idk_volts = {
 444         .mpu.value[OPP_NOM]     = VDD_MPU_DRA7_NOM,
 445         .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
 446         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 447         .mpu.addr               = TPS659038_REG_ADDR_SMPS12,
 448         .mpu.pmic               = &tps659038,
 449         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 450
 451         .eve.value[OPP_NOM]     = VDD_EVE_DRA7_NOM,
 452         .eve.value[OPP_OD]      = VDD_EVE_DRA7_OD,
 453         .eve.value[OPP_HIGH]    = VDD_EVE_DRA7_HIGH,
 454         .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 455         .eve.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_DSPEVE_OD,
 456         .eve.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 457         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 458         .eve.addr               = TPS659038_REG_ADDR_SMPS45,
 459         .eve.pmic               = &tps659038,
 460         .eve.abb_tx_done_mask   = OMAP_ABB_EVE_TXDONE_MASK,
 461
 462         .gpu.value[OPP_NOM]     = VDD_GPU_DRA7_NOM,
 463         .gpu.value[OPP_OD]      = VDD_GPU_DRA7_OD,
 464         .gpu.value[OPP_HIGH]    = VDD_GPU_DRA7_HIGH,
 465         .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
 466         .gpu.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_GPU_OD,
 467         .gpu.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_GPU_HIGH,
 468         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 469         .gpu.addr               = TPS659038_REG_ADDR_SMPS6,
 470         .gpu.pmic               = &tps659038,
 471         .gpu.abb_tx_done_mask   = OMAP_ABB_GPU_TXDONE_MASK,
 472
 473         .core.value[OPP_NOM]    = VDD_CORE_DRA7_NOM,
 474         .core.efuse.reg[OPP_NOM]        = STD_FUSE_OPP_VMIN_CORE_NOM,
 475         .core.efuse.reg_bits    = DRA752_EFUSE_REGBITS,
 476         .core.addr              = TPS659038_REG_ADDR_SMPS7,
 477         .core.pmic              = &tps659038,
 478
 479         .iva.value[OPP_NOM]     = VDD_IVA_DRA7_NOM,
 480         .iva.value[OPP_OD]      = VDD_IVA_DRA7_OD,
 481         .iva.value[OPP_HIGH]    = VDD_IVA_DRA7_HIGH,
 482         .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
 483         .iva.efuse.reg[OPP_OD]  = STD_FUSE_OPP_VMIN_IVA_OD,
 484         .iva.efuse.reg[OPP_HIGH]        = STD_FUSE_OPP_VMIN_IVA_HIGH,
 485         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 486         .iva.addr               = TPS659038_REG_ADDR_SMPS45,
 487         .iva.pmic               = &tps659038,
 488         .iva.abb_tx_done_mask   = OMAP_ABB_IVA_TXDONE_MASK,
 489 };
 490
 491 int get_voltrail_opp(int rail_offset)
 492 {
 493         int opp;
 494
 495         switch (rail_offset) {
 496         case VOLT_MPU:
 497                 opp = DRA7_MPU_OPP;
 498                 break;
 499         case VOLT_CORE:
 500                 opp = DRA7_CORE_OPP;
 501                 break;
 502         case VOLT_GPU:
 503                 opp = DRA7_GPU_OPP;
 504                 break;
 505         case VOLT_EVE:
 506                 opp = DRA7_DSPEVE_OPP;
 507                 break;
 508         case VOLT_IVA:
 509                 opp = DRA7_IVA_OPP;
 510                 break;
 511         default:
 512                 opp = OPP_NOM;
 513         }
 514
 515         return opp;
 516 }
 517
 518
 519 #ifdef CONFIG_SPL_BUILD
 520 /* No env to setup for SPL */
 521 static inline void setup_board_eeprom_env(void) { }
 522
 523 /* Override function to read eeprom information */
 524 void do_board_detect(void)
 525 {
 526         int rc;
 527
 528         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 529                                   CONFIG_EEPROM_CHIP_ADDRESS);
 530         if (rc)
 531                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 532
 533 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 534         rc = board_bootmode_has_emmc();
 535         if (!rc)
 536                 rc = ti_emmc_boardid_get();
 537         if (rc)
 538                 printf("ti_emmc_boardid_get failed %d\n", rc);
 539 #endif
 540 }
 541
 542 #else   /* CONFIG_SPL_BUILD */
 543
 544 /* Override function to read eeprom information: actual i2c read done by SPL*/
 545 void do_board_detect(void)
 546 {
 547         char *bname = NULL;
 548         int rc;
 549
 550         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 551                                   CONFIG_EEPROM_CHIP_ADDRESS);
 552         if (rc)
 553                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 554
 555 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 556         rc = board_bootmode_has_emmc();
 557         if (!rc)
 558                 rc = ti_emmc_boardid_get();
 559         if (rc)
 560                 printf("ti_emmc_boardid_get failed %d\n", rc);
 561 #endif
 562
 563         if (board_is_x15())
 564                 bname = "BeagleBoard X15";
 565         else if (board_is_am572x_evm())
 566                 bname = "AM572x EVM";
 567         else if (board_is_am574x_idk())
 568                 bname = "AM574x IDK";
 569         else if (board_is_am572x_idk())
 570                 bname = "AM572x IDK";
 571         else if (board_is_am571x_idk())
 572                 bname = "AM571x IDK";
 573         else if (board_is_bbai())
 574                 bname = "BeagleBone AI";
 575
 576         if (bname)
 577                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 578                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 579 }
 580
 581 static void setup_board_eeprom_env(void)
 582 {
 583         char *name = "beagle_x15";
 584         int rc;
 585
 586         rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 587                                   CONFIG_EEPROM_CHIP_ADDRESS);
 588         if (rc)
 589                 goto invalid_eeprom;
 590
 591         if (board_is_x15()) {
 592                 if (board_is_x15_revb1())
 593                         name = "beagle_x15_revb1";
 594                 else if (board_is_x15_revc())
 595                         name = "beagle_x15_revc";
 596                 else
 597                         name = "beagle_x15";
 598         } else if (board_is_am572x_evm()) {
 599                 if (board_is_am572x_evm_reva3())
 600                         name = "am57xx_evm_reva3";
 601                 else
 602                         name = "am57xx_evm";
 603         } else if (board_is_am574x_idk()) {
 604                 name = "am574x_idk";
 605         } else if (board_is_am572x_idk()) {
 606                 name = "am572x_idk";
 607         } else if (board_is_am571x_idk()) {
 608                 name = "am571x_idk";
 609         } else if (board_is_bbai()) {
 610                 name = "am5729_beagleboneai";
 611         } else {
 612                 printf("Unidentified board claims %s in eeprom header\n",
 613                        board_ti_get_name());
 614         }
 615
 616 invalid_eeprom:
 617         set_board_info_env(name);
 618 }
 619
 620 #endif  /* CONFIG_SPL_BUILD */
 621
 622 void vcores_init(void)
 623 {
 624         if (board_is_am572x_idk() || board_is_am574x_idk())
 625                 *omap_vcores = &am572x_idk_volts;
 626         else if (board_is_am571x_idk())
 627                 *omap_vcores = &am571x_idk_volts;
 628         else
 629                 *omap_vcores = &beagle_x15_volts;
 630 }
 631
 632 void hw_data_init(void)
 633 {
 634         *prcm = &dra7xx_prcm;
 635         if (is_dra72x())
 636                 *dplls_data = &dra72x_dplls;
 637         else if (is_dra76x())
 638                 *dplls_data = &dra76x_dplls;
 639         else
 640                 *dplls_data = &dra7xx_dplls;
 641         *ctrl = &dra7xx_ctrl;
 642 }
 643
 644 bool am571x_idk_needs_lcd(void)
 645 {
 646         bool needs_lcd;
 647
 648         gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
 649         if (gpio_get_value(GPIO_ETH_LCD))
 650                 needs_lcd = false;
 651         else
 652                 needs_lcd = true;
 653
 654         gpio_free(GPIO_ETH_LCD);
 655
 656         return needs_lcd;
 657 }
 658
 659 int board_init(void)
 660 {
 661         gpmc_init();
 662         gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100);
 663
 664         return 0;
 665 }
 666
 667 void am57x_idk_lcd_detect(void)
 668 {
 669         int r = -ENODEV;
 670         char *idk_lcd = "no";
 671         struct udevice *dev;
 672
 673         /* Only valid for IDKs */
 674         if (!board_is_ti_idk())
 675                 return;
 676
 677         /* Only AM571x IDK has gpio control detect.. so check that */
 678         if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
 679                 goto out;
 680
 681         r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
 682                                     OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
 683         if (r) {
 684                 printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
 685                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 686                        r);
 687                 /* AM572x IDK has no explicit settings for optional LCD kit */
 688                 if (board_is_am571x_idk())
 689                         printf("%s: Touch screen detect failed: %d!\n",
 690                                __func__, r);
 691                 goto out;
 692         }
 693
 694         /* Read FT ID */
 695         r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
 696         if (r < 0) {
 697                 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
 698                        __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
 699                        OSD_TS_FT_REG_ID, r);
 700                 goto out;
 701         }
 702
 703         switch (r) {
 704         case OSD_TS_FT_ID_5606:
 705                 idk_lcd = "osd101t2045";
 706                 break;
 707         case OSD_TS_FT_ID_5x46:
 708                 idk_lcd = "osd101t2587";
 709                 break;
 710         default:
 711                 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
 712                        __func__, r);
 713                 /* we will let default be "no lcd" */
 714         }
 715 out:
 716         env_set("idk_lcd", idk_lcd);
 717
 718         /*
 719          * On AM571x_IDK, no Display with J51 set to LCD is considered as an
 720          * invalid configuration and we prevent boot to get user attention.
 721          */
 722         if (board_is_am571x_idk() && am571x_idk_needs_lcd() &&
 723             !strncmp(idk_lcd, "no", 2)) {
 724                 printf("%s: Invalid HW configuration: display not detected/supported but J51 is set. Remove J51 to boot without display.\n",
 725                        __func__);
 726                 hang();
 727         }
 728
 729         return;
 730 }
 731
 732 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 733 static int device_okay(const char *path)
 734 {
 735         int node;
 736
 737         node = fdt_path_offset(gd->fdt_blob, path);
 738         if (node < 0)
 739                 return 0;
 740
 741         return fdtdec_get_is_enabled(gd->fdt_blob, node);
 742 }
 743 #endif
 744
 745 int board_late_init(void)
 746 {
 747         setup_board_eeprom_env();
 748         u8 val;
 749         struct udevice *dev;
 750
 751         /*
 752          * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 753          * This is the POWERHOLD-in-Low behavior.
 754          */
 755         palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
 756
 757         /*
 758          * Default FIT boot on HS devices. Non FIT images are not allowed
 759          * on HS devices.
 760          */
 761         if (get_device_type() == HS_DEVICE)
 762                 env_set("boot_fit", "1");
 763
 764         /*
 765          * Set the GPIO7 Pad to POWERHOLD. This has higher priority
 766          * over DEV_CTRL.DEV_ON bit. This can be reset in case of
 767          * PMIC Power off. So to be on the safer side set it back
 768          * to POWERHOLD mode irrespective of the current state.
 769          */
 770         palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 771                            &val);
 772         val = val | TPS65903X_PAD2_POWERHOLD_MASK;
 773         palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
 774                             val);
 775
 776         omap_die_id_serial();
 777         omap_set_fastboot_vars();
 778
 779         am57x_idk_lcd_detect();
 780
 781         /* Just probe the potentially supported cdce913 device */
 782         uclass_get_device(UCLASS_CLK, 0, &dev);
 783
 784         if (board_is_bbai())
 785                 env_set("console", "ttyS0,115200n8");
 786
 787 #if !defined(CONFIG_SPL_BUILD)
 788         board_ti_set_ethaddr(2);
 789 #endif
 790
 791 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
 792         if (device_okay("/ocp/omap_dwc3_1@48880000"))
 793                 enable_usb_clocks(0);
 794         if (device_okay("/ocp/omap_dwc3_2@488c0000"))
 795                 enable_usb_clocks(1);
 796 #endif
 797         return 0;
 798 }
 799
 800 void set_muxconf_regs(void)
 801 {
 802         do_set_mux32((*ctrl)->control_padconf_core_base,
 803                      early_padconf, ARRAY_SIZE(early_padconf));
 804
 805 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 806         do_set_mux32((*ctrl)->control_padconf_core_base,
 807                      emmc_padconf, ARRAY_SIZE(emmc_padconf));
 808 #endif
 809 }
 810
 811 #ifdef CONFIG_IODELAY_RECALIBRATION
 812 void recalibrate_iodelay(void)
 813 {
 814         const struct pad_conf_entry *pconf;
 815         const struct iodelay_cfg_entry *iod, *delta_iod;
 816         int pconf_sz, iod_sz, delta_iod_sz = 0;
 817         int ret;
 818
 819         if (board_is_am572x_idk()) {
 820                 pconf = core_padconf_array_essential_am572x_idk;
 821                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 822                 iod = iodelay_cfg_array_am572x_idk;
 823                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
 824         } else if (board_is_am574x_idk()) {
 825                 pconf = core_padconf_array_essential_am574x_idk;
 826                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
 827                 iod = iodelay_cfg_array_am574x_idk;
 828                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
 829         } else if (board_is_am571x_idk()) {
 830                 pconf = core_padconf_array_essential_am571x_idk;
 831                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 832                 iod = iodelay_cfg_array_am571x_idk;
 833                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 834         } else if (board_is_bbai()) {
 835                 pconf = core_padconf_array_essential_bbai;
 836                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_bbai);
 837                 iod = iodelay_cfg_array_bbai;
 838                 iod_sz = ARRAY_SIZE(iodelay_cfg_array_bbai);
 839         } else {
 840                 /* Common for X15/GPEVM */
 841                 pconf = core_padconf_array_essential_x15;
 842                 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 843                 /* There never was an SR1.0 X15.. So.. */
 844                 if (omap_revision() == DRA752_ES1_1) {
 845                         iod = iodelay_cfg_array_x15_sr1_1;
 846                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
 847                 } else {
 848                         /* Since full production should switch to SR2.0  */
 849                         iod = iodelay_cfg_array_x15_sr2_0;
 850                         iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
 851                 }
 852         }
 853
 854         /* Setup I/O isolation */
 855         ret = __recalibrate_iodelay_start();
 856         if (ret)
 857                 goto err;
 858
 859         /* Do the muxing here */
 860         do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 861
 862         /* Now do the weird minor deltas that should be safe */
 863         if (board_is_x15() || board_is_am572x_evm()) {
 864                 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
 865                     board_is_x15_revc()) {
 866                         pconf = core_padconf_array_delta_x15_sr2_0;
 867                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
 868                 } else {
 869                         pconf = core_padconf_array_delta_x15_sr1_1;
 870                         pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
 871                 }
 872                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 873         }
 874
 875         if (board_is_am571x_idk()) {
 876                 if (am571x_idk_needs_lcd()) {
 877                         pconf = core_padconf_array_vout_am571x_idk;
 878                         pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
 879                         delta_iod = iodelay_cfg_array_am571x_idk_4port;
 880                         delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
 881
 882                 } else {
 883                         pconf = core_padconf_array_icss1eth_am571x_idk;
 884                         pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
 885                 }
 886                 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
 887         }
 888
 889         /* Setup IOdelay configuration */
 890         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
 891         if (delta_iod_sz)
 892                 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
 893                                      delta_iod_sz);
 894
 895 err:
 896         /* Closeup.. remove isolation */
 897         __recalibrate_iodelay_end(ret);
 898 }
 899 #endif
 900
 901 #if defined(CONFIG_MMC)
 902 int board_mmc_init(struct bd_info *bis)
 903 {
 904         omap_mmc_init(0, 0, 0, -1, -1);
 905         omap_mmc_init(1, 0, 0, -1, -1);
 906         return 0;
 907 }
 908
 909 static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
 910         .hw_rev = "rev11",
 911         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 912                             MMC_CAP(UHS_SDR104),
 913         .max_freq = 96000000,
 914 };
 915
 916 static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
 917         .hw_rev = "rev11",
 918         .unsupported_caps = MMC_CAP(MMC_HS_200) |
 919                             MMC_CAP(UHS_SDR104) |
 920                             MMC_CAP(UHS_SDR50),
 921         .max_freq = 48000000,
 922 };
 923
 924 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
 925 {
 926         switch (omap_revision()) {
 927         case DRA752_ES1_0:
 928         case DRA752_ES1_1:
 929                 if (addr == OMAP_HSMMC1_BASE)
 930                         return &am57x_es1_1_mmc1_fixups;
 931                 else
 932                         return &am57x_es1_1_mmc23_fixups;
 933         default:
 934                 return NULL;
 935         }
 936 }
 937 #endif
 938
 939 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 940 int spl_start_uboot(void)
 941 {
 942         /* break into full u-boot on 'c' */
 943         if (serial_tstc() && serial_getc() == 'c')
 944                 return 1;
 945
 946 #ifdef CONFIG_SPL_ENV_SUPPORT
 947         env_init();
 948         env_load();
 949         if (env_get_yesno("boot_os") != 1)
 950                 return 1;
 951 #endif
 952
 953         return 0;
 954 }
 955 #endif
 956
 957 #ifdef CONFIG_DRIVER_TI_CPSW
 958
 959 /* Delay value to add to calibrated value */
 960 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 961 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 962 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 963 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 964 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 965 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 966 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 967 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 968 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 969 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 970
 971 static void cpsw_control(int enabled)
 972 {
 973         /* VTP can be added here */
 974 }
 975
 976 static struct cpsw_slave_data cpsw_slaves[] = {
 977         {
 978                 .slave_reg_ofs  = 0x208,
 979                 .sliver_reg_ofs = 0xd80,
 980                 .phy_addr       = 1,
 981         },
 982         {
 983                 .slave_reg_ofs  = 0x308,
 984                 .sliver_reg_ofs = 0xdc0,
 985                 .phy_addr       = 2,
 986         },
 987 };
 988
 989 static struct cpsw_platform_data cpsw_data = {
 990         .mdio_base              = CPSW_MDIO_BASE,
 991         .cpsw_base              = CPSW_BASE,
 992         .mdio_div               = 0xff,
 993         .channels               = 8,
 994         .cpdma_reg_ofs          = 0x800,
 995         .slaves                 = 1,
 996         .slave_data             = cpsw_slaves,
 997         .ale_reg_ofs            = 0xd00,
 998         .ale_entries            = 1024,
 999         .host_port_reg_ofs      = 0x108,
1000         .hw_stats_reg_ofs       = 0x900,
1001         .bd_ram_ofs             = 0x2000,
1002         .mac_control            = (1 << 5),
1003         .control                = cpsw_control,
1004         .host_port_num          = 0,
1005         .version                = CPSW_CTRL_VERSION_2,
1006 };
1007
1008 static u64 mac_to_u64(u8 mac[6])
1009 {
1010         int i;
1011         u64 addr = 0;
1012
1013         for (i = 0; i < 6; i++) {
1014                 addr <<= 8;
1015                 addr |= mac[i];
1016         }
1017
1018         return addr;
1019 }
1020
1021 static void u64_to_mac(u64 addr, u8 mac[6])
1022 {
1023         mac[5] = addr;
1024         mac[4] = addr >> 8;
1025         mac[3] = addr >> 16;
1026         mac[2] = addr >> 24;
1027         mac[1] = addr >> 32;
1028         mac[0] = addr >> 40;
1029 }
1030
1031 int board_eth_init(struct bd_info *bis)
1032 {
1033         int ret;
1034         uint8_t mac_addr[6];
1035         uint32_t mac_hi, mac_lo;
1036         uint32_t ctrl_val;
1037         int i;
1038         u64 mac1, mac2;
1039         u8 mac_addr1[6], mac_addr2[6];
1040         int num_macs;
1041
1042         /* try reading mac address from efuse */
1043         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1044         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1045         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1046         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1047         mac_addr[2] = mac_hi & 0xFF;
1048         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1049         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1050         mac_addr[5] = mac_lo & 0xFF;
1051
1052         if (!env_get("ethaddr")) {
1053                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1054
1055                 if (is_valid_ethaddr(mac_addr))
1056                         eth_env_set_enetaddr("ethaddr", mac_addr);
1057         }
1058
1059         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1060         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1061         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1062         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1063         mac_addr[2] = mac_hi & 0xFF;
1064         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1065         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1066         mac_addr[5] = mac_lo & 0xFF;
1067
1068         if (!env_get("eth1addr")) {
1069                 if (is_valid_ethaddr(mac_addr))
1070                         eth_env_set_enetaddr("eth1addr", mac_addr);
1071         }
1072
1073         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1074         ctrl_val |= 0x22;
1075         writel(ctrl_val, (*ctrl)->control_core_control_io1);
1076
1077         /* The phy address for the AM57xx IDK are different than x15 */
1078         if (board_is_am572x_idk() || board_is_am571x_idk() ||
1079             board_is_am574x_idk()) {
1080                 cpsw_data.slave_data[0].phy_addr = 0;
1081                 cpsw_data.slave_data[1].phy_addr = 1;
1082         }
1083
1084         ret = cpsw_register(&cpsw_data);
1085         if (ret < 0)
1086                 printf("Error %d registering CPSW switch\n", ret);
1087
1088         /*
1089          * Export any Ethernet MAC addresses from EEPROM.
1090          * On AM57xx the 2 MAC addresses define the address range
1091          */
1092         board_ti_get_eth_mac_addr(0, mac_addr1);
1093         board_ti_get_eth_mac_addr(1, mac_addr2);
1094
1095         if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1096                 mac1 = mac_to_u64(mac_addr1);
1097                 mac2 = mac_to_u64(mac_addr2);
1098
1099                 /* must contain an address range */
1100                 num_macs = mac2 - mac1 + 1;
1101                 /* <= 50 to protect against user programming error */
1102                 if (num_macs > 0 && num_macs <= 50) {
1103                         for (i = 0; i < num_macs; i++) {
1104                                 u64_to_mac(mac1 + i, mac_addr);
1105                                 if (is_valid_ethaddr(mac_addr)) {
1106                                         eth_env_set_enetaddr_by_index("eth",
1107                                                                       i + 2,
1108                                                                       mac_addr);
1109                                 }
1110                         }
1111                 }
1112         }
1113
1114         return ret;
1115 }
1116 #endif
1117
1118 #ifdef CONFIG_BOARD_EARLY_INIT_F
1119 /* VTT regulator enable */
1120 static inline void vtt_regulator_enable(void)
1121 {
1122         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1123                 return;
1124
1125         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1126         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1127 }
1128
1129 int board_early_init_f(void)
1130 {
1131         vtt_regulator_enable();
1132         return 0;
1133 }
1134 #endif
1135
1136 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1137 int ft_board_setup(void *blob, struct bd_info *bd)
1138 {
1139         ft_cpu_setup(blob, bd);
1140
1141         return 0;
1142 }
1143 #endif
1144
1145 #ifdef CONFIG_SPL_LOAD_FIT
1146 int board_fit_config_name_match(const char *name)
1147 {
1148         if (board_is_x15()) {
1149                 if (board_is_x15_revb1()) {
1150                         if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1151                                 return 0;
1152                 } else if (board_is_x15_revc()) {
1153                         if (!strcmp(name, "am57xx-beagle-x15-revc"))
1154                                 return 0;
1155                 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1156                         return 0;
1157                 }
1158         } else if (board_is_am572x_evm() &&
1159                    !strcmp(name, "am57xx-beagle-x15")) {
1160                 return 0;
1161         } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1162                 return 0;
1163         } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1164                 return 0;
1165         } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1166                 return 0;
1167         } else if (board_is_bbai() && !strcmp(name, "am5729-beagleboneai")) {
1168                 return 0;
1169         }
1170
1171         return -1;
1172 }
1173 #endif
1174
1175 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1176 int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
1177 {
1178         if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
1179                 return -ENOTSUPP;
1180
1181         printf("Setting reboot to fastboot flag ...\n");
1182         env_set("dofastboot", "1");
1183         env_save();
1184         return 0;
1185 }
1186 #endif
1187
1188 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1189 static int board_bootmode_has_emmc(void)
1190 {
1191         /* Check that boot mode is same as BBAI */
1192         if (gd->arch.omap_boot_mode != 2)
1193                 return -EIO;
1194
1195         return 0;
1196 }
1197 #endif