drivers/clk/clk_rk3288.c

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <syscon.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/cru_rk3288.h>
  15 #include <asm/arch/grf_rk3288.h>
  16 #include <asm/arch/hardware.h>
  17 #include <dt-bindings/clock/rk3288-cru.h>
  18 #include <dm/device-internal.h>
  19 #include <dm/lists.h>
  20 #include <dm/uclass-internal.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 struct rk3288_clk_plat {
  25         enum rk_clk_id clk_id;
  26 };
  27
  28 struct rk3288_clk_priv {
  29         struct rk3288_grf *grf;
  30         struct rk3288_cru *cru;
  31         ulong rate;
  32 };
  33
  34 struct pll_div {
  35         u32 nr;
  36         u32 nf;
  37         u32 no;
  38 };
  39
  40 enum {
  41         VCO_MAX_HZ      = 2200U * 1000000,
  42         VCO_MIN_HZ      = 440 * 1000000,
  43         OUTPUT_MAX_HZ   = 2200U * 1000000,
  44         OUTPUT_MIN_HZ   = 27500000,
  45         FREF_MAX_HZ     = 2200U * 1000000,
  46         FREF_MIN_HZ     = 269 * 1000000,
  47 };
  48
  49 enum {
  50         /* PLL CON0 */
  51         PLL_OD_MASK             = 0x0f,
  52
  53         /* PLL CON1 */
  54         PLL_NF_MASK             = 0x1fff,
  55
  56         /* PLL CON2 */
  57         PLL_BWADJ_MASK          = 0x0fff,
  58
  59         /* PLL CON3 */
  60         PLL_RESET_SHIFT         = 5,
  61
  62         /* CLKSEL0 */
  63         CORE_SEL_PLL_MASK       = 1,
  64         CORE_SEL_PLL_SHIFT      = 15,
  65         A17_DIV_MASK            = 0x1f,
  66         A17_DIV_SHIFT           = 8,
  67         MP_DIV_MASK             = 0xf,
  68         MP_DIV_SHIFT            = 4,
  69         M0_DIV_MASK             = 0xf,
  70         M0_DIV_SHIFT            = 0,
  71
  72         /* CLKSEL1: pd bus clk pll sel: codec or general */
  73         PD_BUS_SEL_PLL_MASK     = 15,
  74         PD_BUS_SEL_CPLL         = 0,
  75         PD_BUS_SEL_GPLL,
  76
  77         /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
  78         PD_BUS_PCLK_DIV_SHIFT   = 12,
  79         PD_BUS_PCLK_DIV_MASK    = 7,
  80
  81         /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  82         PD_BUS_HCLK_DIV_SHIFT   = 8,
  83         PD_BUS_HCLK_DIV_MASK    = 3,
  84
  85         /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
  86         PD_BUS_ACLK_DIV0_SHIFT  = 3,
  87         PD_BUS_ACLK_DIV0_MASK   = 0x1f,
  88         PD_BUS_ACLK_DIV1_SHIFT  = 0,
  89         PD_BUS_ACLK_DIV1_MASK   = 0x7,
  90
  91         /*
  92          * CLKSEL10
  93          * peripheral bus pclk div:
  94          * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
  95          */
  96         PERI_SEL_PLL_MASK        = 1,
  97         PERI_SEL_PLL_SHIFT       = 15,
  98         PERI_SEL_CPLL           = 0,
  99         PERI_SEL_GPLL,
 100
 101         PERI_PCLK_DIV_SHIFT     = 12,
 102         PERI_PCLK_DIV_MASK      = 3,
 103
 104         /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
 105         PERI_HCLK_DIV_SHIFT     = 8,
 106         PERI_HCLK_DIV_MASK      = 3,
 107
 108         /*
 109          * peripheral bus aclk div:
 110          *    aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
 111          */
 112         PERI_ACLK_DIV_SHIFT     = 0,
 113         PERI_ACLK_DIV_MASK      = 0x1f,
 114
 115         SOCSTS_DPLL_LOCK        = 1 << 5,
 116         SOCSTS_APLL_LOCK        = 1 << 6,
 117         SOCSTS_CPLL_LOCK        = 1 << 7,
 118         SOCSTS_GPLL_LOCK        = 1 << 8,
 119         SOCSTS_NPLL_LOCK        = 1 << 9,
 120 };
 121
 122 #define RATE_TO_DIV(input_rate, output_rate) \
 123         ((input_rate) / (output_rate) - 1);
 124
 125 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 126
 127 #define PLL_DIVISORS(hz, _nr, _no) {\
 128         .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
 129         _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
 130                        (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
 131                        "divisors on line " __stringify(__LINE__));
 132
 133 /* Keep divisors as low as possible to reduce jitter and power usage */
 134 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
 135 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 136 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 137
 138 int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp)
 139 {
 140         struct udevice *dev;
 141
 142         for (uclass_find_first_device(UCLASS_CLK, &dev);
 143              dev;
 144              uclass_find_next_device(&dev)) {
 145                 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 146
 147                 if (plat->clk_id == clk_id) {
 148                         *devp = dev;
 149                         return device_probe(dev);
 150                 }
 151         }
 152
 153         return -ENODEV;
 154 }
 155
 156 void *rockchip_get_cru(void)
 157 {
 158         struct rk3288_clk_priv *priv;
 159         struct udevice *dev;
 160         int ret;
 161
 162         ret = rkclk_get_clk(CLK_GENERAL, &dev);
 163         if (ret)
 164                 return ERR_PTR(ret);
 165         priv = dev_get_priv(dev);
 166         return priv->cru;
 167 }
 168
 169 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 170                          const struct pll_div *div)
 171 {
 172         int pll_id = rk_pll_id(clk_id);
 173         struct rk3288_pll *pll = &cru->pll[pll_id];
 174         /* All PLLs have same VCO and output frequency range restrictions. */
 175         uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
 176         uint output_hz = vco_hz / div->no;
 177
 178         debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
 179               (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
 180         assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
 181                output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
 182                (div->no == 1 || !(div->no % 2)));
 183
 184         /* enter reset */
 185         rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 186
 187         rk_clrsetreg(&pll->con0,
 188                      CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
 189                      ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 190         rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 191         rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
 192
 193         udelay(10);
 194
 195         /* return from reset */
 196         rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 197
 198         return 0;
 199 }
 200
 201 static inline unsigned int log2(unsigned int value)
 202 {
 203         return fls(value) - 1;
 204 }
 205
 206 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
 207                                unsigned int hz)
 208 {
 209         static const struct pll_div dpll_cfg[] = {
 210                 {.nf = 25, .nr = 2, .no = 1},
 211                 {.nf = 400, .nr = 9, .no = 2},
 212                 {.nf = 500, .nr = 9, .no = 2},
 213                 {.nf = 100, .nr = 3, .no = 1},
 214         };
 215         int cfg;
 216
 217         switch (hz) {
 218         case 300000000:
 219                 cfg = 0;
 220                 break;
 221         case 533000000: /* actually 533.3P MHz */
 222                 cfg = 1;
 223                 break;
 224         case 666000000: /* actually 666.6P MHz */
 225                 cfg = 2;
 226                 break;
 227         case 800000000:
 228                 cfg = 3;
 229                 break;
 230         default:
 231                 debug("Unsupported SDRAM frequency");
 232                 return -EINVAL;
 233         }
 234
 235         /* pll enter slow-mode */
 236         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 237                      DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 238
 239         rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
 240
 241         /* wait for pll lock */
 242         while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
 243                 udelay(1);
 244
 245         /* PLL enter normal-mode */
 246         rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
 247                      DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 248
 249         return 0;
 250 }
 251
 252 #ifndef CONFIG_SPL_BUILD
 253 #define VCO_MAX_KHZ     2200000
 254 #define VCO_MIN_KHZ     440000
 255 #define FREF_MAX_KHZ    2200000
 256 #define FREF_MIN_KHZ    269
 257
 258 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
 259 {
 260         uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
 261         uint fref_khz;
 262         uint diff_khz, best_diff_khz;
 263         const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
 264         uint vco_khz;
 265         uint no = 1;
 266         uint freq_khz = freq_hz / 1000;
 267
 268         if (!freq_hz) {
 269                 printf("%s: the frequency can not be 0 Hz\n", __func__);
 270                 return -EINVAL;
 271         }
 272
 273         no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
 274         if (ext_div) {
 275                 *ext_div = DIV_ROUND_UP(no, max_no);
 276                 no = DIV_ROUND_UP(no, *ext_div);
 277         }
 278
 279         /* only even divisors (and 1) are supported */
 280         if (no > 1)
 281                 no = DIV_ROUND_UP(no, 2) * 2;
 282
 283         vco_khz = freq_khz * no;
 284         if (ext_div)
 285                 vco_khz *= *ext_div;
 286
 287         if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
 288                 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
 289                        __func__, freq_hz);
 290                 return -1;
 291         }
 292
 293         div->no = no;
 294
 295         best_diff_khz = vco_khz;
 296         for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
 297                 fref_khz = ref_khz / nr;
 298                 if (fref_khz < FREF_MIN_KHZ)
 299                         break;
 300                 if (fref_khz > FREF_MAX_KHZ)
 301                         continue;
 302
 303                 nf = vco_khz / fref_khz;
 304                 if (nf >= max_nf)
 305                         continue;
 306                 diff_khz = vco_khz - nf * fref_khz;
 307                 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
 308                         nf++;
 309                         diff_khz = fref_khz - diff_khz;
 310                 }
 311
 312                 if (diff_khz >= best_diff_khz)
 313                         continue;
 314
 315                 best_diff_khz = diff_khz;
 316                 div->nr = nr;
 317                 div->nf = nf;
 318         }
 319
 320         if (best_diff_khz > 4 * 1000) {
 321                 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
 322                        __func__, freq_hz, best_diff_khz * 1000);
 323                 return -EINVAL;
 324         }
 325
 326         return 0;
 327 }
 328
 329 static int rockchip_mac_set_clk(struct rk3288_cru *cru,
 330                                   int periph, uint freq)
 331 {
 332         /* Assuming mac_clk is fed by an external clock */
 333         rk_clrsetreg(&cru->cru_clksel_con[21],
 334                      RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
 335                      RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
 336
 337          return 0;
 338 }
 339
 340 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
 341                                 int periph, unsigned int rate_hz)
 342 {
 343         struct pll_div npll_config = {0};
 344         u32 lcdc_div;
 345         int ret;
 346
 347         ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
 348         if (ret)
 349                 return ret;
 350
 351         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
 352                      NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
 353         rkclk_set_pll(cru, CLK_NEW, &npll_config);
 354
 355         /* waiting for pll lock */
 356         while (1) {
 357                 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
 358                         break;
 359                 udelay(1);
 360         }
 361
 362         rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
 363                      NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
 364
 365         /* vop dclk source clk: npll,dclk_div: 1 */
 366         switch (periph) {
 367         case DCLK_VOP0:
 368                 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
 369                              (lcdc_div - 1) << 8 | 2 << 0);
 370                 break;
 371         case DCLK_VOP1:
 372                 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
 373                              (lcdc_div - 1) << 8 | 2 << 6);
 374                 break;
 375         }
 376
 377         return 0;
 378 }
 379 #endif
 380
 381 #ifdef CONFIG_SPL_BUILD
 382 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 383 {
 384         u32 aclk_div;
 385         u32 hclk_div;
 386         u32 pclk_div;
 387
 388         /* pll enter slow-mode */
 389         rk_clrsetreg(&cru->cru_mode_con,
 390                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 391                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 392                      GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 393                      CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 394
 395         /* init pll */
 396         rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
 397         rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
 398
 399         /* waiting for pll lock */
 400         while ((readl(&grf->soc_status[1]) &
 401                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
 402                         (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
 403                 udelay(1);
 404
 405         /*
 406          * pd_bus clock pll source selection and
 407          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 408          */
 409         aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
 410         assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 411         hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
 412         assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
 413                 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
 414
 415         pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
 416         assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
 417                 PD_BUS_ACLK_HZ && pclk_div < 0x7);
 418
 419         rk_clrsetreg(&cru->cru_clksel_con[1],
 420                      PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
 421                      PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
 422                      PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
 423                      PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
 424                      pclk_div << PD_BUS_PCLK_DIV_SHIFT |
 425                      hclk_div << PD_BUS_HCLK_DIV_SHIFT |
 426                      aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
 427                      0 << 0);
 428
 429         /*
 430          * peri clock pll source selection and
 431          * set up dependent divisors for PCLK/HCLK and ACLK clocks.
 432          */
 433         aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
 434         assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
 435
 436         hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
 437         assert((1 << hclk_div) * PERI_HCLK_HZ ==
 438                 PERI_ACLK_HZ && (hclk_div < 0x4));
 439
 440         pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
 441         assert((1 << pclk_div) * PERI_PCLK_HZ ==
 442                 PERI_ACLK_HZ && (pclk_div < 0x4));
 443
 444         rk_clrsetreg(&cru->cru_clksel_con[10],
 445                      PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
 446                      PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
 447                      PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
 448                      PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
 449                      pclk_div << PERI_PCLK_DIV_SHIFT |
 450                      hclk_div << PERI_HCLK_DIV_SHIFT |
 451                      aclk_div << PERI_ACLK_DIV_SHIFT);
 452
 453         /* PLL enter normal-mode */
 454         rk_clrsetreg(&cru->cru_mode_con,
 455                      GPLL_MODE_MASK << GPLL_MODE_SHIFT |
 456                      CPLL_MODE_MASK << CPLL_MODE_SHIFT,
 457                      GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 458                      CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 459 }
 460 #endif
 461
 462 void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
 463 {
 464         /* pll enter slow-mode */
 465         rk_clrsetreg(&cru->cru_mode_con,
 466                      APLL_MODE_MASK << APLL_MODE_SHIFT,
 467                      APLL_MODE_SLOW << APLL_MODE_SHIFT);
 468
 469         rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
 470
 471         /* waiting for pll lock */
 472         while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
 473                 udelay(1);
 474
 475         /*
 476          * core clock pll source selection and
 477          * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
 478          * core clock select apll, apll clk = 1800MHz
 479          * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
 480          */
 481         rk_clrsetreg(&cru->cru_clksel_con[0],
 482                      CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT |
 483                      A17_DIV_MASK << A17_DIV_SHIFT |
 484                      MP_DIV_MASK << MP_DIV_SHIFT |
 485                      M0_DIV_MASK << M0_DIV_SHIFT,
 486                      0 << A17_DIV_SHIFT |
 487                      3 << MP_DIV_SHIFT |
 488                      1 << M0_DIV_SHIFT);
 489
 490         /*
 491          * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
 492          * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
 493          */
 494         rk_clrsetreg(&cru->cru_clksel_con[37],
 495                      CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT |
 496                      ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT |
 497                      PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT,
 498                      1 << CLK_L2RAM_DIV_SHIFT |
 499                      3 << ATCLK_CORE_DIV_CON_SHIFT |
 500                      3 << PCLK_CORE_DBG_DIV_SHIFT);
 501
 502         /* PLL enter normal-mode */
 503         rk_clrsetreg(&cru->cru_mode_con,
 504                      APLL_MODE_MASK << APLL_MODE_SHIFT,
 505                      APLL_MODE_NORMAL << APLL_MODE_SHIFT);
 506 }
 507
 508 /* Get pll rate by id */
 509 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
 510                                    enum rk_clk_id clk_id)
 511 {
 512         uint32_t nr, no, nf;
 513         uint32_t con;
 514         int pll_id = rk_pll_id(clk_id);
 515         struct rk3288_pll *pll = &cru->pll[pll_id];
 516         static u8 clk_shift[CLK_COUNT] = {
 517                 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
 518                 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
 519         };
 520         uint shift;
 521
 522         con = readl(&cru->cru_mode_con);
 523         shift = clk_shift[clk_id];
 524         switch ((con >> shift) & APLL_MODE_MASK) {
 525         case APLL_MODE_SLOW:
 526                 return OSC_HZ;
 527         case APLL_MODE_NORMAL:
 528                 /* normal mode */
 529                 con = readl(&pll->con0);
 530                 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
 531                 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
 532                 con = readl(&pll->con1);
 533                 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
 534
 535                 return (24 * nf / (nr * no)) * 1000000;
 536         case APLL_MODE_DEEP:
 537         default:
 538                 return 32768;
 539         }
 540 }
 541
 542 static ulong rk3288_clk_get_rate(struct udevice *dev)
 543 {
 544         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 545         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 546
 547         debug("%s\n", dev->name);
 548         return rkclk_pll_get_rate(priv->cru, plat->clk_id);
 549 }
 550
 551 static ulong rk3288_clk_set_rate(struct udevice *dev, ulong rate)
 552 {
 553         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 554         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 555
 556         debug("%s\n", dev->name);
 557         switch (plat->clk_id) {
 558         case CLK_DDR:
 559                 rkclk_configure_ddr(priv->cru, priv->grf, rate);
 560                 break;
 561         default:
 562                 return -ENOENT;
 563         }
 564
 565         return 0;
 566 }
 567
 568 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 569                                   int periph)
 570 {
 571         uint src_rate;
 572         uint div, mux;
 573         u32 con;
 574
 575         switch (periph) {
 576         case HCLK_EMMC:
 577                 con = readl(&cru->cru_clksel_con[12]);
 578                 mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
 579                 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
 580                 break;
 581         case HCLK_SDMMC:
 582                 con = readl(&cru->cru_clksel_con[11]);
 583                 mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
 584                 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
 585                 break;
 586         case HCLK_SDIO0:
 587                 con = readl(&cru->cru_clksel_con[12]);
 588                 mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
 589                 div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
 590                 break;
 591         default:
 592                 return -EINVAL;
 593         }
 594
 595         src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
 596         return DIV_TO_RATE(src_rate, div);
 597 }
 598
 599 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 600                                   int  periph, uint freq)
 601 {
 602         int src_clk_div;
 603         int mux;
 604
 605         debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
 606         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 607
 608         if (src_clk_div > 0x3f) {
 609                 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
 610                 mux = EMMC_PLL_SELECT_24MHZ;
 611                 assert((int)EMMC_PLL_SELECT_24MHZ ==
 612                        (int)MMC0_PLL_SELECT_24MHZ);
 613         } else {
 614                 mux = EMMC_PLL_SELECT_GENERAL;
 615                 assert((int)EMMC_PLL_SELECT_GENERAL ==
 616                        (int)MMC0_PLL_SELECT_GENERAL);
 617         }
 618         switch (periph) {
 619         case HCLK_EMMC:
 620                 rk_clrsetreg(&cru->cru_clksel_con[12],
 621                              EMMC_PLL_MASK << EMMC_PLL_SHIFT |
 622                              EMMC_DIV_MASK << EMMC_DIV_SHIFT,
 623                              mux << EMMC_PLL_SHIFT |
 624                              (src_clk_div - 1) << EMMC_DIV_SHIFT);
 625                 break;
 626         case HCLK_SDMMC:
 627                 rk_clrsetreg(&cru->cru_clksel_con[11],
 628                              MMC0_PLL_MASK << MMC0_PLL_SHIFT |
 629                              MMC0_DIV_MASK << MMC0_DIV_SHIFT,
 630                              mux << MMC0_PLL_SHIFT |
 631                              (src_clk_div - 1) << MMC0_DIV_SHIFT);
 632                 break;
 633         case HCLK_SDIO0:
 634                 rk_clrsetreg(&cru->cru_clksel_con[12],
 635                              SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
 636                              SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
 637                              mux << SDIO0_PLL_SHIFT |
 638                              (src_clk_div - 1) << SDIO0_DIV_SHIFT);
 639                 break;
 640         default:
 641                 return -EINVAL;
 642         }
 643
 644         return rockchip_mmc_get_clk(cru, gclk_rate, periph);
 645 }
 646
 647 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 648                                   int periph)
 649 {
 650         uint div, mux;
 651         u32 con;
 652
 653         switch (periph) {
 654         case SCLK_SPI0:
 655                 con = readl(&cru->cru_clksel_con[25]);
 656                 mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
 657                 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
 658                 break;
 659         case SCLK_SPI1:
 660                 con = readl(&cru->cru_clksel_con[25]);
 661                 mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
 662                 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
 663                 break;
 664         case SCLK_SPI2:
 665                 con = readl(&cru->cru_clksel_con[39]);
 666                 mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
 667                 div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
 668                 break;
 669         default:
 670                 return -EINVAL;
 671         }
 672         assert(mux == SPI0_PLL_SELECT_GENERAL);
 673
 674         return DIV_TO_RATE(gclk_rate, div);
 675 }
 676
 677 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 678                                   int periph, uint freq)
 679 {
 680         int src_clk_div;
 681
 682         debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
 683         src_clk_div = RATE_TO_DIV(gclk_rate, freq);
 684         switch (periph) {
 685         case SCLK_SPI0:
 686                 rk_clrsetreg(&cru->cru_clksel_con[25],
 687                              SPI0_PLL_MASK << SPI0_PLL_SHIFT |
 688                              SPI0_DIV_MASK << SPI0_DIV_SHIFT,
 689                              SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
 690                              src_clk_div << SPI0_DIV_SHIFT);
 691                 break;
 692         case SCLK_SPI1:
 693                 rk_clrsetreg(&cru->cru_clksel_con[25],
 694                              SPI1_PLL_MASK << SPI1_PLL_SHIFT |
 695                              SPI1_DIV_MASK << SPI1_DIV_SHIFT,
 696                              SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
 697                              src_clk_div << SPI1_DIV_SHIFT);
 698                 break;
 699         case SCLK_SPI2:
 700                 rk_clrsetreg(&cru->cru_clksel_con[39],
 701                              SPI2_PLL_MASK << SPI2_PLL_SHIFT |
 702                              SPI2_DIV_MASK << SPI2_DIV_SHIFT,
 703                              SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
 704                              src_clk_div << SPI2_DIV_SHIFT);
 705                 break;
 706         default:
 707                 return -EINVAL;
 708         }
 709
 710         return rockchip_spi_get_clk(cru, gclk_rate, periph);
 711 }
 712
 713 static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
 714 {
 715         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 716         struct udevice *gclk;
 717         ulong new_rate, gclk_rate;
 718         int ret;
 719
 720         ret = rkclk_get_clk(CLK_GENERAL, &gclk);
 721         if (ret)
 722                 return ret;
 723         gclk_rate = clk_get_rate(gclk);
 724         switch (periph) {
 725         case HCLK_EMMC:
 726         case HCLK_SDMMC:
 727         case HCLK_SDIO0:
 728                 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph);
 729                 break;
 730         case SCLK_SPI0:
 731         case SCLK_SPI1:
 732         case SCLK_SPI2:
 733                 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, periph);
 734                 break;
 735         case PCLK_I2C0:
 736         case PCLK_I2C1:
 737         case PCLK_I2C2:
 738         case PCLK_I2C3:
 739         case PCLK_I2C4:
 740         case PCLK_I2C5:
 741                 return gclk_rate;
 742         default:
 743                 return -ENOENT;
 744         }
 745
 746         return new_rate;
 747 }
 748
 749 static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 750 {
 751         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 752         struct rk3288_cru *cru = priv->cru;
 753         struct udevice *gclk;
 754         ulong new_rate, gclk_rate;
 755         int ret;
 756
 757         ret = rkclk_get_clk(CLK_GENERAL, &gclk);
 758         if (ret)
 759                 return ret;
 760         gclk_rate = clk_get_rate(gclk);
 761         switch (periph) {
 762         case HCLK_EMMC:
 763         case HCLK_SDMMC:
 764         case HCLK_SDIO0:
 765                 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, periph, rate);
 766                 break;
 767         case SCLK_SPI0:
 768         case SCLK_SPI1:
 769         case SCLK_SPI2:
 770                 new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate);
 771                 break;
 772 #ifndef CONFIG_SPL_BUILD
 773         case SCLK_MAC:
 774                 new_rate = rockchip_mac_set_clk(priv->cru, periph, rate);
 775                 break;
 776         case DCLK_VOP0:
 777         case DCLK_VOP1:
 778                 new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate);
 779                 break;
 780         case SCLK_EDP_24M:
 781                 /* clk_edp_24M source: 24M */
 782                 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
 783
 784                 /* rst edp */
 785                 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
 786                 udelay(1);
 787                 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
 788                 new_rate = rate;
 789                 break;
 790         case ACLK_VOP0:
 791         case ACLK_VOP1: {
 792                 u32 div;
 793
 794                 /* vop aclk source clk: cpll */
 795                 div = CPLL_HZ / rate;
 796                 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
 797
 798                 switch (periph) {
 799                 case ACLK_VOP0:
 800                         rk_clrsetreg(&cru->cru_clksel_con[31],
 801                                      3 << 6 | 0x1f << 0,
 802                                      0 << 6 | (div - 1) << 0);
 803                         break;
 804                 case ACLK_VOP1:
 805                         rk_clrsetreg(&cru->cru_clksel_con[31],
 806                                      3 << 14 | 0x1f << 8,
 807                                      0 << 14 | (div - 1) << 8);
 808                         break;
 809                 }
 810                 new_rate = rate;
 811                 break;
 812         }
 813         case PCLK_HDMI_CTRL:
 814                 /* enable pclk hdmi ctrl */
 815                 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
 816
 817                 /* software reset hdmi */
 818                 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
 819                 udelay(1);
 820                 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
 821                 new_rate = rate;
 822                 break;
 823 #endif
 824         default:
 825                 return -ENOENT;
 826         }
 827
 828         return new_rate;
 829 }
 830
 831 static struct clk_ops rk3288_clk_ops = {
 832         .get_rate       = rk3288_clk_get_rate,
 833         .set_rate       = rk3288_clk_set_rate,
 834         .set_periph_rate = rk3288_set_periph_rate,
 835         .get_periph_rate = rk3288_get_periph_rate,
 836 };
 837
 838 static int rk3288_clk_probe(struct udevice *dev)
 839 {
 840         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 841         struct rk3288_clk_priv *priv = dev_get_priv(dev);
 842
 843         if (plat->clk_id != CLK_OSC) {
 844                 struct rk3288_clk_priv *parent_priv = dev_get_priv(dev->parent);
 845
 846                 priv->cru = parent_priv->cru;
 847                 priv->grf = parent_priv->grf;
 848                 return 0;
 849         }
 850         priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
 851         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 852 #ifdef CONFIG_SPL_BUILD
 853         rkclk_init(priv->cru, priv->grf);
 854 #endif
 855
 856         return 0;
 857 }
 858
 859 static const char *const clk_name[CLK_COUNT] = {
 860         "osc",
 861         "apll",
 862         "dpll",
 863         "cpll",
 864         "gpll",
 865         "npll",
 866 };
 867
 868 static int rk3288_clk_bind(struct udevice *dev)
 869 {
 870         struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 871         int pll, ret;
 872
 873         /* We only need to set up the root clock */
 874         if (dev->of_offset == -1) {
 875                 plat->clk_id = CLK_OSC;
 876                 return 0;
 877         }
 878
 879         /* Create devices for P main clocks */
 880         for (pll = 1; pll < CLK_COUNT; pll++) {
 881                 struct udevice *child;
 882                 struct rk3288_clk_plat *cplat;
 883
 884                 debug("%s %s\n", __func__, clk_name[pll]);
 885                 ret = device_bind_driver(dev, "clk_rk3288", clk_name[pll],
 886                                          &child);
 887                 if (ret)
 888                         return ret;
 889                 cplat = dev_get_platdata(child);
 890                 cplat->clk_id = pll;
 891         }
 892
 893         /* The reset driver does not have a device node, so bind it here */
 894         ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev);
 895         if (ret)
 896                 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
 897
 898         return 0;
 899 }
 900
 901 static const struct udevice_id rk3288_clk_ids[] = {
 902         { .compatible = "rockchip,rk3288-cru" },
 903         { }
 904 };
 905
 906 U_BOOT_DRIVER(clk_rk3288) = {
 907         .name           = "clk_rk3288",
 908         .id             = UCLASS_CLK,
 909         .of_match       = rk3288_clk_ids,
 910         .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
 911         .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
 912         .ops            = &rk3288_clk_ops,
 913         .bind           = rk3288_clk_bind,
 914         .probe          = rk3288_clk_probe,
 915 };