arch/arm/mach-imx/mx7/clock.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   4  *
   5  * Author:
   6  *      Peng Fan <[email protected]>
   7  */
   8
   9 #include <common.h>
  10 #include <clock_legacy.h>
  11 #include <command.h>
  12 #include <div64.h>
  13 #include <asm/io.h>
  14 #include <linux/errno.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/sys_proto.h>
  19
  20 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
  21                                          ANATOP_BASE_ADDR;
  22 struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  23
  24 #ifdef CONFIG_FSL_ESDHC_IMX
  25 DECLARE_GLOBAL_DATA_PTR;
  26 #endif
  27
  28 int get_clocks(void)
  29 {
  30 #ifdef CONFIG_FSL_ESDHC_IMX
  31 #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
  32         gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  33 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
  34         gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  35 #else
  36         gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  37 #endif
  38 #endif
  39         return 0;
  40 }
  41
  42 u32 get_ahb_clk(void)
  43 {
  44         return get_root_clk(AHB_CLK_ROOT);
  45 }
  46
  47 static u32 get_ipg_clk(void)
  48 {
  49         /*
  50          * The AHB and IPG are fixed at 2:1 ratio, and synchronized to
  51          * each other.
  52          */
  53         return get_ahb_clk() / 2;
  54 }
  55
  56 u32 imx_get_uartclk(void)
  57 {
  58         return get_root_clk(UART_CLK_ROOT);
  59 }
  60
  61 u32 imx_get_fecclk(void)
  62 {
  63         return get_root_clk(ENET_AXI_CLK_ROOT);
  64 }
  65
  66 #ifdef CONFIG_MXC_OCOTP
  67 void enable_ocotp_clk(unsigned char enable)
  68 {
  69         clock_enable(CCGR_OCOTP, enable);
  70 }
  71
  72 void enable_thermal_clk(void)
  73 {
  74         enable_ocotp_clk(1);
  75 }
  76 #endif
  77
  78 void enable_usboh3_clk(unsigned char enable)
  79 {
  80         u32 target;
  81
  82         if (enable) {
  83                 /* disable the clock gate first */
  84                 clock_enable(CCGR_USB_HSIC, 0);
  85
  86                 /* 120Mhz */
  87                 target = CLK_ROOT_ON |
  88                          USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
  89                          CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  90                          CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  91                 clock_set_target_val(USB_HSIC_CLK_ROOT, target);
  92
  93                 /* enable the clock gate */
  94                 clock_enable(CCGR_USB_CTRL, 1);
  95                 clock_enable(CCGR_USB_HSIC, 1);
  96                 clock_enable(CCGR_USB_PHY1, 1);
  97                 clock_enable(CCGR_USB_PHY2, 1);
  98         } else {
  99                 clock_enable(CCGR_USB_CTRL, 0);
 100                 clock_enable(CCGR_USB_HSIC, 0);
 101                 clock_enable(CCGR_USB_PHY1, 0);
 102                 clock_enable(CCGR_USB_PHY2, 0);
 103         }
 104 }
 105
 106 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 107 {
 108         u32 reg, div_sel;
 109         u32 num, denom;
 110
 111         /*
 112          * Alought there are four choices for the bypass src,
 113          * we choose OSC_24M which is the default set in ROM.
 114          */
 115         switch (pll) {
 116         case PLL_CORE:
 117                 reg = readl(&ccm_anatop->pll_arm);
 118
 119                 if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
 120                         return 0;
 121
 122                 if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
 123                         return MXC_HCLK;
 124
 125                 div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
 126                            CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
 127
 128                 return (infreq * div_sel) / 2;
 129
 130         case PLL_SYS:
 131                 reg = readl(&ccm_anatop->pll_480);
 132
 133                 if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
 134                         return 0;
 135
 136                 if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
 137                         return MXC_HCLK;
 138
 139                 if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
 140                         CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
 141                         return 480000000u;
 142                 else
 143                         return 528000000u;
 144
 145         case PLL_ENET:
 146                 reg = readl(&ccm_anatop->pll_enet);
 147
 148                 if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
 149                         return 0;
 150
 151                 if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
 152                         return MXC_HCLK;
 153
 154                 return 1000000000u;
 155
 156         case PLL_DDR:
 157                 reg = readl(&ccm_anatop->pll_ddr);
 158
 159                 if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
 160                         return 0;
 161
 162                 num = ccm_anatop->pll_ddr_num;
 163                 denom = ccm_anatop->pll_ddr_denom;
 164
 165                 if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
 166                         return MXC_HCLK;
 167
 168                 div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
 169                            CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
 170
 171                 return infreq * (div_sel + num / denom);
 172
 173         case PLL_USB:
 174                 return 480000000u;
 175
 176         default:
 177                 printf("Unsupported pll clocks %d\n", pll);
 178                 break;
 179         }
 180
 181         return 0;
 182 }
 183
 184 static u32 mxc_get_pll_sys_derive(int derive)
 185 {
 186         u32 freq, div, frac;
 187         u32 reg;
 188
 189         div = 1;
 190         reg = readl(&ccm_anatop->pll_480);
 191         freq = decode_pll(PLL_SYS, MXC_HCLK);
 192
 193         switch (derive) {
 194         case PLL_SYS_MAIN_480M_CLK:
 195                 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
 196                         return 0;
 197                 else
 198                         return freq;
 199         case PLL_SYS_MAIN_240M_CLK:
 200                 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
 201                         return 0;
 202                 else
 203                         return freq / 2;
 204         case PLL_SYS_MAIN_120M_CLK:
 205                 if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
 206                         return 0;
 207                 else
 208                         return freq / 4;
 209         case PLL_SYS_PFD0_392M_CLK:
 210                 reg = readl(&ccm_anatop->pfd_480a);
 211                 if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
 212                         return 0;
 213                 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
 214                         CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
 215                 break;
 216         case PLL_SYS_PFD0_196M_CLK:
 217                 if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
 218                         return 0;
 219                 reg = readl(&ccm_anatop->pfd_480a);
 220                 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
 221                         CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
 222                 div = 2;
 223                 break;
 224         case PLL_SYS_PFD1_332M_CLK:
 225                 reg = readl(&ccm_anatop->pfd_480a);
 226                 if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
 227                         return 0;
 228                 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
 229                         CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
 230                 break;
 231         case PLL_SYS_PFD1_166M_CLK:
 232                 if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
 233                         return 0;
 234                 reg = readl(&ccm_anatop->pfd_480a);
 235                 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
 236                         CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
 237                 div = 2;
 238                 break;
 239         case PLL_SYS_PFD2_270M_CLK:
 240                 reg = readl(&ccm_anatop->pfd_480a);
 241                 if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
 242                         return 0;
 243                 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
 244                         CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
 245                 break;
 246         case PLL_SYS_PFD2_135M_CLK:
 247                 if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
 248                         return 0;
 249                 reg = readl(&ccm_anatop->pfd_480a);
 250                 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
 251                         CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
 252                 div = 2;
 253                 break;
 254         case PLL_SYS_PFD3_CLK:
 255                 reg = readl(&ccm_anatop->pfd_480a);
 256                 if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
 257                         return 0;
 258                 frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
 259                         CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
 260                 break;
 261         case PLL_SYS_PFD4_CLK:
 262                 reg = readl(&ccm_anatop->pfd_480b);
 263                 if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
 264                         return 0;
 265                 frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
 266                         CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
 267                 break;
 268         case PLL_SYS_PFD5_CLK:
 269                 reg = readl(&ccm_anatop->pfd_480b);
 270                 if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
 271                         return 0;
 272                 frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
 273                         CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
 274                 break;
 275         case PLL_SYS_PFD6_CLK:
 276                 reg = readl(&ccm_anatop->pfd_480b);
 277                 if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
 278                         return 0;
 279                 frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
 280                         CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
 281                 break;
 282         case PLL_SYS_PFD7_CLK:
 283                 reg = readl(&ccm_anatop->pfd_480b);
 284                 if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
 285                         return 0;
 286                 frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
 287                         CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
 288                 break;
 289         default:
 290                 printf("Error derived pll_sys clock %d\n", derive);
 291                 return 0;
 292         }
 293
 294         return ((freq / frac) * 18) / div;
 295 }
 296
 297 static u32 mxc_get_pll_enet_derive(int derive)
 298 {
 299         u32 freq, reg;
 300
 301         freq = decode_pll(PLL_ENET, MXC_HCLK);
 302         reg = readl(&ccm_anatop->pll_enet);
 303
 304         switch (derive) {
 305         case PLL_ENET_MAIN_500M_CLK:
 306                 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
 307                         return freq / 2;
 308                 break;
 309         case PLL_ENET_MAIN_250M_CLK:
 310                 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
 311                         return freq / 4;
 312                 break;
 313         case PLL_ENET_MAIN_125M_CLK:
 314                 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
 315                         return freq / 8;
 316                 break;
 317         case PLL_ENET_MAIN_100M_CLK:
 318                 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
 319                         return freq / 10;
 320                 break;
 321         case PLL_ENET_MAIN_50M_CLK:
 322                 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
 323                         return freq / 20;
 324                 break;
 325         case PLL_ENET_MAIN_40M_CLK:
 326                 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
 327                         return freq / 25;
 328                 break;
 329         case PLL_ENET_MAIN_25M_CLK:
 330                 if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
 331                         return freq / 40;
 332                 break;
 333         default:
 334                 printf("Error derived pll_enet clock %d\n", derive);
 335                 break;
 336         }
 337
 338         return 0;
 339 }
 340
 341 static u32 mxc_get_pll_ddr_derive(int derive)
 342 {
 343         u32 freq, reg;
 344
 345         freq = decode_pll(PLL_DDR, MXC_HCLK);
 346         reg = readl(&ccm_anatop->pll_ddr);
 347
 348         switch (derive) {
 349         case PLL_DRAM_MAIN_1066M_CLK:
 350                 return freq;
 351         case PLL_DRAM_MAIN_533M_CLK:
 352                 if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
 353                         return freq / 2;
 354                 break;
 355         default:
 356                 printf("Error derived pll_ddr clock %d\n", derive);
 357                 break;
 358         }
 359
 360         return 0;
 361 }
 362
 363 static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
 364 {
 365         switch (pll) {
 366         case PLL_SYS:
 367                 return mxc_get_pll_sys_derive(derive);
 368         case PLL_ENET:
 369                 return mxc_get_pll_enet_derive(derive);
 370         case PLL_DDR:
 371                 return mxc_get_pll_ddr_derive(derive);
 372         default:
 373                 printf("Error pll.\n");
 374                 return 0;
 375         }
 376 }
 377
 378 static u32 get_root_src_clk(enum clk_root_src root_src)
 379 {
 380         switch (root_src) {
 381         case OSC_24M_CLK:
 382                 return 24000000u;
 383         case PLL_ARM_MAIN_800M_CLK:
 384                 return decode_pll(PLL_CORE, MXC_HCLK);
 385
 386         case PLL_SYS_MAIN_480M_CLK:
 387         case PLL_SYS_MAIN_240M_CLK:
 388         case PLL_SYS_MAIN_120M_CLK:
 389         case PLL_SYS_PFD0_392M_CLK:
 390         case PLL_SYS_PFD0_196M_CLK:
 391         case PLL_SYS_PFD1_332M_CLK:
 392         case PLL_SYS_PFD1_166M_CLK:
 393         case PLL_SYS_PFD2_270M_CLK:
 394         case PLL_SYS_PFD2_135M_CLK:
 395         case PLL_SYS_PFD3_CLK:
 396         case PLL_SYS_PFD4_CLK:
 397         case PLL_SYS_PFD5_CLK:
 398         case PLL_SYS_PFD6_CLK:
 399         case PLL_SYS_PFD7_CLK:
 400                 return mxc_get_pll_derive(PLL_SYS, root_src);
 401
 402         case PLL_ENET_MAIN_500M_CLK:
 403         case PLL_ENET_MAIN_250M_CLK:
 404         case PLL_ENET_MAIN_125M_CLK:
 405         case PLL_ENET_MAIN_100M_CLK:
 406         case PLL_ENET_MAIN_50M_CLK:
 407         case PLL_ENET_MAIN_40M_CLK:
 408         case PLL_ENET_MAIN_25M_CLK:
 409                 return mxc_get_pll_derive(PLL_ENET, root_src);
 410
 411         case PLL_DRAM_MAIN_1066M_CLK:
 412         case PLL_DRAM_MAIN_533M_CLK:
 413                 return mxc_get_pll_derive(PLL_DDR, root_src);
 414
 415         case PLL_AUDIO_MAIN_CLK:
 416                 return decode_pll(PLL_AUDIO, MXC_HCLK);
 417         case PLL_VIDEO_MAIN_CLK:
 418                 return decode_pll(PLL_VIDEO, MXC_HCLK);
 419
 420         case PLL_USB_MAIN_480M_CLK:
 421                 return decode_pll(PLL_USB, MXC_HCLK);
 422
 423         case REF_1M_CLK:
 424                 return 1000000;
 425         case OSC_32K_CLK:
 426                 return MXC_CLK32;
 427
 428         case EXT_CLK_1:
 429         case EXT_CLK_2:
 430         case EXT_CLK_3:
 431         case EXT_CLK_4:
 432                 printf("No EXT CLK supported??\n");
 433                 break;
 434         };
 435
 436         return 0;
 437 }
 438
 439 u32 get_root_clk(enum clk_root_index clock_id)
 440 {
 441         enum clk_root_src root_src;
 442         u32 post_podf, pre_podf, auto_podf, root_src_clk;
 443         int auto_en;
 444
 445         if (clock_root_enabled(clock_id) <= 0)
 446                 return 0;
 447
 448         if (clock_get_prediv(clock_id, &pre_podf) < 0)
 449                 return 0;
 450
 451         if (clock_get_postdiv(clock_id, &post_podf) < 0)
 452                 return 0;
 453
 454         if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
 455                 return 0;
 456
 457         if (auto_en == 0)
 458                 auto_podf = 0;
 459
 460         if (clock_get_src(clock_id, &root_src) < 0)
 461                 return 0;
 462
 463         root_src_clk = get_root_src_clk(root_src);
 464
 465         /*
 466          * bypass clk is ignored.
 467          */
 468
 469         return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
 470                 (auto_podf + 1);
 471 }
 472
 473 static u32 get_ddrc_clk(void)
 474 {
 475         u32 reg, freq;
 476         enum root_post_div post_div;
 477
 478         reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
 479         if (reg & CLK_ROOT_MUX_MASK)
 480                 /* DRAM_ALT_CLK_ROOT */
 481                 freq = get_root_clk(DRAM_ALT_CLK_ROOT);
 482         else
 483                 /* PLL_DRAM_MAIN_1066M_CLK */
 484                 freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
 485
 486         post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
 487
 488         return freq / (post_div + 1) / 2;
 489 }
 490
 491 unsigned int mxc_get_clock(enum mxc_clock clk)
 492 {
 493         switch (clk) {
 494         case MXC_ARM_CLK:
 495                 return get_root_clk(ARM_A7_CLK_ROOT);
 496         case MXC_AXI_CLK:
 497                 return get_root_clk(MAIN_AXI_CLK_ROOT);
 498         case MXC_AHB_CLK:
 499                 return get_root_clk(AHB_CLK_ROOT);
 500         case MXC_IPG_CLK:
 501                 return get_ipg_clk();
 502         case MXC_I2C_CLK:
 503                 return get_root_clk(I2C1_CLK_ROOT);
 504         case MXC_UART_CLK:
 505                 return get_root_clk(UART1_CLK_ROOT);
 506         case MXC_CSPI_CLK:
 507                 return get_root_clk(ECSPI1_CLK_ROOT);
 508         case MXC_DDR_CLK:
 509                 return get_ddrc_clk();
 510         case MXC_ESDHC_CLK:
 511                 return get_root_clk(USDHC1_CLK_ROOT);
 512         case MXC_ESDHC2_CLK:
 513                 return get_root_clk(USDHC2_CLK_ROOT);
 514         case MXC_ESDHC3_CLK:
 515                 return get_root_clk(USDHC3_CLK_ROOT);
 516         default:
 517                 printf("Unsupported mxc_clock %d\n", clk);
 518                 break;
 519         }
 520
 521         return 0;
 522 }
 523
 524 #ifdef CONFIG_SYS_I2C_MXC
 525 /* i2c_num can be 0 - 3 */
 526 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 527 {
 528         u32 target;
 529
 530         if (i2c_num >= 4)
 531                 return -EINVAL;
 532
 533         if (enable) {
 534                 clock_enable(CCGR_I2C1 + i2c_num, 0);
 535
 536                 /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */
 537
 538                 target = CLK_ROOT_ON |
 539                          I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
 540                          CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 541                          CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
 542                 clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
 543
 544                 clock_enable(CCGR_I2C1 + i2c_num, 1);
 545         } else {
 546                 clock_enable(CCGR_I2C1 + i2c_num, 0);
 547         }
 548
 549         return 0;
 550 }
 551 #endif
 552
 553 static void init_clk_esdhc(void)
 554 {
 555         u32 target;
 556
 557         /* disable the clock gate first */
 558         clock_enable(CCGR_USDHC1, 0);
 559         clock_enable(CCGR_USDHC2, 0);
 560         clock_enable(CCGR_USDHC3, 0);
 561
 562         /* 196: 392/2 */
 563         target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
 564                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 565                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
 566         clock_set_target_val(USDHC1_CLK_ROOT, target);
 567
 568         target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
 569                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 570                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
 571         clock_set_target_val(USDHC2_CLK_ROOT, target);
 572
 573         target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
 574                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 575                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
 576         clock_set_target_val(USDHC3_CLK_ROOT, target);
 577
 578         /* enable the clock gate */
 579         clock_enable(CCGR_USDHC1, 1);
 580         clock_enable(CCGR_USDHC2, 1);
 581         clock_enable(CCGR_USDHC3, 1);
 582 }
 583
 584 static void init_clk_uart(void)
 585 {
 586         u32 target;
 587
 588         /* disable the clock gate first */
 589         clock_enable(CCGR_UART1, 0);
 590         clock_enable(CCGR_UART2, 0);
 591         clock_enable(CCGR_UART3, 0);
 592         clock_enable(CCGR_UART4, 0);
 593         clock_enable(CCGR_UART5, 0);
 594         clock_enable(CCGR_UART6, 0);
 595         clock_enable(CCGR_UART7, 0);
 596
 597         /* 24Mhz */
 598         target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
 599                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 600                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 601         clock_set_target_val(UART1_CLK_ROOT, target);
 602
 603         target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
 604                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 605                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 606         clock_set_target_val(UART2_CLK_ROOT, target);
 607
 608         target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
 609                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 610                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 611         clock_set_target_val(UART3_CLK_ROOT, target);
 612
 613         target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
 614                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 615                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 616         clock_set_target_val(UART4_CLK_ROOT, target);
 617
 618         target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
 619                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 620                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 621         clock_set_target_val(UART5_CLK_ROOT, target);
 622
 623         target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
 624                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 625                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 626         clock_set_target_val(UART6_CLK_ROOT, target);
 627
 628         target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
 629                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 630                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 631         clock_set_target_val(UART7_CLK_ROOT, target);
 632
 633         /* enable the clock gate */
 634         clock_enable(CCGR_UART1, 1);
 635         clock_enable(CCGR_UART2, 1);
 636         clock_enable(CCGR_UART3, 1);
 637         clock_enable(CCGR_UART4, 1);
 638         clock_enable(CCGR_UART5, 1);
 639         clock_enable(CCGR_UART6, 1);
 640         clock_enable(CCGR_UART7, 1);
 641 }
 642
 643 static void init_clk_weim(void)
 644 {
 645         u32 target;
 646
 647         /* disable the clock gate first */
 648         clock_enable(CCGR_WEIM, 0);
 649
 650         /* 120Mhz */
 651         target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
 652                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 653                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 654         clock_set_target_val(EIM_CLK_ROOT, target);
 655
 656         /* enable the clock gate */
 657         clock_enable(CCGR_WEIM, 1);
 658 }
 659
 660 static void init_clk_ecspi(void)
 661 {
 662         u32 target;
 663
 664         /* disable the clock gate first */
 665         clock_enable(CCGR_ECSPI1, 0);
 666         clock_enable(CCGR_ECSPI2, 0);
 667         clock_enable(CCGR_ECSPI3, 0);
 668         clock_enable(CCGR_ECSPI4, 0);
 669
 670         /* 60Mhz: 240/4 */
 671         target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
 672                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 673                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
 674         clock_set_target_val(ECSPI1_CLK_ROOT, target);
 675
 676         target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
 677                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 678                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
 679         clock_set_target_val(ECSPI2_CLK_ROOT, target);
 680
 681         target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
 682                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 683                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
 684         clock_set_target_val(ECSPI3_CLK_ROOT, target);
 685
 686         target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
 687                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 688                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
 689         clock_set_target_val(ECSPI4_CLK_ROOT, target);
 690
 691         /* enable the clock gate */
 692         clock_enable(CCGR_ECSPI1, 1);
 693         clock_enable(CCGR_ECSPI2, 1);
 694         clock_enable(CCGR_ECSPI3, 1);
 695         clock_enable(CCGR_ECSPI4, 1);
 696 }
 697
 698 static void init_clk_wdog(void)
 699 {
 700         u32 target;
 701
 702         /* disable the clock gate first */
 703         clock_enable(CCGR_WDOG1, 0);
 704         clock_enable(CCGR_WDOG2, 0);
 705         clock_enable(CCGR_WDOG3, 0);
 706         clock_enable(CCGR_WDOG4, 0);
 707
 708         /* 24Mhz */
 709         target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
 710                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 711                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 712         clock_set_target_val(WDOG_CLK_ROOT, target);
 713
 714         /* enable the clock gate */
 715         clock_enable(CCGR_WDOG1, 1);
 716         clock_enable(CCGR_WDOG2, 1);
 717         clock_enable(CCGR_WDOG3, 1);
 718         clock_enable(CCGR_WDOG4, 1);
 719 }
 720
 721 #ifdef CONFIG_MXC_EPDC
 722 static void init_clk_epdc(void)
 723 {
 724         u32 target;
 725
 726         /* disable the clock gate first */
 727         clock_enable(CCGR_EPDC, 0);
 728
 729         /* 24Mhz */
 730         target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
 731                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 732                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
 733         clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
 734
 735         /* enable the clock gate */
 736         clock_enable(CCGR_EPDC, 1);
 737 }
 738 #endif
 739
 740 static int enable_pll_enet(void)
 741 {
 742         u32 reg;
 743         s32 timeout = 100000;
 744
 745         reg = readl(&ccm_anatop->pll_enet);
 746         /* If pll_enet powered up, no need to set it again */
 747         if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
 748                 reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
 749                 writel(reg, &ccm_anatop->pll_enet);
 750
 751                 while (timeout--) {
 752                         if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
 753                                 break;
 754                 }
 755
 756                 if (timeout <= 0) {
 757                         /* If timeout, we set pwdn for pll_enet. */
 758                         reg |= ANADIG_PLL_ENET_PWDN_MASK;
 759                         return -ETIME;
 760                 }
 761         }
 762
 763         /* Clear bypass */
 764         writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
 765
 766         writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
 767                 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
 768                 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
 769                 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
 770                 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
 771                 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
 772                 | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
 773                &ccm_anatop->pll_enet_set);
 774
 775         return 0;
 776 }
 777 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
 778         u32 post_div)
 779 {
 780         u32 reg = 0;
 781         ulong start;
 782
 783         debug("pll5 div = %d, num = %d, denom = %d\n",
 784                 pll_div, pll_num, pll_denom);
 785
 786         /* Power up PLL5 video and disable its output */
 787         writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
 788                 CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
 789                 CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
 790                 CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
 791                 CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
 792                 CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
 793                 &ccm_anatop->pll_video_clr);
 794
 795         /* Set div, num and denom */
 796         switch (post_div) {
 797         case 1:
 798                 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
 799                         CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
 800                         CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
 801                         &ccm_anatop->pll_video_set);
 802                 break;
 803         case 2:
 804                 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
 805                         CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
 806                         CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
 807                         &ccm_anatop->pll_video_set);
 808                 break;
 809         case 3:
 810                 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
 811                         CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
 812                         CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
 813                         &ccm_anatop->pll_video_set);
 814                 break;
 815         case 4:
 816                 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
 817                         CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
 818                         CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
 819                         &ccm_anatop->pll_video_set);
 820                 break;
 821         case 0:
 822         default:
 823                 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
 824                         CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
 825                         CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
 826                         &ccm_anatop->pll_video_set);
 827                 break;
 828         }
 829
 830         writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
 831                 &ccm_anatop->pll_video_num);
 832
 833         writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
 834                 &ccm_anatop->pll_video_denom);
 835
 836         /* Wait PLL5 lock */
 837         start = get_timer(0);   /* Get current timestamp */
 838
 839         do {
 840                 reg = readl(&ccm_anatop->pll_video);
 841                 if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
 842                         /* Enable PLL out */
 843                         writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
 844                                         &ccm_anatop->pll_video_set);
 845                         return 0;
 846                 }
 847         } while (get_timer(0) < (start + 10)); /* Wait 10ms */
 848
 849         printf("Lock PLL5 timeout\n");
 850
 851         return 1;
 852 }
 853
 854 int set_clk_qspi(void)
 855 {
 856         u32 target;
 857
 858         /* disable the clock gate first */
 859         clock_enable(CCGR_QSPI, 0);
 860
 861         /* 49M: 392/2/4 */
 862         target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
 863                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 864                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
 865         clock_set_target_val(QSPI_CLK_ROOT, target);
 866
 867         /* enable the clock gate */
 868         clock_enable(CCGR_QSPI, 1);
 869
 870         return 0;
 871 }
 872
 873 int set_clk_nand(void)
 874 {
 875         u32 target;
 876
 877         /* disable the clock gate first */
 878         clock_enable(CCGR_RAWNAND, 0);
 879
 880         enable_pll_enet();
 881         /* 100: 500/5 */
 882         target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
 883                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 884                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
 885         clock_set_target_val(NAND_CLK_ROOT, target);
 886
 887         /* enable the clock gate */
 888         clock_enable(CCGR_RAWNAND, 1);
 889
 890         return 0;
 891 }
 892
 893 void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
 894 {
 895         u32 hck = MXC_HCLK/1000;
 896         u32 min = hck * 27;
 897         u32 max = hck * 54;
 898         u32 temp, best = 0;
 899         u32 i, j, pred = 1, postd = 1;
 900         u32 pll_div, pll_num, pll_denom, post_div = 0;
 901         u32 target;
 902
 903         debug("mxs_set_lcdclk, freq = %d\n", freq);
 904
 905         clock_enable(CCGR_LCDIF, 0);
 906
 907         temp = (freq * 8 * 8);
 908         if (temp < min) {
 909                 for (i = 1; i <= 4; i++) {
 910                         if ((temp * (1 << i)) > min) {
 911                                 post_div = i;
 912                                 freq = (freq * (1 << i));
 913                                 break;
 914                         }
 915                 }
 916
 917                 if (5 == i) {
 918                         printf("Fail to set rate to %dkhz", freq);
 919                         return;
 920                 }
 921         }
 922
 923         for (i = 1; i <= 8; i++) {
 924                 for (j = 1; j <= 8; j++) {
 925                         temp = freq * i * j;
 926                         if (temp > max || temp < min)
 927                                 continue;
 928
 929                         if (best == 0 || temp < best) {
 930                                 best = temp;
 931                                 pred = i;
 932                                 postd = j;
 933                         }
 934                 }
 935         }
 936
 937         if (best == 0) {
 938                 printf("Fail to set rate to %dkhz", freq);
 939                 return;
 940         }
 941
 942         debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
 943
 944         pll_div = best / hck;
 945         pll_denom = 1000000;
 946         pll_num = (best - hck * pll_div) * pll_denom / hck;
 947
 948         if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 949                 return;
 950
 951         target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
 952                  CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
 953         clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
 954
 955         clock_enable(CCGR_LCDIF, 1);
 956 }
 957
 958 #ifdef CONFIG_FEC_MXC
 959 int set_clk_enet(enum enet_freq type)
 960 {
 961         u32 target;
 962         int ret;
 963         u32 enet1_ref, enet2_ref;
 964
 965         /* disable the clock first */
 966         clock_enable(CCGR_ENET1, 0);
 967         clock_enable(CCGR_ENET2, 0);
 968
 969         switch (type) {
 970         case ENET_125MHZ:
 971                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
 972                 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
 973                 break;
 974         case ENET_50MHZ:
 975                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
 976                 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
 977                 break;
 978         case ENET_25MHZ:
 979                 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
 980                 enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
 981                 break;
 982         default:
 983                 return -EINVAL;
 984         }
 985
 986         ret = enable_pll_enet();
 987         if (ret != 0)
 988                 return ret;
 989
 990         /* set enet axi clock 196M: 392/2 */
 991         target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
 992                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 993                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
 994         clock_set_target_val(ENET_AXI_CLK_ROOT, target);
 995
 996         target = CLK_ROOT_ON | enet1_ref |
 997                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
 998                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
 999         clock_set_target_val(ENET1_REF_CLK_ROOT, target);
1000
1001         target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
1002                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1003                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
1004         clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
1005
1006         target = CLK_ROOT_ON | enet2_ref |
1007                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1008                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
1009         clock_set_target_val(ENET2_REF_CLK_ROOT, target);
1010
1011         target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
1012                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1013                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
1014         clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
1015
1016 #ifdef CONFIG_FEC_MXC_25M_REF_CLK
1017         target = CLK_ROOT_ON |
1018                  ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
1019                  CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
1020                  CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
1021         clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
1022 #endif
1023         /* enable clock */
1024         clock_enable(CCGR_ENET1, 1);
1025         clock_enable(CCGR_ENET2, 1);
1026
1027         return 0;
1028 }
1029 #endif
1030
1031 /* Configure PLL/PFD freq */
1032 void clock_init(void)
1033 {
1034 /* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
1035  *   In u-boot, we have to:
1036  *   1. Configure PFD3- PFD7 for freq we needed in u-boot
1037  *   2. Set clock root for peripherals (ip channel) used in u-boot but without set rate
1038  *       interface.  The clocks for these peripherals are enabled after this intialization.
1039  *   3. Other peripherals with set clock rate interface does not be set in this function.
1040  */
1041         u32 reg;
1042
1043         /*
1044          * Configure PFD4 to 392M
1045          * 480M * 18 / 0x16 = 392M
1046          */
1047         reg = readl(&ccm_anatop->pfd_480b);
1048
1049         reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
1050                  CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
1051         reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
1052
1053         writel(reg, &ccm_anatop->pfd_480b);
1054
1055         init_clk_esdhc();
1056         init_clk_uart();
1057         init_clk_weim();
1058         init_clk_ecspi();
1059         init_clk_wdog();
1060 #ifdef CONFIG_MXC_EPDC
1061         init_clk_epdc();
1062 #endif
1063
1064         enable_usboh3_clk(1);
1065
1066         clock_enable(CCGR_SNVS, 1);
1067
1068 #ifdef CONFIG_NAND_MXS
1069         clock_enable(CCGR_RAWNAND, 1);
1070 #endif
1071
1072         if (IS_ENABLED(CONFIG_IMX_RDC)) {
1073                 clock_enable(CCGR_RDC, 1);
1074                 clock_enable(CCGR_SEMA1, 1);
1075                 clock_enable(CCGR_SEMA2, 1);
1076         }
1077 }
1078
1079 #ifdef CONFIG_IMX_HAB
1080 void hab_caam_clock_enable(unsigned char enable)
1081 {
1082         if (enable)
1083                 clock_enable(CCGR_CAAM, 1);
1084         else
1085                 clock_enable(CCGR_CAAM, 0);
1086 }
1087 #endif
1088
1089 #ifdef CONFIG_MXC_EPDC
1090 void epdc_clock_enable(void)
1091 {
1092         clock_enable(CCGR_EPDC, 1);
1093 }
1094 void epdc_clock_disable(void)
1095 {
1096         clock_enable(CCGR_EPDC, 0);
1097 }
1098 #endif
1099
1100 #ifndef CONFIG_SPL_BUILD
1101 /*
1102  * Dump some core clockes.
1103  */
1104 int do_mx7_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
1105                       char *const argv[])
1106 {
1107         u32 freq;
1108         freq = decode_pll(PLL_CORE, MXC_HCLK);
1109         printf("PLL_CORE    %8d MHz\n", freq / 1000000);
1110         freq = decode_pll(PLL_SYS, MXC_HCLK);
1111         printf("PLL_SYS    %8d MHz\n", freq / 1000000);
1112         freq = decode_pll(PLL_ENET, MXC_HCLK);
1113         printf("PLL_NET    %8d MHz\n", freq / 1000000);
1114
1115         printf("\n");
1116
1117         printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
1118         printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
1119 #ifdef CONFIG_MXC_SPI
1120         printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
1121 #endif
1122         printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
1123         printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
1124         printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
1125         printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
1126         printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
1127         printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
1128
1129         return 0;
1130 }
1131
1132 U_BOOT_CMD(
1133         clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
1134         "display clocks",
1135         ""
1136 );
1137 #endif