arch/arm/cpu/armv8/fsl-layerscape/mp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <image.h>
   9 #include <asm/cache.h>
  10 #include <asm/io.h>
  11 #include <asm/system.h>
  12 #include <asm/arch/mp.h>
  13 #include <asm/arch/soc.h>
  14 #include "cpu.h"
  15 #include <asm/arch-fsl-layerscape/soc.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 void *get_spin_tbl_addr(void)
  20 {
  21         return &__spin_table;
  22 }
  23
  24 phys_addr_t determine_mp_bootpg(void)
  25 {
  26         return (phys_addr_t)&secondary_boot_code;
  27 }
  28
  29 void update_os_arch_secondary_cores(uint8_t os_arch)
  30 {
  31         u64 *table = get_spin_tbl_addr();
  32         int i;
  33
  34         for (i = 1; i < CONFIG_MAX_CPUS; i++) {
  35                 if (os_arch == IH_ARCH_DEFAULT)
  36                         table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  37                                 SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME;
  38                 else
  39                         table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  40                                 SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF;
  41         }
  42 }
  43
  44 #ifdef CONFIG_FSL_LSCH3
  45 void wake_secondary_core_n(int cluster, int core, int cluster_cores)
  46 {
  47         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  48         struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  49         u32 mpidr = 0;
  50
  51         mpidr = ((cluster << 8) | core);
  52         /*
  53          * mpidr_el1 register value of core which needs to be released
  54          * is written to scratchrw[6] register
  55          */
  56         gur_out32(&gur->scratchrw[6], mpidr);
  57         asm volatile("dsb st" : : : "memory");
  58         rst->brrl |= 1 << ((cluster * cluster_cores) + core);
  59         asm volatile("dsb st" : : : "memory");
  60         /*
  61          * scratchrw[6] register value is polled
  62          * when the value becomes zero, this means that this core is up
  63          * and running, next core can be released now
  64          */
  65         while (gur_in32(&gur->scratchrw[6]) != 0)
  66                 ;
  67 }
  68 #endif
  69
  70 int fsl_layerscape_wake_seconday_cores(void)
  71 {
  72         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  73 #ifdef CONFIG_FSL_LSCH3
  74         struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  75         u32 svr, ver, cluster, type;
  76         int j = 0, cluster_cores = 0;
  77 #elif defined(CONFIG_FSL_LSCH2)
  78         struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
  79 #endif
  80         u32 cores, cpu_up_mask = 1;
  81         int i, timeout = 10;
  82         u64 *table = get_spin_tbl_addr();
  83
  84 #ifdef COUNTER_FREQUENCY_REAL
  85         /* update for secondary cores */
  86         __real_cntfrq = COUNTER_FREQUENCY_REAL;
  87         flush_dcache_range((unsigned long)&__real_cntfrq,
  88                            (unsigned long)&__real_cntfrq + 8);
  89 #endif
  90
  91         cores = cpu_mask();
  92         /* Clear spin table so that secondary processors
  93          * observe the correct value after waking up from wfe.
  94          */
  95         memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
  96         flush_dcache_range((unsigned long)table,
  97                            (unsigned long)table +
  98                            (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
  99
 100         printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
 101
 102 #ifdef CONFIG_FSL_LSCH3
 103         gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
 104         gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
 105
 106         svr = gur_in32(&gur->svr);
 107         ver = SVR_SOC_VER(svr);
 108         if (ver == SVR_LS2080A || ver == SVR_LS2085A) {
 109                 gur_out32(&gur->scratchrw[6], 1);
 110                 asm volatile("dsb st" : : : "memory");
 111                 rst->brrl = cores;
 112                 asm volatile("dsb st" : : : "memory");
 113         } else {
 114                 /*
 115                  * Release the cores out of reset one-at-a-time to avoid
 116                  * power spikes
 117                  */
 118                 i = 0;
 119                 cluster = in_le32(&gur->tp_cluster[i].lower);
 120                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 121                         type = initiator_type(cluster, j);
 122                         if (type &&
 123                             TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 124                                 cluster_cores++;
 125                 }
 126
 127                 do {
 128                         cluster = in_le32(&gur->tp_cluster[i].lower);
 129                         for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 130                                 type = initiator_type(cluster, j);
 131                                 if (type &&
 132                                     TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 133                                         wake_secondary_core_n(i, j,
 134                                                               cluster_cores);
 135                         }
 136                 i++;
 137                 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
 138         }
 139 #elif defined(CONFIG_FSL_LSCH2)
 140         scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
 141         scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
 142         asm volatile("dsb st" : : : "memory");
 143         gur_out32(&gur->brrl, cores);
 144         asm volatile("dsb st" : : : "memory");
 145
 146         /* Bootup online cores */
 147         scfg_out32(&scfg->corebcr, cores);
 148 #endif
 149         /* This is needed as a precautionary measure.
 150          * If some code before this has accidentally  released the secondary
 151          * cores then the pre-bootloader code will trap them in a "wfe" unless
 152          * the scratchrw[6] is set. In this case we need a sev here to get these
 153          * cores moving again.
 154          */
 155         asm volatile("sev");
 156
 157         while (timeout--) {
 158                 flush_dcache_range((unsigned long)table, (unsigned long)table +
 159                                    CONFIG_MAX_CPUS * 64);
 160                 for (i = 1; i < CONFIG_MAX_CPUS; i++) {
 161                         if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
 162                                         SPIN_TABLE_ELEM_STATUS_IDX])
 163                                 cpu_up_mask |= 1 << i;
 164                 }
 165                 if (hweight32(cpu_up_mask) == hweight32(cores))
 166                         break;
 167                 udelay(10);
 168         }
 169         if (timeout <= 0) {
 170                 printf("Not all cores (0x%x) are up (0x%x)\n",
 171                        cores, cpu_up_mask);
 172                 return 1;
 173         }
 174         printf("All (%d) cores are up.\n", hweight32(cores));
 175
 176         return 0;
 177 }
 178
 179 int is_core_valid(unsigned int core)
 180 {
 181         return !!((1 << core) & cpu_mask());
 182 }
 183
 184 static int is_pos_valid(unsigned int pos)
 185 {
 186         return !!((1 << pos) & cpu_pos_mask());
 187 }
 188
 189 int is_core_online(u64 cpu_id)
 190 {
 191         u64 *table;
 192         int pos = id_to_core(cpu_id);
 193         table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
 194         return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
 195 }
 196
 197 int cpu_reset(u32 nr)
 198 {
 199         puts("Feature is not implemented.\n");
 200
 201         return 0;
 202 }
 203
 204 int cpu_disable(u32 nr)
 205 {
 206         puts("Feature is not implemented.\n");
 207
 208         return 0;
 209 }
 210
 211 static int core_to_pos(int nr)
 212 {
 213         u32 cores = cpu_pos_mask();
 214         int i, count = 0;
 215
 216         if (nr == 0) {
 217                 return 0;
 218         } else if (nr >= hweight32(cores)) {
 219                 puts("Not a valid core number.\n");
 220                 return -1;
 221         }
 222
 223         for (i = 1; i < 32; i++) {
 224                 if (is_pos_valid(i)) {
 225                         count++;
 226                         if (count == nr)
 227                                 break;
 228                 }
 229         }
 230
 231         if (count != nr)
 232                 return -1;
 233
 234         return i;
 235 }
 236
 237 int cpu_status(u32 nr)
 238 {
 239         u64 *table;
 240         int pos;
 241
 242         if (nr == 0) {
 243                 table = (u64 *)get_spin_tbl_addr();
 244                 printf("table base @ 0x%p\n", table);
 245         } else {
 246                 pos = core_to_pos(nr);
 247                 if (pos < 0)
 248                         return -1;
 249                 table = (u64 *)get_spin_tbl_addr() + pos *
 250                         WORDS_PER_SPIN_TABLE_ENTRY;
 251                 printf("table @ 0x%p\n", table);
 252                 printf("   addr - 0x%016llx\n",
 253                        table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
 254                 printf("   status   - 0x%016llx\n",
 255                        table[SPIN_TABLE_ELEM_STATUS_IDX]);
 256                 printf("   lpid  - 0x%016llx\n",
 257                        table[SPIN_TABLE_ELEM_LPID_IDX]);
 258         }
 259
 260         return 0;
 261 }
 262
 263 int cpu_release(u32 nr, int argc, char *const argv[])
 264 {
 265         u64 boot_addr;
 266         u64 *table = (u64 *)get_spin_tbl_addr();
 267         int pos;
 268
 269         pos = core_to_pos(nr);
 270         if (pos <= 0)
 271                 return -1;
 272
 273         table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
 274         boot_addr = simple_strtoull(argv[0], NULL, 16);
 275         table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
 276         flush_dcache_range((unsigned long)table,
 277                            (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
 278         asm volatile("dsb st");
 279         smp_kick_all_cpus();    /* only those with entry addr set will run */
 280         /*
 281          * When the first release command runs, all cores are set to go. Those
 282          * without a valid entry address will be trapped by "wfe". "sev" kicks
 283          * them off to check the address again. When set, they continue to run.
 284          */
 285         asm volatile("sev");
 286
 287         return 0;
 288 }