5 * SPDX-License-Identifier: GPL-2.0+
8 /* for now: just dummy functions to satisfy the linker */
12 void __flush_cache(unsigned long start, unsigned long size)
14 #if defined(CONFIG_ARM1136)
16 #if !defined(CONFIG_SYS_ICACHE_OFF)
17 asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
20 #if !defined(CONFIG_SYS_DCACHE_OFF)
21 asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
24 #endif /* CONFIG_ARM1136 */
26 #ifdef CONFIG_ARM926EJS
27 /* test and clean, page 2-23 of arm926ejs manual */
28 asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
29 /* disable write buffer as well (page 2-22) */
30 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
31 #endif /* CONFIG_ARM926EJS */
34 void flush_cache(unsigned long start, unsigned long size)
35 __attribute__((weak, alias("__flush_cache")));
38 * Default implementation:
39 * do a range flush for the entire range
41 void __flush_dcache_all(void)
45 void flush_dcache_all(void)
46 __attribute__((weak, alias("__flush_dcache_all")));
50 * Default implementation of enable_caches()
51 * Real implementation should be in platform code
53 void __enable_caches(void)
55 puts("WARNING: Caches not enabled\n");
57 void enable_caches(void)
58 __attribute__((weak, alias("__enable_caches")));