drivers/net/phy/aquantia.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Aquantia PHY drivers
   4  *
   5  * Copyright 2014 Freescale Semiconductor, Inc.
   6  * Copyright 2018, 2021 NXP
   7  */
   8 #include <config.h>
   9 #include <dm.h>
  10 #include <log.h>
  11 #include <net.h>
  12 #include <phy.h>
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <u-boot/crc.h>
  16 #include <malloc.h>
  17 #include <asm/byteorder.h>
  18 #include <fs.h>
  19
  20 #define AQUNTIA_10G_CTL         0x20
  21 #define AQUNTIA_VENDOR_P1       0xc400
  22
  23 #define AQUNTIA_SPEED_LSB_MASK  0x2000
  24 #define AQUNTIA_SPEED_MSB_MASK  0x40
  25
  26 #define AQUANTIA_SYSTEM_INTERFACE_SR     0xe812
  27 #define  AQUANTIA_SYSTEM_INTERFACE_SR_READY     BIT(0)
  28 #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
  29 #define AQUANTIA_FIRMWARE_ID             0x20
  30 #define AQUANTIA_RESERVED_STATUS         0xc885
  31 #define AQUANTIA_FIRMWARE_MAJOR_MASK     0xff00
  32 #define AQUANTIA_FIRMWARE_MINOR_MASK     0xff
  33 #define AQUANTIA_FIRMWARE_BUILD_MASK     0xf0
  34
  35 #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
  36 #define AQUANTIA_SI_IN_USE_MASK          0x0078
  37 #define AQUANTIA_SI_USXGMII              0x0018
  38
  39 /* registers in MDIO_MMD_VEND1 region */
  40 #define AQUANTIA_VND1_GLOBAL_SC                 0x000
  41 #define  AQUANTIA_VND1_GLOBAL_SC_LP             BIT(0xb)
  42
  43 #define GLOBAL_FIRMWARE_ID 0x20
  44 #define GLOBAL_FAULT 0xc850
  45 #define GLOBAL_RSTATUS_1 0xc885
  46
  47 #define GLOBAL_ALARM_1 0xcc00
  48 #define SYSTEM_READY_BIT 0x40
  49
  50 #define GLOBAL_STANDARD_CONTROL 0x0
  51 #define SOFT_RESET BIT(15)
  52 #define LOW_POWER BIT(11)
  53
  54 #define MAILBOX_CONTROL 0x0200
  55 #define MAILBOX_EXECUTE BIT(15)
  56 #define MAILBOX_WRITE BIT(14)
  57 #define MAILBOX_RESET_CRC BIT(12)
  58 #define MAILBOX_BUSY BIT(8)
  59
  60 #define MAILBOX_CRC 0x0201
  61
  62 #define MAILBOX_ADDR_MSW 0x0202
  63 #define MAILBOX_ADDR_LSW 0x0203
  64
  65 #define MAILBOX_DATA_MSW 0x0204
  66 #define MAILBOX_DATA_LSW 0x0205
  67
  68 #define UP_CONTROL 0xc001
  69 #define UP_RESET BIT(15)
  70 #define UP_RUN_STALL_OVERRIDE BIT(6)
  71 #define UP_RUN_STALL BIT(0)
  72
  73 #define AQUANTIA_PMA_RX_VENDOR_P1               0xe400
  74 #define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK      GENMASK(1, 0)
  75 /* MDI reversal configured through registers */
  76 #define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG      BIT(1)
  77 /* MDI reversal enabled */
  78 #define  AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV      BIT(0)
  79
  80 /*
  81  * global start rate, the protocol associated with this speed is used by default
  82  * on SI.
  83  */
  84 #define AQUANTIA_VND1_GSTART_RATE               0x31a
  85 #define  AQUANTIA_VND1_GSTART_RATE_OFF          0
  86 #define  AQUANTIA_VND1_GSTART_RATE_100M         1
  87 #define  AQUANTIA_VND1_GSTART_RATE_1G           2
  88 #define  AQUANTIA_VND1_GSTART_RATE_10G          3
  89 #define  AQUANTIA_VND1_GSTART_RATE_2_5G         4
  90 #define  AQUANTIA_VND1_GSTART_RATE_5G           5
  91
  92 /* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
  93 #define AQUANTIA_VND1_GSYSCFG_BASE              0x31b
  94 #define AQUANTIA_VND1_GSYSCFG_100M              0
  95 #define AQUANTIA_VND1_GSYSCFG_1G                1
  96 #define AQUANTIA_VND1_GSYSCFG_2_5G              2
  97 #define AQUANTIA_VND1_GSYSCFG_5G                3
  98 #define AQUANTIA_VND1_GSYSCFG_10G               4
  99
 100 #define AQUANTIA_VND1_SMBUS0                    0xc485
 101 #define AQUANTIA_VND1_SMBUS1                    0xc495
 102
 103 /* addresses of memory segments in the phy */
 104 #define DRAM_BASE_ADDR 0x3FFE0000
 105 #define IRAM_BASE_ADDR 0x40000000
 106
 107 /* firmware image format constants */
 108 #define VERSION_STRING_SIZE 0x40
 109 #define VERSION_STRING_OFFSET 0x0200
 110 #define HEADER_OFFSET 0x300
 111
 112 /* driver private data */
 113 #define AQUANTIA_NA             0
 114 #define AQUANTIA_GEN1           1
 115 #define AQUANTIA_GEN2           2
 116 #define AQUANTIA_GEN3           3
 117
 118 #pragma pack(1)
 119 struct fw_header {
 120         u8 padding[4];
 121         u8 iram_offset[3];
 122         u8 iram_size[3];
 123         u8 dram_offset[3];
 124         u8 dram_size[3];
 125 };
 126
 127 #pragma pack()
 128
 129 #if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW)
 130 static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
 131 {
 132         loff_t length, read;
 133         int ret;
 134         void *addr = NULL;
 135
 136         *fw_addr = NULL;
 137         *fw_length = 0;
 138         debug("Loading Aquantia microcode from %s %s\n",
 139               CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME);
 140         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
 141         if (ret < 0)
 142                 goto cleanup;
 143
 144         ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length);
 145         if (ret < 0)
 146                 goto cleanup;
 147
 148         addr = malloc(length);
 149         if (!addr) {
 150                 ret = -ENOMEM;
 151                 goto cleanup;
 152         }
 153
 154         ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
 155         if (ret < 0)
 156                 goto cleanup;
 157
 158         ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,
 159                       &read);
 160         if (ret < 0)
 161                 goto cleanup;
 162
 163         *fw_addr = addr;
 164         *fw_length = length;
 165         debug("Found Aquantia microcode.\n");
 166
 167 cleanup:
 168         if (ret < 0) {
 169                 printf("loading firmware file %s %s failed with error %d\n",
 170                        CONFIG_PHY_AQUANTIA_FW_PART,
 171                        CONFIG_PHY_AQUANTIA_FW_NAME, ret);
 172                 free(addr);
 173         }
 174         return ret;
 175 }
 176
 177 /* load data into the phy's memory */
 178 static int aquantia_load_memory(struct phy_device *phydev, u32 addr,
 179                                 const u8 *data, size_t len)
 180 {
 181         size_t pos;
 182         u16 crc = 0, up_crc;
 183
 184         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC);
 185         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16);
 186         phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);
 187
 188         for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {
 189                 u32 word = 0;
 190
 191                 memcpy(&word, &data[pos], min(sizeof(u32), len - pos));
 192
 193                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW,
 194                           (word >> 16));
 195                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW,
 196                           word & 0xffff);
 197
 198                 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL,
 199                           MAILBOX_EXECUTE | MAILBOX_WRITE);
 200
 201                 /* keep a big endian CRC to match the phy processor */
 202                 word = cpu_to_be32(word);
 203                 crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word));
 204         }
 205
 206         up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC);
 207         if (crc != up_crc) {
 208                 printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",
 209                        phydev->dev->name, crc, up_crc);
 210                 return -EINVAL;
 211         }
 212         return 0;
 213 }
 214
 215 static u32 unpack_u24(const u8 *data)
 216 {
 217         return (data[2] << 16) + (data[1] << 8) + data[0];
 218 }
 219
 220 static int aquantia_upload_firmware(struct phy_device *phydev)
 221 {
 222         int ret;
 223         u8 *addr = NULL;
 224         size_t fw_length = 0;
 225         u16 calculated_crc, read_crc;
 226         char version[VERSION_STRING_SIZE];
 227         u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size;
 228         const struct fw_header *header;
 229
 230         ret = aquantia_read_fw(&addr, &fw_length);
 231         if (ret != 0)
 232                 return ret;
 233
 234         read_crc = (addr[fw_length - 2] << 8)  | addr[fw_length - 1];
 235         calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
 236         if (read_crc != calculated_crc) {
 237                 printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
 238                        phydev->dev->name, read_crc, calculated_crc);
 239                 ret = -EINVAL;
 240                 goto done;
 241         }
 242
 243         /* Find the DRAM and IRAM sections within the firmware file. */
 244         primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;
 245
 246         header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET];
 247
 248         iram_offset = primary_offset + unpack_u24(header->iram_offset);
 249         iram_size = unpack_u24(header->iram_size);
 250
 251         dram_offset = primary_offset + unpack_u24(header->dram_offset);
 252         dram_size = unpack_u24(header->dram_size);
 253
 254         debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n",
 255               primary_offset, iram_offset, iram_size, dram_offset, dram_size);
 256
 257         strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
 258                 VERSION_STRING_SIZE);
 259         printf("%s loading firmware version '%s'\n", phydev->dev->name, version);
 260
 261         /* stall the microcprocessor */
 262         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 263                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
 264
 265         debug("loading dram 0x%08x from offset=%d size=%d\n",
 266               DRAM_BASE_ADDR, dram_offset, dram_size);
 267         ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
 268                                    dram_size);
 269         if (ret != 0)
 270                 goto done;
 271
 272         debug("loading iram 0x%08x from offset=%d size=%d\n",
 273               IRAM_BASE_ADDR, iram_offset, iram_size);
 274         ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
 275                                    iram_size);
 276         if (ret != 0)
 277                 goto done;
 278
 279         /* make sure soft reset and low power mode are clear */
 280         phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);
 281
 282         /* Release the microprocessor. UP_RESET must be held for 100 usec. */
 283         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
 284                   UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET);
 285
 286         udelay(100);
 287
 288         phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE);
 289
 290         printf("%s firmware loading done.\n", phydev->dev->name);
 291 done:
 292         free(addr);
 293         return ret;
 294 }
 295 #else
 296 static int aquantia_upload_firmware(struct phy_device *phydev)
 297 {
 298         printf("ERROR %s firmware loading disabled.\n", phydev->dev->name);
 299         return -1;
 300 }
 301 #endif
 302
 303 struct {
 304         u16 syscfg;
 305         int cnt;
 306         u16 start_rate;
 307 } aquantia_syscfg[PHY_INTERFACE_MODE_MAX] = {
 308         [PHY_INTERFACE_MODE_SGMII] =      {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
 309                                            AQUANTIA_VND1_GSTART_RATE_1G},
 310         [PHY_INTERFACE_MODE_2500BASEX]  = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
 311                                            AQUANTIA_VND1_GSTART_RATE_2_5G},
 312         [PHY_INTERFACE_MODE_10GBASER] =   {0x100, AQUANTIA_VND1_GSYSCFG_10G,
 313                                            AQUANTIA_VND1_GSTART_RATE_10G},
 314         [PHY_INTERFACE_MODE_USXGMII] =    {0x080, AQUANTIA_VND1_GSYSCFG_10G,
 315                                            AQUANTIA_VND1_GSTART_RATE_10G},
 316 };
 317
 318 static int aquantia_set_proto(struct phy_device *phydev,
 319                               phy_interface_t interface)
 320 {
 321         int i;
 322
 323         if (!aquantia_syscfg[interface].cnt)
 324                 return 0;
 325
 326         /* set the default rate to enable the SI link */
 327         phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
 328                   aquantia_syscfg[interface].start_rate);
 329
 330         /* set selected protocol for all relevant line side link speeds */
 331         for (i = 0; i <= aquantia_syscfg[interface].cnt; i++)
 332                 phy_write(phydev, MDIO_MMD_VEND1,
 333                           AQUANTIA_VND1_GSYSCFG_BASE + i,
 334                           aquantia_syscfg[interface].syscfg);
 335         return 0;
 336 }
 337
 338 static int aquantia_dts_config(struct phy_device *phydev)
 339 {
 340         ofnode node = phydev->node;
 341         u32 prop;
 342         u16 reg;
 343
 344         /* this code only works on gen2 and gen3 PHYs */
 345         if (phydev->drv->data != AQUANTIA_GEN2 &&
 346             phydev->drv->data != AQUANTIA_GEN3)
 347                 return -ENOTSUPP;
 348
 349         if (!ofnode_valid(node))
 350                 return 0;
 351
 352         if (!ofnode_read_u32(node, "mdi-reversal", &prop)) {
 353                 debug("mdi-reversal = %d\n", (int)prop);
 354                 reg =  phy_read(phydev, MDIO_MMD_PMAPMD,
 355                                 AQUANTIA_PMA_RX_VENDOR_P1);
 356                 reg &= ~AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK;
 357                 reg |= AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG;
 358                 reg |= prop ? AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV : 0;
 359                 phy_write(phydev, MDIO_MMD_PMAPMD, AQUANTIA_PMA_RX_VENDOR_P1,
 360                           reg);
 361         }
 362         if (!ofnode_read_u32(node, "smb-addr", &prop)) {
 363                 debug("smb-addr = %x\n", (int)prop);
 364                 /*
 365                  * there are two addresses here, normally just one bus would
 366                  * be in use so we're setting both regs using the same DT
 367                  * property.
 368                  */
 369                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS0,
 370                           (u16)(prop << 1));
 371                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS1,
 372                           (u16)(prop << 1));
 373         }
 374
 375         return 0;
 376 }
 377
 378 static bool aquantia_link_is_up(struct phy_device *phydev)
 379 {
 380         u16 reg, regmask;
 381         int devad, regnum;
 382
 383         /*
 384          * On Gen 2 and 3 we have a bit that indicates that both system and
 385          * line side are ready for data, use that if possible.
 386          */
 387         if (phydev->drv->data == AQUANTIA_GEN2 ||
 388             phydev->drv->data == AQUANTIA_GEN3) {
 389                 devad = MDIO_MMD_PHYXS;
 390                 regnum = AQUANTIA_SYSTEM_INTERFACE_SR;
 391                 regmask = AQUANTIA_SYSTEM_INTERFACE_SR_READY;
 392         } else {
 393                 devad = MDIO_MMD_AN;
 394                 regnum = MDIO_STAT1;
 395                 regmask = MDIO_AN_STAT1_COMPLETE;
 396         }
 397         /* the register should be latched, do a double read */
 398         phy_read(phydev, devad, regnum);
 399         reg = phy_read(phydev, devad, regnum);
 400
 401         return !!(reg & regmask);
 402 }
 403
 404 int aquantia_config(struct phy_device *phydev)
 405 {
 406         int interface = phydev->interface;
 407         u32 val, id, rstatus, fault;
 408         u32 reg_val1 = 0;
 409         int num_retries = 5;
 410         int usx_an = 0;
 411
 412         /*
 413          * check if the system is out of reset and init sequence completed.
 414          * chip-wide reset for gen1 quad phys takes longer
 415          */
 416         while (--num_retries) {
 417                 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1);
 418                 if (rstatus & SYSTEM_READY_BIT)
 419                         break;
 420                 mdelay(10);
 421         }
 422
 423         id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
 424         rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
 425         fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT);
 426
 427         if (id != 0)
 428                 debug("%s running firmware version %X.%X.%X\n",
 429                       phydev->dev->name, (id >> 8), id & 0xff,
 430                       (rstatus >> 4) & 0xf);
 431
 432         if (fault != 0)
 433                 printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);
 434
 435         if (id == 0 || fault != 0) {
 436                 int ret;
 437
 438                 ret = aquantia_upload_firmware(phydev);
 439                 if (ret != 0)
 440                         return ret;
 441         }
 442         /*
 443          * for backward compatibility convert XGMII into either 10GBase-R or
 444          * USXGMII based on FW config
 445          */
 446         if (interface == PHY_INTERFACE_MODE_XGMII) {
 447                 debug("use 10GBase-R or USXGMII SI protos, XGMII is not valid\n");
 448
 449                 reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
 450                                     AQUANTIA_SYSTEM_INTERFACE_SR);
 451                 if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
 452                         interface = PHY_INTERFACE_MODE_USXGMII;
 453                 else
 454                         interface = PHY_INTERFACE_MODE_10GBASER;
 455         }
 456
 457         /*
 458          * if link is up already we can just use it, otherwise configure
 459          * the protocols in the PHY.  If link is down set the system
 460          * interface protocol to use based on phydev->interface
 461          */
 462         if (!aquantia_link_is_up(phydev) &&
 463             (phydev->drv->data == AQUANTIA_GEN2 ||
 464              phydev->drv->data == AQUANTIA_GEN3)) {
 465                 /* set PHY in low power mode so we can configure protocols */
 466                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,
 467                           AQUANTIA_VND1_GLOBAL_SC_LP);
 468                 mdelay(10);
 469
 470                 /* configure protocol based on phydev->interface */
 471                 aquantia_set_proto(phydev, interface);
 472                 /* apply custom configuration based on DT */
 473                 aquantia_dts_config(phydev);
 474
 475                 /* wake PHY back up */
 476                 phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
 477                 mdelay(10);
 478         }
 479
 480         val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 481
 482         switch (interface) {
 483         case PHY_INTERFACE_MODE_SGMII:
 484                 /* 1000BASE-T mode */
 485                 phydev->advertising = SUPPORTED_1000baseT_Full;
 486                 phydev->supported = phydev->advertising;
 487
 488                 val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
 489                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 490                 break;
 491         case PHY_INTERFACE_MODE_USXGMII:
 492                 usx_an = 1;
 493                 /* FALLTHROUGH */
 494         case PHY_INTERFACE_MODE_10GBASER:
 495                 /* 10GBASE-T mode */
 496                 phydev->advertising = SUPPORTED_10000baseT_Full;
 497                 phydev->supported = phydev->advertising;
 498
 499                 if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
 500                     !(val & AQUNTIA_SPEED_MSB_MASK))
 501                         phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
 502                                   AQUNTIA_SPEED_LSB_MASK |
 503                                   AQUNTIA_SPEED_MSB_MASK);
 504
 505                 /* If SI is USXGMII then start USXGMII autoneg */
 506                 reg_val1 =  phy_read(phydev, MDIO_MMD_PHYXS,
 507                                      AQUANTIA_VENDOR_PROVISIONING_REG);
 508
 509                 if (usx_an) {
 510                         reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
 511                         debug("%s: system interface USXGMII\n",
 512                               phydev->dev->name);
 513                 } else {
 514                         reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
 515                         debug("%s: system interface 10GBase-R\n",
 516                               phydev->dev->name);
 517                 }
 518
 519                 phy_write(phydev, MDIO_MMD_PHYXS,
 520                           AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
 521                 break;
 522         case PHY_INTERFACE_MODE_2500BASEX:
 523                 /* 2.5GBASE-T mode */
 524                 phydev->advertising = SUPPORTED_1000baseT_Full;
 525                 phydev->supported = phydev->advertising;
 526
 527                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
 528                 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
 529                 break;
 530         case PHY_INTERFACE_MODE_MII:
 531                 /* 100BASE-TX mode */
 532                 phydev->advertising = SUPPORTED_100baseT_Full;
 533                 phydev->supported = phydev->advertising;
 534
 535                 val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
 536                 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
 537                 break;
 538         };
 539
 540         val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
 541         reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
 542
 543         debug("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
 544               phydev->drv->name,
 545               (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
 546               reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
 547               (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
 548
 549         return 0;
 550 }
 551
 552 int aquantia_startup(struct phy_device *phydev)
 553 {
 554         u32 speed;
 555         int i = 0;
 556         int reg;
 557
 558         phydev->duplex = DUPLEX_FULL;
 559
 560         /* if the AN is still in progress, wait till timeout. */
 561         if (!aquantia_link_is_up(phydev)) {
 562                 printf("%s Waiting for PHY auto negotiation to complete",
 563                        phydev->dev->name);
 564                 do {
 565                         udelay(1000);
 566                         if ((i++ % 500) == 0)
 567                                 printf(".");
 568                 } while (!aquantia_link_is_up(phydev) &&
 569                          i < (4 * PHY_ANEG_TIMEOUT));
 570
 571                 if (i > PHY_ANEG_TIMEOUT)
 572                         printf(" TIMEOUT !\n");
 573         }
 574
 575         /* Read twice because link state is latched and a
 576          * read moves the current state into the register */
 577         phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 578         reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
 579         if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
 580                 phydev->link = 0;
 581         else
 582                 phydev->link = 1;
 583
 584         speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
 585         if (speed & AQUNTIA_SPEED_MSB_MASK) {
 586                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 587                         phydev->speed = SPEED_10000;
 588                 else
 589                         phydev->speed = SPEED_1000;
 590         } else {
 591                 if (speed & AQUNTIA_SPEED_LSB_MASK)
 592                         phydev->speed = SPEED_100;
 593                 else
 594                         phydev->speed = SPEED_10;
 595         }
 596
 597         return 0;
 598 }
 599
 600 U_BOOT_PHY_DRIVER(aq1202) = {
 601         .name = "Aquantia AQ1202",
 602         .uid = 0x3a1b445,
 603         .mask = 0xfffffff0,
 604         .features = PHY_10G_FEATURES,
 605         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 606                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 607                         MDIO_MMD_VEND1),
 608         .config = &aquantia_config,
 609         .startup = &aquantia_startup,
 610         .shutdown = &gen10g_shutdown,
 611 };
 612
 613 U_BOOT_PHY_DRIVER(aq2104) = {
 614         .name = "Aquantia AQ2104",
 615         .uid = 0x3a1b460,
 616         .mask = 0xfffffff0,
 617         .features = PHY_10G_FEATURES,
 618         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 619                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 620                         MDIO_MMD_VEND1),
 621         .config = &aquantia_config,
 622         .startup = &aquantia_startup,
 623         .shutdown = &gen10g_shutdown,
 624 };
 625
 626 U_BOOT_PHY_DRIVER(aqr105) = {
 627         .name = "Aquantia AQR105",
 628         .uid = 0x3a1b4a2,
 629         .mask = 0xfffffff0,
 630         .features = PHY_10G_FEATURES,
 631         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 632                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 633                         MDIO_MMD_VEND1),
 634         .config = &aquantia_config,
 635         .startup = &aquantia_startup,
 636         .shutdown = &gen10g_shutdown,
 637         .data = AQUANTIA_GEN1,
 638 };
 639
 640 U_BOOT_PHY_DRIVER(aqr106) = {
 641         .name = "Aquantia AQR106",
 642         .uid = 0x3a1b4d0,
 643         .mask = 0xfffffff0,
 644         .features = PHY_10G_FEATURES,
 645         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 646                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 647                         MDIO_MMD_VEND1),
 648         .config = &aquantia_config,
 649         .startup = &aquantia_startup,
 650         .shutdown = &gen10g_shutdown,
 651 };
 652
 653 U_BOOT_PHY_DRIVER(aqr107) = {
 654         .name = "Aquantia AQR107",
 655         .uid = 0x3a1b4e0,
 656         .mask = 0xfffffff0,
 657         .features = PHY_10G_FEATURES,
 658         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 659                         MDIO_MMD_PHYXS | MDIO_MMD_AN |
 660                         MDIO_MMD_VEND1),
 661         .config = &aquantia_config,
 662         .startup = &aquantia_startup,
 663         .shutdown = &gen10g_shutdown,
 664         .data = AQUANTIA_GEN2,
 665 };
 666
 667 U_BOOT_PHY_DRIVER(aqr112) = {
 668         .name = "Aquantia AQR112",
 669         .uid = 0x3a1b660,
 670         .mask = 0xfffffff0,
 671         .features = PHY_10G_FEATURES,
 672         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 673                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 674                  MDIO_MMD_VEND1),
 675         .config = &aquantia_config,
 676         .startup = &aquantia_startup,
 677         .shutdown = &gen10g_shutdown,
 678         .data = AQUANTIA_GEN3,
 679 };
 680
 681 U_BOOT_PHY_DRIVER(aqr113c) = {
 682         .name = "Aquantia AQR113C",
 683         .uid = 0x31c31c12,
 684         .mask = 0xfffffff0,
 685         .features = PHY_10G_FEATURES,
 686         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 687                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 688                  MDIO_MMD_VEND1),
 689         .config = &aquantia_config,
 690         .startup = &aquantia_startup,
 691         .shutdown = &gen10g_shutdown,
 692         .data = AQUANTIA_GEN3,
 693 };
 694
 695 U_BOOT_PHY_DRIVER(aqr405) = {
 696         .name = "Aquantia AQR405",
 697         .uid = 0x3a1b4b2,
 698         .mask = 0xfffffff0,
 699         .features = PHY_10G_FEATURES,
 700         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
 701                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 702                  MDIO_MMD_VEND1),
 703         .config = &aquantia_config,
 704         .startup = &aquantia_startup,
 705         .shutdown = &gen10g_shutdown,
 706         .data = AQUANTIA_GEN1,
 707 };
 708
 709 U_BOOT_PHY_DRIVER(aqr412) = {
 710         .name = "Aquantia AQR412",
 711         .uid = 0x3a1b710,
 712         .mask = 0xfffffff0,
 713         .features = PHY_10G_FEATURES,
 714         .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
 715                  MDIO_MMD_PHYXS | MDIO_MMD_AN |
 716                  MDIO_MMD_VEND1),
 717         .config = &aquantia_config,
 718         .startup = &aquantia_startup,
 719         .shutdown = &gen10g_shutdown,
 720         .data = AQUANTIA_GEN3,
 721 };