1 // SPDX-License-Identifier: GPL-2.0+
6 #include <asm-generic/gpio.h>
7 #include <asm-generic/sections.h>
8 #include <asm/arch/clock.h>
9 #include <asm/arch/ddr.h>
10 #include <asm/arch/sys_proto.h>
12 #include <asm/mach-imx/boot_mode.h>
13 #include <asm/mach-imx/iomux-v3.h>
14 #include <dm/uclass.h>
16 #include <i2c_eeprom.h>
22 #include <dm/uclass.h>
23 #include <dm/device.h>
24 #include <dm/uclass-internal.h>
25 #include <dm/device-internal.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
31 #define DDRC_ECCCFG0_ECC_MODE_MASK 0x7
33 u8 dmo_get_memcfg(void)
35 struct gpio_desc gpio[4];
40 node = ofnode_path("/config");
41 if (!ofnode_valid(node)) {
42 printf("%s: no /config node?\n", __func__);
43 return BIT(2) | BIT(0);
46 ret = gpio_request_list_by_name_nodev(node,
47 "dmo,ram-coding-gpios",
48 gpio, ARRAY_SIZE(gpio),
50 for (i = 0; i < ret; i++)
51 memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i;
53 gpio_free_list_nodev(gpio, ret);
58 int board_phys_sdram_size(phys_size_t *size)
60 u8 memcfg = dmo_get_memcfg();
63 *size = 4ULL >> ((memcfg >> 1) & 0x3);
65 if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) {
66 /* 896 MiB, i.e. 1 GiB without 12.5% reserved for in-band ECC */
67 ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK;
70 *size *= SZ_1G - (ecc ? (SZ_1G / 8) : 0);
75 #ifdef CONFIG_SPL_BUILD
76 static void data_modul_imx_edm_sbc_early_init_f(const iomux_v3_cfg_t wdog_pad)
78 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
80 imx_iomux_v3_setup_pad(wdog_pad | MUX_PAD_CTRL(WDOG_PAD_CTRL));
85 __weak int data_modul_imx_edm_sbc_board_power_init(void)
90 static void spl_dram_init(struct dram_timing_info *dram_timing_info[8])
92 u8 memcfg = dmo_get_memcfg();
95 printf("DDR: %d GiB x%d [0x%x]\n",
96 /* 0..4 GiB, 1..2 GiB, 0..1 GiB */
97 4 >> ((memcfg >> 1) & 0x3),
99 32 >> (memcfg & BIT(0)),
102 if (!dram_timing_info[memcfg]) {
103 printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n",
105 for (i = 7; i >= 0; i--)
106 if (dram_timing_info[i]) /* Configuration found */
110 ddr_init(dram_timing_info[memcfg]);
112 if (IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)) {
113 printf("DDR: Inline ECC %sabled\n",
114 (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ?
119 void dmo_board_init_f(const iomux_v3_cfg_t wdog_pad,
120 struct dram_timing_info *dram_timing_info[8])
131 data_modul_imx_edm_sbc_early_init_f(wdog_pad);
134 memset(__bss_start, 0, __bss_end - __bss_start);
136 ret = spl_early_init();
138 debug("spl_early_init() failed: %d\n", ret);
142 preloader_console_init();
144 ret = uclass_get_device_by_name(UCLASS_CLK,
145 "clock-controller@30380000",
148 printf("Failed to find clock node. Check device tree\n");
154 data_modul_imx_edm_sbc_board_power_init();
156 /* DDR initialization */
157 spl_dram_init(dram_timing_info);
159 board_init_r(NULL, 0);
162 void dmo_setup_boot_device(void)
164 int boot_device = get_boot_device();
167 devnum = env_get("devnum");
168 if (devnum) /* devnum is already set */
171 if (boot_device == MMC3_BOOT) /* eMMC */
172 env_set_ulong("devnum", 0);
174 env_set_ulong("devnum", 1);
177 void dmo_setup_mac_address(void)
179 unsigned char enetaddr[6];
183 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
184 if (ret) /* ethaddr is already set */
187 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
189 printf("%s: No eeprom0 path offset\n", __func__);
193 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
195 printf("Cannot find EEPROM!\n");
199 ret = i2c_eeprom_read(dev, 0xb0, enetaddr, 0x6);
201 printf("Error reading configuration EEPROM!\n");
205 if (is_valid_ethaddr(enetaddr))
206 eth_env_set_enetaddr("ethaddr", enetaddr);