[J-u-boot.git] / include / configs / ls1021atwr.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 * Copyright 2019 NXP
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

#define CONFIG_SYS_FSL_CLK

#define CONFIG_DEEP_SLEEP

#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE

#define CONFIG_SYS_CLK_FREQ		100000000

#define DDR_SDRAM_CFG			0x470c0008
#define DDR_CS0_BNDS			0x008000bf
#define DDR_CS0_CONFIG			0x80014302
#define DDR_TIMING_CFG_0		0x50550004
#define DDR_TIMING_CFG_1		0xbcb38c56
#define DDR_TIMING_CFG_2		0x0040d120
#define DDR_TIMING_CFG_3		0x010e1000
#define DDR_TIMING_CFG_4		0x00000001
#define DDR_TIMING_CFG_5		0x03401400
#define DDR_SDRAM_CFG_2			0x00401010
#define DDR_SDRAM_MODE			0x00061c60
#define DDR_SDRAM_MODE_2		0x00180000
#define DDR_SDRAM_INTERVAL		0x18600618
#define DDR_DDR_WRLVL_CNTL		0x8655f605
#define DDR_DDR_WRLVL_CNTL_2		0x05060607
#define DDR_DDR_WRLVL_CNTL_3		0x05050505
#define DDR_DDR_CDR1			0x80040000
#define DDR_DDR_CDR2			0x00000001
#define DDR_SDRAM_CLK_CNTL		0x02000000
#define DDR_DDR_ZQ_CNTL			0x89080600
#define DDR_CS0_CONFIG_2		0
#define DDR_SDRAM_CFG_MEM_EN		0x80000000
#define SDRAM_CFG2_D_INIT		0x00000010
#define DDR_CDR2_VREF_TRAIN_EN		0x00000080
#define SDRAM_CFG2_FRC_SR		0x80000000
#define SDRAM_CFG_BI			0x00000001

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_NXP_ESBC
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image.
 */
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
#endif /* ifdef CONFIG_NXP_ESBC */

#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
		CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif

#define PHYS_SDRAM			0x80000000
#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)

#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_CHIP_SELECTS_PER_CTRL	4

/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_FLASH_BASE		0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TAVDS(0x0) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1A) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWP(0x1c) | \
					FTIM2_NOR_TWPH(0x0e))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#endif

/* CPLD */

#define CONFIG_SYS_CPLD_BASE	0x7fb00000
#define CPLD_BASE_PHYS		CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
					FTIM0_GPCM_TEADC(0xf) | \
					FTIM0_GPCM_TEAHC(0xf))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0xff))
#define CONFIG_SYS_FPGA_FTIM3           0x0
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_FPGA_FTIM3

/*
 * Serial Port
 */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#endif
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#endif

/*
 * I2C
 */

/* GPIO */

/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		1

/*
 * MMC
 */

/*
 * Video
 */
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO

#define CONFIG_FSL_DCU_SII9022A
#define CONFIG_SYS_I2C_DVI_BUS_NUM	1
#define CONFIG_SYS_I2C_DVI_ADDR		0x39
#endif

/*
 * eTSEC
 */

#ifdef CONFIG_TSEC_ENET
#define CONFIG_ETHPRIME			"ethernet@2d10000"
#endif

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR		0x01ee0200
#define COUNTER_FREQUENCY		12500000

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		256

#define CONFIG_FSL_DEVICE_DISABLE

#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 0) \
	func(USB, usb, 0) \
	func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>

#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS       \
	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "	\
		"cma=64M@0x0-0xb0000000\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_addr=0x64f00000\0"		\
	"kernel_addr=0x65000000\0"	\
	"scriptaddr=0x80000000\0"	\
	"scripthdraddr=0x80080000\0"	\
	"fdtheader_addr_r=0x80100000\0"	\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"	\
	"fdt_addr_r=0x90000000\0"	\
	"ramdisk_addr_r=0xa0000000\0"	\
	"load_addr=0xa0000000\0"	\
	"kernel_size=0x2800000\0"	\
	"kernel_addr_sd=0x8000\0"	\
	"kernel_size_sd=0x14000\0"	\
	"othbootargs=cma=64M@0x0-0xb0000000\0"	\
	BOOTENV				\
	"boot_scripts=ls1021atwr_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1021atwr_bs.out\0"	\
		"scan_dev_for_boot_part="	\
			"part list ${devtype} ${devnum} devplist; "	\
			"env exists devplist || setenv devplist 1; "	\
			"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "				\
				"${devnum}:${distro_bootpart} "		\
				"bootfstype; then "			\
				"run scan_dev_for_boot; "		\
			"fi; "			\
		"done\0"			\
	"scan_dev_for_boot="				  \
		"echo Scanning ${devtype} "		  \
				"${devnum}:${distro_bootpart}...; "  \
		"for prefix in ${boot_prefixes}; do "	  \
			"run scan_dev_for_scripts; "	  \
		"done;"					  \
		"\0"					  \
	"boot_a_script="				  \
		"load ${devtype} ${devnum}:${distro_bootpart} "  \
			"${scriptaddr} ${prefix}${script}; "    \
		"env exists secureboot && load ${devtype} "     \
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
			"env exists secureboot "	\
			"&& esbc_validate ${scripthdraddr};"    \
		"source ${scriptaddr}\0"	  \
	"installer=load mmc 0:2 $load_addr "	\
		"/flex_installer_arm32.itb; "		\
		"bootm $load_addr#ls1021atwr\0"	\
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_addr $kernel_size && bootm $load_addr#$board\0"	\
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "		\
		"$kernel_size && bootm $load_addr#$board\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootargs=root=/dev/ram0 rw console=ttyS0,115200 "	\
		"cma=64M@0x0-0xb0000000\0" \
	"initrd_high=0xffffffff\0"      \
	"fdt_addr=0x64f00000\0"		\
	"kernel_addr=0x61000000\0"	\
	"kernelheader_addr=0x60800000\0"	\
	"scriptaddr=0x80000000\0"	\
	"scripthdraddr=0x80080000\0"	\
	"fdtheader_addr_r=0x80100000\0"	\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"	\
	"kernelheader_size=0x40000\0"	\
	"fdt_addr_r=0x90000000\0"	\
	"ramdisk_addr_r=0xa0000000\0"	\
	"load_addr=0xa0000000\0"	\
	"kernel_size=0x2800000\0"	\
	"kernel_addr_sd=0x8000\0"	\
	"kernel_size_sd=0x14000\0"	\
	"kernelhdr_addr_sd=0x4000\0"		\
	"kernelhdr_size_sd=0x10\0"		\
	"othbootargs=cma=64M@0x0-0xb0000000\0"	\
	BOOTENV				\
	"boot_scripts=ls1021atwr_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1021atwr_bs.out\0"	\
		"scan_dev_for_boot_part="	\
			"part list ${devtype} ${devnum} devplist; "	\
			"env exists devplist || setenv devplist 1; "	\
			"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "				\
				"${devnum}:${distro_bootpart} "		\
				"bootfstype; then "			\
				"run scan_dev_for_boot; "		\
			"fi; "			\
		"done\0"			\
	"scan_dev_for_boot="				  \
		"echo Scanning ${devtype} "		  \
				"${devnum}:${distro_bootpart}...; "  \
		"for prefix in ${boot_prefixes}; do "	  \
			"run scan_dev_for_scripts; "	  \
		"done;"					  \
		"\0"					  \
	"boot_a_script="				  \
		"load ${devtype} ${devnum}:${distro_bootpart} "  \
			"${scriptaddr} ${prefix}${script}; "    \
		"env exists secureboot && load ${devtype} "     \
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
			"&& esbc_validate ${scripthdraddr};"    \
		"source ${scriptaddr}\0"	  \
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_addr $kernel_size; env exists secureboot "	\
		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0" \
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "		\
		"$kernel_size; env exists secureboot "	\
		"&& cp.b $kernelheader_addr $kernelheader_addr_r "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"	\
	"sd_bootcmd=echo Trying load from SD ..;"       \
		"mmcinfo && mmc read $load_addr "	\
		"$kernel_addr_sd $kernel_size_sd && "	\
		"env exists secureboot && mmc read $kernelheader_addr_r "		\
		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$board\0"
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)

#define CONFIG_LS102XA_STREAM_ID

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

/*
 * Environment
 */

#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
c8a7d9da WH	2	/*
c8a7d9da WH	3	* Copyright 2014 Freescale Semiconductor, Inc.
9ebde884	4	* Copyright 2019 NXP
c8a7d9da WH	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
3288628a HZ	10	#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
3288628a HZ	11
18fb0e3c	12	#define CONFIG_SYS_FSL_CLK
c8a7d9da	13
99e1bd42	14	#define CONFIG_DEEP_SLEEP
c8a7d9da	15
c8a7d9da WH	16	#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
	17	#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
	18
c8a7d9da	19	#define CONFIG_SYS_CLK_FREQ 100000000
c8a7d9da	20
a88cc3bd YS	21	#define DDR_SDRAM_CFG 0x470c0008
	22	#define DDR_CS0_BNDS 0x008000bf
	23	#define DDR_CS0_CONFIG 0x80014302
	24	#define DDR_TIMING_CFG_0 0x50550004
	25	#define DDR_TIMING_CFG_1 0xbcb38c56
	26	#define DDR_TIMING_CFG_2 0x0040d120
	27	#define DDR_TIMING_CFG_3 0x010e1000
	28	#define DDR_TIMING_CFG_4 0x00000001
	29	#define DDR_TIMING_CFG_5 0x03401400
	30	#define DDR_SDRAM_CFG_2 0x00401010
	31	#define DDR_SDRAM_MODE 0x00061c60
	32	#define DDR_SDRAM_MODE_2 0x00180000
	33	#define DDR_SDRAM_INTERVAL 0x18600618
	34	#define DDR_DDR_WRLVL_CNTL 0x8655f605
	35	#define DDR_DDR_WRLVL_CNTL_2 0x05060607
	36	#define DDR_DDR_WRLVL_CNTL_3 0x05050505
	37	#define DDR_DDR_CDR1 0x80040000
	38	#define DDR_DDR_CDR2 0x00000001
	39	#define DDR_SDRAM_CLK_CNTL 0x02000000
	40	#define DDR_DDR_ZQ_CNTL 0x89080600
	41	#define DDR_CS0_CONFIG_2 0
	42	#define DDR_SDRAM_CFG_MEM_EN 0x80000000
99e1bd42 TY	43	#define SDRAM_CFG2_D_INIT 0x00000010
	44	#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
	45	#define SDRAM_CFG2_FRC_SR 0x80000000
	46	#define SDRAM_CFG_BI 0x00000001
a88cc3bd	47
8415bb68	48	#ifdef CONFIG_SD_BOOT
5536c3c9	49	#ifdef CONFIG_NXP_ESBC
e7e720c2 SG	50	/*
	51	* HDR would be appended at end of image and copied to DDR along
	52	* with U-Boot image.
	53	*/
693d4c9f	54	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
5536c3c9	55	#endif /* ifdef CONFIG_NXP_ESBC */
8415bb68	56
8415bb68 AW	57	#define CONFIG_SPL_MAX_SIZE 0x1a000
	58	#define CONFIG_SPL_STACK 0x1001d000
	59	#define CONFIG_SPL_PAD_TO 0x1c000
8415bb68	60
99e1bd42 TY	61	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
99e1bd42 TY	62	CONFIG_SYS_MONITOR_LEN)
8415bb68 AW	63	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	64	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	65	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
e7e720c2 SG	66
	67	#ifdef CONFIG_U_BOOT_HDR_SIZE
	68	/*
	69	* HDR would be appended at end of image and copied to DDR along
	70	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	71	* size increases then increase this size in case of secure boot as
	72	* it uses raw u-boot image instead of fit image.
	73	*/
9b6639fa	74	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
e7e720c2	75	#else
9b6639fa	76	#define CONFIG_SYS_MONITOR_LEN 0x100000
e7e720c2	77	#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
8415bb68 AW	78	#endif
8415bb68 AW	79
c8a7d9da WH	80	#define PHYS_SDRAM 0x80000000
	81	#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
	82
	83	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	84	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	85
15809705 AW	86	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
15809705 AW	87
c8a7d9da WH	88	/*
	89	* IFC Definitions
	90	*/
947cee11	91	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
c8a7d9da WH	92	#define CONFIG_SYS_FLASH_BASE 0x60000000
	93	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	94
	95	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	96	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	97	CSPR_PORT_SIZE_16 \| \
	98	CSPR_MSEL_NOR \| \
	99	CSPR_V)
	100	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	101
	102	/* NOR Flash Timing Params */
	103	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	104	CSOR_NOR_TRHZ_80)
	105	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	106	FTIM0_NOR_TEADC(0x5) \| \
	107	FTIM0_NOR_TAVDS(0x0) \| \
	108	FTIM0_NOR_TEAHC(0x5))
	109	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	110	FTIM1_NOR_TRAD_NOR(0x1A) \| \
	111	FTIM1_NOR_TSEQRAD_NOR(0x13))
	112	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	113	FTIM2_NOR_TCH(0x4) \| \
	114	FTIM2_NOR_TWP(0x1c) \| \
	115	FTIM2_NOR_TWPH(0x0e))
	116	#define CONFIG_SYS_NOR_FTIM3 0
	117
c8a7d9da WH	118	#define CONFIG_SYS_FLASH_QUIET_TEST
	119	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	120
	121	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	122	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	123	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	124	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	125
	126	#define CONFIG_SYS_FLASH_EMPTY_INFO
	127	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
	128
	129	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
272c5265	130	#define CONFIG_SYS_WRITE_SWAPPED_DATA
d612f0ab	131	#endif
c8a7d9da WH	132
	133	/* CPLD */
	134
	135	#define CONFIG_SYS_CPLD_BASE 0x7fb00000
	136	#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
	137
	138	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	139	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) \| \
	140	CSPR_PORT_SIZE_8 \| \
	141	CSPR_MSEL_GPCM \| \
	142	CSPR_V)
	143	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	144	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	145	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	146	CSOR_NOR_TRHZ_80)
	147
	148	/* CPLD Timing parameters for IFC GPCM */
	149	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) \| \
	150	FTIM0_GPCM_TEADC(0xf) \| \
	151	FTIM0_GPCM_TEAHC(0xf))
	152	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	153	FTIM1_GPCM_TRAD(0x3f))
	154	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	155	FTIM2_GPCM_TCH(0xf) \| \
	156	FTIM2_GPCM_TWP(0xff))
	157	#define CONFIG_SYS_FPGA_FTIM3 0x0
	158	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	159	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	160	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	161	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	162	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	163	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	164	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	165	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	166	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
	167	#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
	168	#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
	169	#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
	170	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
	171	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
	172	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
	173	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
	174
	175	/*
	176	* Serial Port
	177	*/
55d53ab4	178	#ifdef CONFIG_LPUART
55d53ab4 AW	179	#define CONFIG_LPUART_32B_REG
55d53ab4 AW	180	#else
c8a7d9da	181	#define CONFIG_SYS_NS16550_SERIAL
f833cd62	182	#ifndef CONFIG_DM_SERIAL
c8a7d9da	183	#define CONFIG_SYS_NS16550_REG_SIZE 1
f833cd62	184	#endif
c8a7d9da	185	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
55d53ab4	186	#endif
c8a7d9da	187
c8a7d9da WH	188	/*
	189	* I2C
	190	*/
c8a7d9da	191
7c1f095a	192	/* GPIO */
7c1f095a	193
5175a288	194	/* EEPROM */
5175a288 AW	195	#define CONFIG_SYS_I2C_EEPROM_NXID
5175a288 AW	196	#define CONFIG_SYS_EEPROM_BUS_NUM 1
5175a288	197
c8a7d9da WH	198	/*
	199	* MMC
	200	*/
c8a7d9da	201
b4ecc8c6 WH	202	/*
	203	* Video
	204	*/
b215fb3f	205	#ifdef CONFIG_VIDEO_FSL_DCU_FB
b4ecc8c6 WH	206	#define CONFIG_VIDEO_LOGO
	207	#define CONFIG_VIDEO_BMP_LOGO
	208
	209	#define CONFIG_FSL_DCU_SII9022A
	210	#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
	211	#define CONFIG_SYS_I2C_DVI_ADDR 0x39
	212	#endif
	213
c8a7d9da WH	214	/*
	215	* eTSEC
	216	*/
c8a7d9da WH	217
c8a7d9da WH	218	#ifdef CONFIG_TSEC_ENET
f588b4d2	219	#define CONFIG_ETHPRIME "ethernet@2d10000"
c8a7d9da WH	220	#endif
c8a7d9da WH	221
da419027	222	/* PCIe */
b38eaec5 RD	223	#define CONFIG_PCIE1 /* PCIE controller 1 */
b38eaec5 RD	224	#define CONFIG_PCIE2 /* PCIE controller 2 */
da419027	225
180b8688	226	#ifdef CONFIG_PCI
180b8688	227	#define CONFIG_PCI_SCAN_SHOW
180b8688 ML	228	#endif
180b8688 ML	229
1a2826f6	230	#define CONFIG_PEN_ADDR_BIG_ENDIAN
435acd83	231	#define CONFIG_LAYERSCAPE_NS_ACCESS
1a2826f6	232	#define CONFIG_SMP_PEN_ADDR 0x01ee0200
e4916e85	233	#define COUNTER_FREQUENCY 12500000
1a2826f6	234
c8a7d9da	235	#define CONFIG_HWCONFIG
03c22449 ZZ	236	#define HWCONFIG_BUFFER_SIZE 256
	237
	238	#define CONFIG_FSL_DEVICE_DISABLE
c8a7d9da	239
a65d7408 AW	240	#define BOOT_TARGET_DEVICES(func) \
a65d7408 AW	241	func(MMC, mmc, 0) \
d2c49aad YD	242	func(USB, usb, 0) \
d2c49aad YD	243	func(DHCP, dhcp, na)
a65d7408	244	#include <config_distro_bootcmd.h>
c8a7d9da	245
55d53ab4 AW	246	#ifdef CONFIG_LPUART
55d53ab4 AW	247	#define CONFIG_EXTRA_ENV_SETTINGS \
33c3dfd2 AW	248	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
33c3dfd2 AW	249	"cma=64M@0x0-0xb0000000\0" \
7ff7166c	250	"initrd_high=0xffffffff\0" \
a65d7408 AW	251	"fdt_addr=0x64f00000\0" \
	252	"kernel_addr=0x65000000\0" \
	253	"scriptaddr=0x80000000\0" \
b8ae6798	254	"scripthdraddr=0x80080000\0" \
a65d7408 AW	255	"fdtheader_addr_r=0x80100000\0" \
	256	"kernelheader_addr_r=0x80200000\0" \
	257	"kernel_addr_r=0x81000000\0" \
	258	"fdt_addr_r=0x90000000\0" \
	259	"ramdisk_addr_r=0xa0000000\0" \
	260	"load_addr=0xa0000000\0" \
	261	"kernel_size=0x2800000\0" \
397a173e SL	262	"kernel_addr_sd=0x8000\0" \
397a173e SL	263	"kernel_size_sd=0x14000\0" \
feb8fa2e	264	"othbootargs=cma=64M@0x0-0xb0000000\0" \
a65d7408 AW	265	BOOTENV \
a65d7408 AW	266	"boot_scripts=ls1021atwr_boot.scr\0" \
b8ae6798	267	"boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
a65d7408 AW	268	"scan_dev_for_boot_part=" \
	269	"part list ${devtype} ${devnum} devplist; " \
	270	"env exists devplist \|\| setenv devplist 1; " \
	271	"for distro_bootpart in ${devplist}; do " \
	272	"if fstype ${devtype} " \
	273	"${devnum}:${distro_bootpart} " \
	274	"bootfstype; then " \
	275	"run scan_dev_for_boot; " \
	276	"fi; " \
	277	"done\0" \
b8ae6798 SG	278	"scan_dev_for_boot=" \
	279	"echo Scanning ${devtype} " \
	280	"${devnum}:${distro_bootpart}...; " \
	281	"for prefix in ${boot_prefixes}; do " \
	282	"run scan_dev_for_scripts; " \
	283	"done;" \
	284	"\0" \
	285	"boot_a_script=" \
	286	"load ${devtype} ${devnum}:${distro_bootpart} " \
	287	"${scriptaddr} ${prefix}${script}; " \
	288	"env exists secureboot && load ${devtype} " \
	289	"${devnum}:${distro_bootpart} " \
78c58082 VP	290	"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
78c58082 VP	291	"env exists secureboot " \
b8ae6798 SG	292	"&& esbc_validate ${scripthdraddr};" \
b8ae6798 SG	293	"source ${scriptaddr}\0" \
a65d7408 AW	294	"installer=load mmc 0:2 $load_addr " \
	295	"/flex_installer_arm32.itb; " \
	296	"bootm $load_addr#ls1021atwr\0" \
	297	"qspi_bootcmd=echo Trying load from qspi..;" \
	298	"sf probe && sf read $load_addr " \
	299	"$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
	300	"nor_bootcmd=echo Trying load from nor..;" \
	301	"cp.b $kernel_addr $load_addr " \
	302	"$kernel_size && bootm $load_addr#$board\0"
55d53ab4	303	#else
c8a7d9da	304	#define CONFIG_EXTRA_ENV_SETTINGS \
33c3dfd2 AW	305	"bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
33c3dfd2 AW	306	"cma=64M@0x0-0xb0000000\0" \
7ff7166c	307	"initrd_high=0xffffffff\0" \
a65d7408	308	"fdt_addr=0x64f00000\0" \
9b457cc6 VPB	309	"kernel_addr=0x61000000\0" \
9b457cc6 VPB	310	"kernelheader_addr=0x60800000\0" \
a65d7408	311	"scriptaddr=0x80000000\0" \
b8ae6798	312	"scripthdraddr=0x80080000\0" \
a65d7408 AW	313	"fdtheader_addr_r=0x80100000\0" \
	314	"kernelheader_addr_r=0x80200000\0" \
	315	"kernel_addr_r=0x81000000\0" \
9b457cc6	316	"kernelheader_size=0x40000\0" \
a65d7408 AW	317	"fdt_addr_r=0x90000000\0" \
	318	"ramdisk_addr_r=0xa0000000\0" \
	319	"load_addr=0xa0000000\0" \
	320	"kernel_size=0x2800000\0" \
9b457cc6 VPB	321	"kernel_addr_sd=0x8000\0" \
	322	"kernel_size_sd=0x14000\0" \
	323	"kernelhdr_addr_sd=0x4000\0" \
	324	"kernelhdr_size_sd=0x10\0" \
feb8fa2e	325	"othbootargs=cma=64M@0x0-0xb0000000\0" \
a65d7408 AW	326	BOOTENV \
a65d7408 AW	327	"boot_scripts=ls1021atwr_boot.scr\0" \
b8ae6798	328	"boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
a65d7408 AW	329	"scan_dev_for_boot_part=" \
	330	"part list ${devtype} ${devnum} devplist; " \
	331	"env exists devplist \|\| setenv devplist 1; " \
	332	"for distro_bootpart in ${devplist}; do " \
	333	"if fstype ${devtype} " \
	334	"${devnum}:${distro_bootpart} " \
	335	"bootfstype; then " \
	336	"run scan_dev_for_boot; " \
	337	"fi; " \
	338	"done\0" \
b8ae6798 SG	339	"scan_dev_for_boot=" \
	340	"echo Scanning ${devtype} " \
	341	"${devnum}:${distro_bootpart}...; " \
	342	"for prefix in ${boot_prefixes}; do " \
	343	"run scan_dev_for_scripts; " \
	344	"done;" \
	345	"\0" \
	346	"boot_a_script=" \
	347	"load ${devtype} ${devnum}:${distro_bootpart} " \
	348	"${scriptaddr} ${prefix}${script}; " \
	349	"env exists secureboot && load ${devtype} " \
	350	"${devnum}:${distro_bootpart} " \
	351	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	352	"&& esbc_validate ${scripthdraddr};" \
	353	"source ${scriptaddr}\0" \
a65d7408 AW	354	"qspi_bootcmd=echo Trying load from qspi..;" \
a65d7408 AW	355	"sf probe && sf read $load_addr " \
9b457cc6 VPB	356	"$kernel_addr $kernel_size; env exists secureboot " \
	357	"&& sf read $kernelheader_addr_r $kernelheader_addr " \
	358	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	359	"bootm $load_addr#$board\0" \
a65d7408 AW	360	"nor_bootcmd=echo Trying load from nor..;" \
a65d7408 AW	361	"cp.b $kernel_addr $load_addr " \
9b457cc6 VPB	362	"$kernel_size; env exists secureboot " \
	363	"&& cp.b $kernelheader_addr $kernelheader_addr_r " \
	364	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	365	"bootm $load_addr#$board\0" \
397a173e SL	366	"sd_bootcmd=echo Trying load from SD ..;" \
	367	"mmcinfo && mmc read $load_addr " \
	368	"$kernel_addr_sd $kernel_size_sd && " \
9b457cc6 VPB	369	"env exists secureboot && mmc read $kernelheader_addr_r " \
	370	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	371	" && esbc_validate ${kernelheader_addr_r};" \
397a173e	372	"bootm $load_addr#$board\0"
55d53ab4	373	#endif
c8a7d9da WH	374
	375	/*
	376	* Miscellaneous configurable options
	377	*/
c463eeb4	378	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
c8a7d9da	379
660673af XL	380	#define CONFIG_LS102XA_STREAM_ID
660673af XL	381
c8a7d9da WH	382	#define CONFIG_SYS_INIT_SP_OFFSET \
	383	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	384	#define CONFIG_SYS_INIT_SP_ADDR \
	385	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	386
8415bb68 AW	387	#ifdef CONFIG_SPL_BUILD
	388	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	389	#else
c8a7d9da	390	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
8415bb68	391	#endif
c8a7d9da WH	392
	393	/*
	394	* Environment
	395	*/
c8a7d9da	396
ef6c55a2	397	#include <asm/fsl_secure_boot.h>
cc7b8b9a	398	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
4ba4a095	399
c8a7d9da	400	#endif