[J-u-boot.git] / include / configs / ls1021atwr.h

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <config_cmd_default.h>

#define CONFIG_LS102XA

#define CONFIG_SYS_GENERIC_BOARD

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)

#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE

/*
 * Generic Timer Definitions
 */
#define GENERIC_TIMER_CLK		12500000

#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021atwr/ls102xa_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_FSL_PBL_RCW	board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT	"arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0xe8
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x400

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000
#define CONFIG_SYS_TEXT_BASE		0x82000000

#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_MONITOR_LEN		0x80000
#endif

#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_TEXT_BASE		0x40010000
#define CONFIG_SYS_NO_FLASH
#endif

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0x67f80000
#endif

#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			0x80000000
#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)

#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_SYS_HAS_SERDES

#define CONFIG_FSL_CAAM			/* Enable CAAM */

#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
	!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#endif

/*
 * IFC Definitions
 */
#ifndef CONFIG_QSPI_BOOT
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE		0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TAVDS(0x0) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1A) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWP(0x1c) | \
					FTIM2_NOR_TWPH(0x0e))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#endif

/* CPLD */

#define CONFIG_SYS_CPLD_BASE	0x7fb00000
#define CPLD_BASE_PHYS		CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
					FTIM0_GPCM_TEADC(0xf) | \
					FTIM0_GPCM_TEAHC(0xf))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0xff))
#define CONFIG_SYS_FPGA_FTIM3           0x0
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_FPGA_FTIM3

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#define CONFIG_BAUDRATE			115200

/*
 * I2C
 */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC

/* EEPROM */
#ifndef CONFIG_SD_BOOT
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		1
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
#endif

/*
 * MMC
 */
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_GENERIC_MMC

#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION

/* QSPI */
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE			0x40000000
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2

#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#endif

/*
 * Video
 */
#define CONFIG_FSL_DCU_FB

#ifdef CONFIG_FSL_DCU_FB
#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO

#define CONFIG_FSL_DCU_SII9022A
#define CONFIG_SYS_I2C_DVI_BUS_NUM	1
#define CONFIG_SYS_I2C_DVI_ADDR		0x39
#endif

/*
 * eTSEC
 */
#define CONFIG_TSEC_ENET

#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII
#define CONFIG_MII_DEFAULT_TSEC		1
#define CONFIG_TSEC1			1
#define CONFIG_TSEC1_NAME		"eTSEC1"
#define CONFIG_TSEC2			1
#define CONFIG_TSEC2_NAME		"eTSEC2"
#define CONFIG_TSEC3			1
#define CONFIG_TSEC3_NAME		"eTSEC3"

#define TSEC1_PHY_ADDR			2
#define TSEC2_PHY_ADDR			0
#define TSEC3_PHY_ADDR			1

#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX			0
#define TSEC2_PHYIDX			0
#define TSEC3_PHYIDX			0

#define CONFIG_ETHPRIME			"eTSEC1"

#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif

/* PCIe */
#define CONFIG_PCI		/* Enable PCI/PCIE */
#define CONFIG_PCIE1		/* PCIE controler 1 */
#define CONFIG_PCIE2		/* PCIE controler 2 */
#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"

#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET

#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING

#ifdef CONFIG_QSPI_BOOT
#undef CONFIG_CMD_IMLS
#else
#define CONFIG_CMD_IMLS
#endif

#define CONFIG_ARMV7_NONSEC
#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LS102XA_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR		0x01ee0200
#define CONFIG_TIMER_CLK_FREQ		12500000
#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#define CONFIG_BOOTDELAY		3

#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
	"initrd_high=0xcfffffff\0"      \
	"fdt_high=0xcfffffff\0"

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_CMD_ENV_EXISTS
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x9fffffff

#define CONFIG_SYS_LOAD_ADDR		0x82000000

#define CONFIG_LS102XA_STREAM_ID

/*
 * Stack sizes
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE		(30 * 1024)

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

#define CONFIG_SYS_QE_FW_ADDR     0x67f40000

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET		0x100000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			0x20000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		0x100000
#define CONFIG_ENV_SECT_SIZE		0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE			0x20000
#define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
#endif

#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_CMD_BOOTZ

#define CONFIG_MISC_INIT_R

/* Hash command with SHA acceleration supported in hardware */
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL

#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CMD_BLOB
#endif

#endif
Commit	Line	Data
c8a7d9da WH	1	/*
	2	* Copyright 2014 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
	10	#include <config_cmd_default.h>
	11
	12	#define CONFIG_LS102XA
	13
	14	#define CONFIG_SYS_GENERIC_BOARD
	15
	16	#define CONFIG_DISPLAY_CPUINFO
	17	#define CONFIG_DISPLAY_BOARDINFO
	18
	19	#define CONFIG_SKIP_LOWLEVEL_INIT
	20	#define CONFIG_BOARD_EARLY_INIT_F
	21
	22	/*
	23	* Size of malloc() pool
	24	*/
	25	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
	26
	27	#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
	28	#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
	29
	30	/*
	31	* Generic Timer Definitions
	32	*/
	33	#define GENERIC_TIMER_CLK 12500000
	34
	35	#define CONFIG_SYS_CLK_FREQ 100000000
	36	#define CONFIG_DDR_CLK_FREQ 100000000
	37
8415bb68 AW	38	#ifdef CONFIG_RAMBOOT_PBL
	39	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
	40	#endif
	41
	42	#ifdef CONFIG_SD_BOOT
	43	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
	44	#define CONFIG_SPL_FRAMEWORK
	45	#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
	46	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	47	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	48	#define CONFIG_SPL_ENV_SUPPORT
	49	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	50	#define CONFIG_SPL_I2C_SUPPORT
	51	#define CONFIG_SPL_WATCHDOG_SUPPORT
	52	#define CONFIG_SPL_SERIAL_SUPPORT
	53	#define CONFIG_SPL_MMC_SUPPORT
	54	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
	55	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
	56
	57	#define CONFIG_SPL_TEXT_BASE 0x10000000
	58	#define CONFIG_SPL_MAX_SIZE 0x1a000
	59	#define CONFIG_SPL_STACK 0x1001d000
	60	#define CONFIG_SPL_PAD_TO 0x1c000
	61	#define CONFIG_SYS_TEXT_BASE 0x82000000
	62
	63	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	64	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	65	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	66	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	67	#define CONFIG_SYS_MONITOR_LEN 0x80000
	68	#endif
	69
d612f0ab AW	70	#ifdef CONFIG_QSPI_BOOT
	71	#define CONFIG_SYS_TEXT_BASE 0x40010000
	72	#define CONFIG_SYS_NO_FLASH
	73	#endif
	74
c8a7d9da WH	75	#ifndef CONFIG_SYS_TEXT_BASE
	76	#define CONFIG_SYS_TEXT_BASE 0x67f80000
	77	#endif
	78
	79	#define CONFIG_NR_DRAM_BANKS 1
	80	#define PHYS_SDRAM 0x80000000
	81	#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
	82
	83	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	84	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	85
	86	#define CONFIG_SYS_HAS_SERDES
	87
4ba4a095 RG	88	#define CONFIG_FSL_CAAM /* Enable CAAM */
4ba4a095 RG	89
4c59ab9c AW	90	#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
4c59ab9c AW	91	!defined(CONFIG_QSPI_BOOT)
eaa859e7 ZQ	92	#define CONFIG_U_QE
	93	#endif
	94
c8a7d9da WH	95	/*
	96	* IFC Definitions
	97	*/
d612f0ab	98	#ifndef CONFIG_QSPI_BOOT
c8a7d9da WH	99	#define CONFIG_FSL_IFC
	100	#define CONFIG_SYS_FLASH_BASE 0x60000000
	101	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	102
	103	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	104	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	105	CSPR_PORT_SIZE_16 \| \
	106	CSPR_MSEL_NOR \| \
	107	CSPR_V)
	108	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	109
	110	/* NOR Flash Timing Params */
	111	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	112	CSOR_NOR_TRHZ_80)
	113	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	114	FTIM0_NOR_TEADC(0x5) \| \
	115	FTIM0_NOR_TAVDS(0x0) \| \
	116	FTIM0_NOR_TEAHC(0x5))
	117	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	118	FTIM1_NOR_TRAD_NOR(0x1A) \| \
	119	FTIM1_NOR_TSEQRAD_NOR(0x13))
	120	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	121	FTIM2_NOR_TCH(0x4) \| \
	122	FTIM2_NOR_TWP(0x1c) \| \
	123	FTIM2_NOR_TWPH(0x0e))
	124	#define CONFIG_SYS_NOR_FTIM3 0
	125
	126	#define CONFIG_FLASH_CFI_DRIVER
	127	#define CONFIG_SYS_FLASH_CFI
	128	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	129	#define CONFIG_SYS_FLASH_QUIET_TEST
	130	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	131
	132	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	133	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	134	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	135	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	136
	137	#define CONFIG_SYS_FLASH_EMPTY_INFO
	138	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
	139
	140	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
272c5265	141	#define CONFIG_SYS_WRITE_SWAPPED_DATA
d612f0ab	142	#endif
c8a7d9da WH	143
	144	/* CPLD */
	145
	146	#define CONFIG_SYS_CPLD_BASE 0x7fb00000
	147	#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
	148
	149	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	150	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) \| \
	151	CSPR_PORT_SIZE_8 \| \
	152	CSPR_MSEL_GPCM \| \
	153	CSPR_V)
	154	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	155	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	156	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	157	CSOR_NOR_TRHZ_80)
	158
	159	/* CPLD Timing parameters for IFC GPCM */
	160	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) \| \
	161	FTIM0_GPCM_TEADC(0xf) \| \
	162	FTIM0_GPCM_TEAHC(0xf))
	163	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	164	FTIM1_GPCM_TRAD(0x3f))
	165	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	166	FTIM2_GPCM_TCH(0xf) \| \
	167	FTIM2_GPCM_TWP(0xff))
	168	#define CONFIG_SYS_FPGA_FTIM3 0x0
	169	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	170	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	171	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	172	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	173	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	174	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	175	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	176	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	177	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
	178	#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
	179	#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
	180	#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
	181	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
	182	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
	183	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
	184	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
	185
	186	/*
	187	* Serial Port
	188	*/
	189	#define CONFIG_CONS_INDEX 1
	190	#define CONFIG_SYS_NS16550
	191	#define CONFIG_SYS_NS16550_SERIAL
	192	#define CONFIG_SYS_NS16550_REG_SIZE 1
	193	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	194
	195	#define CONFIG_BAUDRATE 115200
	196
	197	/*
	198	* I2C
	199	*/
	200	#define CONFIG_CMD_I2C
	201	#define CONFIG_SYS_I2C
	202	#define CONFIG_SYS_I2C_MXC
	203
5175a288 AW	204	/* EEPROM */
	205	#ifndef CONFIG_SD_BOOT
	206	#define CONFIG_ID_EEPROM
	207	#define CONFIG_SYS_I2C_EEPROM_NXID
	208	#define CONFIG_SYS_EEPROM_BUS_NUM 1
	209	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
	210	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	211	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	212	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	213	#endif
	214
c8a7d9da WH	215	/*
	216	* MMC
	217	*/
	218	#define CONFIG_MMC
	219	#define CONFIG_CMD_MMC
	220	#define CONFIG_FSL_ESDHC
	221	#define CONFIG_GENERIC_MMC
	222
8251ed23 AW	223	#define CONFIG_CMD_FAT
	224	#define CONFIG_DOS_PARTITION
	225
d612f0ab AW	226	/* QSPI */
	227	#ifdef CONFIG_QSPI_BOOT
	228	#define CONFIG_FSL_QSPI
	229	#define QSPI0_AMBA_BASE 0x40000000
	230	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	231	#define FSL_QSPI_FLASH_NUM 2
	232
	233	#define CONFIG_CMD_SF
	234	#define CONFIG_SPI_FLASH
	235	#define CONFIG_SPI_FLASH_STMICRO
	236	#endif
	237
b4ecc8c6 WH	238	/*
	239	* Video
	240	*/
	241	#define CONFIG_FSL_DCU_FB
	242
	243	#ifdef CONFIG_FSL_DCU_FB
	244	#define CONFIG_VIDEO
	245	#define CONFIG_CMD_BMP
	246	#define CONFIG_CFB_CONSOLE
	247	#define CONFIG_VGA_AS_SINGLE_DEVICE
	248	#define CONFIG_VIDEO_LOGO
	249	#define CONFIG_VIDEO_BMP_LOGO
	250
	251	#define CONFIG_FSL_DCU_SII9022A
	252	#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
	253	#define CONFIG_SYS_I2C_DVI_ADDR 0x39
	254	#endif
	255
c8a7d9da WH	256	/*
	257	* eTSEC
	258	*/
	259	#define CONFIG_TSEC_ENET
	260
	261	#ifdef CONFIG_TSEC_ENET
	262	#define CONFIG_MII
	263	#define CONFIG_MII_DEFAULT_TSEC 1
	264	#define CONFIG_TSEC1 1
	265	#define CONFIG_TSEC1_NAME "eTSEC1"
	266	#define CONFIG_TSEC2 1
	267	#define CONFIG_TSEC2_NAME "eTSEC2"
	268	#define CONFIG_TSEC3 1
	269	#define CONFIG_TSEC3_NAME "eTSEC3"
	270
	271	#define TSEC1_PHY_ADDR 2
	272	#define TSEC2_PHY_ADDR 0
	273	#define TSEC3_PHY_ADDR 1
	274
	275	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	276	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	277	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	278
	279	#define TSEC1_PHYIDX 0
	280	#define TSEC2_PHYIDX 0
	281	#define TSEC3_PHYIDX 0
	282
	283	#define CONFIG_ETHPRIME "eTSEC1"
	284
	285	#define CONFIG_PHY_GIGE
	286	#define CONFIG_PHYLIB
	287	#define CONFIG_PHY_ATHEROS
	288
	289	#define CONFIG_HAS_ETH0
	290	#define CONFIG_HAS_ETH1
	291	#define CONFIG_HAS_ETH2
	292	#endif
	293
da419027 ML	294	/* PCIe */
	295	#define CONFIG_PCI /* Enable PCI/PCIE */
	296	#define CONFIG_PCIE1 /* PCIE controler 1 */
	297	#define CONFIG_PCIE2 /* PCIE controler 2 */
	298	#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
	299	#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
	300
c8a7d9da WH	301	#define CONFIG_CMD_PING
	302	#define CONFIG_CMD_DHCP
	303	#define CONFIG_CMD_MII
	304	#define CONFIG_CMD_NET
	305
	306	#define CONFIG_CMDLINE_TAG
	307	#define CONFIG_CMDLINE_EDITING
8415bb68	308
d612f0ab AW	309	#ifdef CONFIG_QSPI_BOOT
	310	#undef CONFIG_CMD_IMLS
	311	#else
c8a7d9da	312	#define CONFIG_CMD_IMLS
d612f0ab	313	#endif
c8a7d9da	314
1a2826f6 XL	315	#define CONFIG_ARMV7_NONSEC
	316	#define CONFIG_ARMV7_VIRT
	317	#define CONFIG_PEN_ADDR_BIG_ENDIAN
e87f3b30	318	#define CONFIG_LS102XA_NS_ACCESS
1a2826f6 XL	319	#define CONFIG_SMP_PEN_ADDR 0x01ee0200
	320	#define CONFIG_TIMER_CLK_FREQ 12500000
	321	#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
	322
c8a7d9da WH	323	#define CONFIG_HWCONFIG
	324	#define HWCONFIG_BUFFER_SIZE 128
	325
	326	#define CONFIG_BOOTDELAY 3
	327
	328	#define CONFIG_EXTRA_ENV_SETTINGS \
	329	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
	330	"initrd_high=0xcfffffff\0" \
	331	"fdt_high=0xcfffffff\0"
	332
	333	/*
	334	* Miscellaneous configurable options
	335	*/
	336	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	337	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	338	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
c8a7d9da WH	339	#define CONFIG_AUTO_COMPLETE
	340	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	341	#define CONFIG_SYS_PBSIZE \
	342	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	343	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	344	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	345
	346	#define CONFIG_CMD_ENV_EXISTS
	347	#define CONFIG_CMD_GREPENV
	348	#define CONFIG_CMD_MEMINFO
	349	#define CONFIG_CMD_MEMTEST
	350	#define CONFIG_SYS_MEMTEST_START 0x80000000
	351	#define CONFIG_SYS_MEMTEST_END 0x9fffffff
	352
	353	#define CONFIG_SYS_LOAD_ADDR 0x82000000
c8a7d9da	354
660673af XL	355	#define CONFIG_LS102XA_STREAM_ID
660673af XL	356
c8a7d9da WH	357	/*
	358	* Stack sizes
	359	* The stack sizes are set up in start.S using the settings below
	360	*/
	361	#define CONFIG_STACKSIZE (30 * 1024)
	362
	363	#define CONFIG_SYS_INIT_SP_OFFSET \
	364	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	365	#define CONFIG_SYS_INIT_SP_ADDR \
	366	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	367
8415bb68 AW	368	#ifdef CONFIG_SPL_BUILD
	369	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	370	#else
c8a7d9da	371	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
8415bb68	372	#endif
c8a7d9da	373
eaa859e7 ZQ	374	#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
eaa859e7 ZQ	375
c8a7d9da WH	376	/*
	377	* Environment
	378	*/
	379	#define CONFIG_ENV_OVERWRITE
	380
8415bb68 AW	381	#if defined(CONFIG_SD_BOOT)
	382	#define CONFIG_ENV_OFFSET 0x100000
	383	#define CONFIG_ENV_IS_IN_MMC
	384	#define CONFIG_SYS_MMC_ENV_DEV 0
	385	#define CONFIG_ENV_SIZE 0x20000
d612f0ab AW	386	#elif defined(CONFIG_QSPI_BOOT)
	387	#define CONFIG_ENV_IS_IN_SPI_FLASH
	388	#define CONFIG_ENV_SIZE 0x2000
	389	#define CONFIG_ENV_OFFSET 0x100000
	390	#define CONFIG_ENV_SECT_SIZE 0x10000
8415bb68	391	#else
c8a7d9da WH	392	#define CONFIG_ENV_IS_IN_FLASH
	393	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
	394	#define CONFIG_ENV_SIZE 0x20000
	395	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
8415bb68	396	#endif
c8a7d9da WH	397
	398	#define CONFIG_OF_LIBFDT
	399	#define CONFIG_OF_BOARD_SETUP
	400	#define CONFIG_CMD_BOOTZ
	401
4ba4a095 RG	402	#define CONFIG_MISC_INIT_R
	403
	404	/* Hash command with SHA acceleration supported in hardware */
	405	#define CONFIG_CMD_HASH
	406	#define CONFIG_SHA_HW_ACCEL
	407
ba474020 RG	408	#ifdef CONFIG_SECURE_BOOT
	409	#define CONFIG_CMD_BLOB
	410	#endif
	411
c8a7d9da	412	#endif