[J-u-boot.git] / include / configs / SXNI855T.h

/*
 * U-Boot configuration for SIXNET SXNI855T CPU board.
 * This board is based (loosely) on the Motorola FADS board, so this
 * file is based (loosely) on config_FADS860T.h, see it for additional
 * credits.
 *
 * Copyright (c) 2000-2002 Dave Ellis, SIXNET, [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

/*
 * Memory map:
 *
 *   ff100000 -> ff13ffff : FPGA        CS1
 *   ff030000 -> ff03ffff : EXPANSION   CS7
 *   ff020000 -> ff02ffff : DATA FLASH  CS4
 *   ff018000 -> ff01ffff : UART B      CS6/UPMB
 *   ff010000 -> ff017fff : UART A      CS5/UPMB
 *   ff000000 -> ff00ffff : IMAP                   internal to the MPC855T
 *   f8000000 -> fbffffff : FLASH       CS0        up to 64MB
 *   f4000000 -> f7ffffff : NVSRAM      CS2        up to 64MB
 *   00000000 -> 0fffffff : SDRAM       CS3/UPMA   up to 256MB
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#include <mpc8xx_irq.h>

#define CONFIG_SXNI855T		1	/* SIXNET IPm 855T CPU module */

/* The 855T is just a stripped 860T and needs code for 860, so for now
 * at least define 860, 860T and 855T
 */
#define CONFIG_MPC860		1
#define CONFIG_MPC860T		1
#define CONFIG_MPC855T		1

#define	CONFIG_SYS_TEXT_BASE	0xF8000000

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_SCC1
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		9600
#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/

#define MPC8XX_FACT		10	/* 50 MHz is 5 MHz in times 10	*/

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_HAS_ETH1

/*-----------------------------------------------------------------------
 * Definitions for status LED
 */
#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/

# define STATUS_LED_PAR		im_ioport.iop_papar
# define STATUS_LED_DIR		im_ioport.iop_padir
# define STATUS_LED_ODR		im_ioport.iop_paodr
# define STATUS_LED_DAT		im_ioport.iop_padat

# define STATUS_LED_BIT		0x8000		/* LED 0 is on PA.0 */
# define STATUS_LED_PERIOD	((CONFIG_SYS_HZ / 2) / 5)	/* blink at 5 Hz */
# define STATUS_LED_STATE	STATUS_LED_BLINKING

# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/

# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */

#ifdef DEV	/* development (debug) settings */
#define CONFIG_BOOT_LED_STATE	STATUS_LED_OFF
#else		/* production settings */
#define CONFIG_BOOT_LED_STATE	STATUS_LED_ON
#endif

#define CONFIG_SHOW_BOOT_PROGRESS 1

#define CONFIG_BOOTCOMMAND	"bootm f8040000 f8100000" /* autoboot command */
#define CONFIG_BOOTARGS		"root=/dev/ram ip=off"

#define CONFIG_MISC_INIT_R		/* have misc_init_r() function */
#define CONFIG_BOARD_POSTCLK_INIT	/* have board_postclk_init() function */

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_RTC_DS1306		/* Dallas 1306 real time clock	*/

#define	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

# define CONFIG_SYS_I2C_SPEED		50000
# define CONFIG_SYS_I2C_SLAVE		0xFE
# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Atmel 24C64			*/
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* two byte address		*/

#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
#define	CONFIG_MII		1

#define CONFIG_SYS_DISCOVER_PHY


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_DATE

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save a little memory */
#define	CONFIG_SYS_PROMPT		"=>"	/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFF000000
#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define	CONFIG_SYS_SRAM_BASE		0xF4000000
#define	CONFIG_SYS_SRAM_SIZE		0x04000000	/* autosize up to 64Mbyte */

#define CONFIG_SYS_FLASH_BASE		0xF8000000
#define CONFIG_SYS_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */

#define CONFIG_SYS_DFLASH_BASE		0xff020000 /* DiskOnChip or NAND FLASH */
#define CONFIG_SYS_DFLASH_SIZE		0x00010000

#define CONFIG_SYS_FPGA_BASE		0xFF100000	/* Xilinx FPGA */
#define CONFIG_SYS_FPGA_PROG		0xFF130000	/* Programming address */
#define CONFIG_SYS_FPGA_SIZE		0x00040000	/* 256KiB usable */

#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
 * AMD 29LV641 has 128 64K sectors in 8MB
 */
#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control					11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration					11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control					11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
 *-----------------------------------------------------------------------
 * set the PLL, the low-power modes and the reset control (15-29)
 */
#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)

 /*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER		0

/* Because of the way the 860 starts up and assigns CS0 the
 * entire address space, we have to set the memory controller
 * differently.  Normally, you write the option register
 * first, and then enable the chip select by writing the
 * base register.  For CS0, you must write the base register
 * first, followed by the option register.
 */

/*
 * Init Memory Controller:
 *
 **********************************************************
 * BR0 and OR0 (FLASH)
 */

#define CONFIG_SYS_PRELIM_OR0_AM	0xFC000000	/* OR addr mask */

/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)

#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR0_AM | CONFIG_SYS_OR_TIMING_FLASH)

#define CONFIG_FLASH_16BIT
#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
#define CONFIG_SYS_FLASH_PROTECTION	/* need to lock/unlock sectors in hardware */

/**********************************************************
 * BR1 and OR1 (FPGA)
 * These preliminary values are also the final values.
 */
#define CONFIG_SYS_OR_TIMING_FPGA \
	(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX)
#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
#define CONFIG_SYS_OR1_PRELIM	(((-CONFIG_SYS_FPGA_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_FPGA)

/**********************************************************
 * BR4 and OR4 (data flash)
 * These preliminary values are also the final values.
 */
#define CONFIG_SYS_OR_TIMING_DFLASH \
	(OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX)
#define CONFIG_SYS_BR4_PRELIM	((CONFIG_SYS_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
#define CONFIG_SYS_OR4_PRELIM	(((-CONFIG_SYS_DFLASH_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_DFLASH)

/**********************************************************
 * BR5/6 and OR5/6 (Dual UART)
 */
#define CONFIG_SYS_DUART_SIZE	0x8000	/* 32K window, only uses 8 bytes */
#define CONFIG_SYS_DUARTA_BASE	0xff010000
#define CONFIG_SYS_DUARTB_BASE	0xff018000

#define DUART_MBMR	0
#define DUART_OR_VALUE (ORMASK(CONFIG_SYS_DUART_SIZE) | OR_G5LS| OR_BI)
#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
#define DUART_BR5_VALUE ((CONFIG_SYS_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
#define DUART_BR6_VALUE ((CONFIG_SYS_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)

#define CONFIG_RESET_ON_PANIC		/* reset if system panic() */

#define CONFIG_ENV_IS_IN_FLASH
#ifdef CONFIG_ENV_IS_IN_FLASH
  /* environment is in FLASH */
  #define CONFIG_ENV_ADDR		0xF8040000	/* AM29LV641 or AM29LV800BT */
  #define CONFIG_ENV_ADDR_REDUND	0xF8050000	/* AM29LV641 or AM29LV800BT */
  #define CONFIG_ENV_SECT_SIZE	0x00010000
  #define CONFIG_ENV_SIZE		0x00002000
#else
  /* environment is in EEPROM */
  #define CONFIG_ENV_IS_IN_EEPROM		1
  #define CONFIG_ENV_OFFSET		0	/* at beginning of EEPROM */
  #define CONFIG_ENV_SIZE		     1024	/* Use only a part of it*/
#endif

#if 1
#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR	"delayabit"
#define CONFIG_AUTOBOOT_STOP_STR	" " /* easy to stop for now */
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
cc1c8a13 WD	1	/*
	2	* U-Boot configuration for SIXNET SXNI855T CPU board.
	3	* This board is based (loosely) on the Motorola FADS board, so this
	4	* file is based (loosely) on config_FADS860T.h, see it for additional
	5	* credits.
	6	*
	7	* Copyright (c) 2000-2002 Dave Ellis, SIXNET, [email protected]
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*
	27	*/
	28
	29	/*
	30	* Memory map:
	31	*
	32	* ff100000 -> ff13ffff : FPGA CS1
	33	* ff030000 -> ff03ffff : EXPANSION CS7
	34	* ff020000 -> ff02ffff : DATA FLASH CS4
	35	* ff018000 -> ff01ffff : UART B CS6/UPMB
	36	* ff010000 -> ff017fff : UART A CS5/UPMB
	37	* ff000000 -> ff00ffff : IMAP internal to the MPC855T
	38	* f8000000 -> fbffffff : FLASH CS0 up to 64MB
	39	* f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB
	40	* 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB
	41	*/
	42
	43	/* ------------------------------------------------------------------------- */
	44
	45	/*
	46	* board/config.h - configuration options, board specific
	47	*/
	48
	49	#ifndef __CONFIG_H
	50	#define __CONFIG_H
	51
	52	/*
	53	* High Level Configuration Options
	54	* (easy to change)
	55	*/
	56	#include <mpc8xx_irq.h>
	57
	58	#define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */
	59
	60	/* The 855T is just a stripped 860T and needs code for 860, so for now
	61	* at least define 860, 860T and 855T
	62	*/
	63	#define CONFIG_MPC860 1
	64	#define CONFIG_MPC860T 1
65	#define CONFIG_MPC855T 1
66
2ae18241 WD	67	#define CONFIG_SYS_TEXT_BASE 0xF8000000
2ae18241 WD	68
cc1c8a13 WD	69	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	70	#undef CONFIG_8xx_CONS_SMC2
	71	#undef CONFIG_8xx_CONS_SCC1
	72	#undef CONFIG_8xx_CONS_NONE
	73	#define CONFIG_BAUDRATE 9600
	74	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	75
	76	#define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */
	77
	78	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	79
	80	#if 0
	81	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	82	#else
	83	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	84	#endif
	85
e2ffd59b WD	86	#define CONFIG_HAS_ETH1
e2ffd59b WD	87
506f0441 WD	88	/*-----------------------------------------------------------------------
	89	* Definitions for status LED
	90	*/
	91	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	92
	93	# define STATUS_LED_PAR im_ioport.iop_papar
	94	# define STATUS_LED_DIR im_ioport.iop_padir
	95	# define STATUS_LED_ODR im_ioport.iop_paodr
	96	# define STATUS_LED_DAT im_ioport.iop_padat
	97
	98	# define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */
6d0f6bcf	99	# define STATUS_LED_PERIOD ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
506f0441 WD	100	# define STATUS_LED_STATE STATUS_LED_BLINKING
	101
	102	# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
	103
	104	# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
	105
	106	#ifdef DEV /* development (debug) settings */
	107	#define CONFIG_BOOT_LED_STATE STATUS_LED_OFF
	108	#else /* production settings */
	109	#define CONFIG_BOOT_LED_STATE STATUS_LED_ON
	110	#endif
	111
	112	#define CONFIG_SHOW_BOOT_PROGRESS 1
	113
cc1c8a13 WD	114	#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */
	115	#define CONFIG_BOOTARGS "root=/dev/ram ip=off"
	116
	117	#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
	118	#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
	119
	120	#undef CONFIG_WATCHDOG /* watchdog disabled */
	121
	122	#define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */
	123
	124	#define CONFIG_SOFT_I2C /* I2C bit-banged */
	125	/*
	126	* Software (bit-bang) I2C driver configuration
	127	*/
	128	#define PB_SCL 0x00000020 /* PB 26 */
	129	#define PB_SDA 0x00000010 /* PB 27 */
	130
	131	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	132	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	133	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	134	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	135	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	136	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	137	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	138	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	139	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	140
6d0f6bcf JCPV	141	# define CONFIG_SYS_I2C_SPEED 50000
	142	# define CONFIG_SYS_I2C_SLAVE 0xFE
	143	# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */
	144	# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
cc1c8a13 WD	145
cc1c8a13 WD	146	#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
63ff004c	147	#define CONFIG_MII 1
cc1c8a13	148
6d0f6bcf	149	#define CONFIG_SYS_DISCOVER_PHY
cc1c8a13	150
cc1c8a13	151
a1aa0bb5 JL	152	/*
	153	* BOOTP options
	154	*/
	155	#define CONFIG_BOOTP_BOOTFILESIZE
	156	#define CONFIG_BOOTP_BOOTPATH
	157	#define CONFIG_BOOTP_GATEWAY
	158	#define CONFIG_BOOTP_HOSTNAME
	159
	160
fe7f782d JL	161	/*
	162	* Command line configuration.
	163	*/
	164	#include <config_cmd_default.h>
	165
	166	#define CONFIG_CMD_EEPROM
	167	#define CONFIG_CMD_JFFS2
fe7f782d JL	168	#define CONFIG_CMD_DATE
fe7f782d JL	169
cc1c8a13 WD	170	/*
	171	* Miscellaneous configurable options
	172	*/
6d0f6bcf JCPV	173	#define CONFIG_SYS_LONGHELP /* undef to save a little memory */
6d0f6bcf JCPV	174	#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
fe7f782d	175	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	176	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
cc1c8a13	177	#else
6d0f6bcf	178	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
cc1c8a13	179	#endif
6d0f6bcf JCPV	180	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	181	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	182	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
cc1c8a13	183
6d0f6bcf JCPV	184	#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
6d0f6bcf JCPV	185	#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
cc1c8a13	186
6d0f6bcf	187	#define CONFIG_SYS_LOAD_ADDR 0x00100000
cc1c8a13	188
6d0f6bcf	189	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
cc1c8a13	190
cc1c8a13 WD	191	/*
	192	* Low Level Configuration Settings
	193	* (address mappings, register initial values, etc.)
	194	* You should know what you are doing if you make changes here.
	195	*/
	196	/*-----------------------------------------------------------------------
	197	* Internal Memory Mapped Register
	198	*/
6d0f6bcf JCPV	199	#define CONFIG_SYS_IMMR 0xFF000000
6d0f6bcf JCPV	200	#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
cc1c8a13 WD	201
	202	/*-----------------------------------------------------------------------
	203	* Definitions for initial stack pointer and data area (in DPRAM)
	204	*/
6d0f6bcf	205	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	206	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	207	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	208	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
cc1c8a13 WD	209
	210	/*-----------------------------------------------------------------------
	211	* Start addresses for the final memory configuration
	212	* (Set up by the startup code)
6d0f6bcf	213	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
cc1c8a13	214	*/
6d0f6bcf JCPV	215	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	216	#define CONFIG_SYS_SRAM_BASE 0xF4000000
	217	#define CONFIG_SYS_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */
cc1c8a13	218
6d0f6bcf JCPV	219	#define CONFIG_SYS_FLASH_BASE 0xF8000000
6d0f6bcf JCPV	220	#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
cc1c8a13	221
6d0f6bcf JCPV	222	#define CONFIG_SYS_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */
6d0f6bcf JCPV	223	#define CONFIG_SYS_DFLASH_SIZE 0x00010000
cc1c8a13	224
6d0f6bcf JCPV	225	#define CONFIG_SYS_FPGA_BASE 0xFF100000 /* Xilinx FPGA */
	226	#define CONFIG_SYS_FPGA_PROG 0xFF130000 /* Programming address */
	227	#define CONFIG_SYS_FPGA_SIZE 0x00040000 /* 256KiB usable */
cc1c8a13	228
6d0f6bcf JCPV	229	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	230	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	231	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
cc1c8a13 WD	232
	233	/*
	234	* For booting Linux, the board info and command line data
	235	* have to be in the first 8 MB of memory, since this is
	236	* the maximum mapped by the Linux kernel during initialization.
	237	*/
6d0f6bcf	238	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
cc1c8a13 WD	239	/*-----------------------------------------------------------------------
	240	* FLASH organization
	241	*/
6d0f6bcf	242	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
cc1c8a13 WD	243	/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
	244	* AMD 29LV641 has 128 64K sectors in 8MB
	245	*/
6d0f6bcf	246	#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
cc1c8a13	247
6d0f6bcf JCPV	248	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	249	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
cc1c8a13 WD	250
	251	/*-----------------------------------------------------------------------
	252	* Cache Configuration
	253	*/
6d0f6bcf	254	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
fe7f782d	255	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	256	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
cc1c8a13 WD	257	#endif
	258
	259	/*-----------------------------------------------------------------------
	260	* SYPCR - System Protection Control 11-9
	261	* SYPCR can only be written once after reset!
	262	*-----------------------------------------------------------------------
	263	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	264	*/
	265	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	266	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
cc1c8a13 WD	267	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
cc1c8a13 WD	268	#else
6d0f6bcf	269	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
cc1c8a13 WD	270	#endif
	271
	272	/*-----------------------------------------------------------------------
	273	* SIUMCR - SIU Module Configuration 11-6
	274	*-----------------------------------------------------------------------
	275	* PCMCIA config., multi-function pin tri-state
	276	*/
6d0f6bcf	277	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
cc1c8a13 WD	278
	279	/*-----------------------------------------------------------------------
	280	* TBSCR - Time Base Status and Control 11-26
	281	*-----------------------------------------------------------------------
	282	* Clear Reference Interrupt Status, Timebase freezing enabled
	283	*/
6d0f6bcf	284	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
cc1c8a13 WD	285
	286	/*-----------------------------------------------------------------------
	287	* PISCR - Periodic Interrupt Status and Control 11-31
	288	*-----------------------------------------------------------------------
	289	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	290	*/
6d0f6bcf	291	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
cc1c8a13 WD	292
	293	/*-----------------------------------------------------------------------
	294	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	295	*-----------------------------------------------------------------------
	296	* set the PLL, the low-power modes and the reset control (15-29)
	297	*/
6d0f6bcf	298	#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) \| \
cc1c8a13 WD	299	PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
	300
	301	/*-----------------------------------------------------------------------
	302	* SCCR - System Clock and reset Control Register 15-27
	303	*-----------------------------------------------------------------------
	304	* Set clock output, timebase and RTC source and divider,
	305	* power management and some other internal clocks
	306	*/
	307	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	308	#define CONFIG_SYS_SCCR (SCCR_TBS\|SCCR_COM00\|SCCR_DFSYNC00\|SCCR_DFBRG00\|SCCR_DFNL000\|SCCR_DFNH000\|SCCR_DFLCD000\|SCCR_DFALCD00)
cc1c8a13 WD	309
	310	/*-----------------------------------------------------------------------
	311	*
	312	*-----------------------------------------------------------------------
	313	*
	314	*/
6d0f6bcf	315	#define CONFIG_SYS_DER 0
cc1c8a13 WD	316
	317	/* Because of the way the 860 starts up and assigns CS0 the
	318	* entire address space, we have to set the memory controller
	319	* differently. Normally, you write the option register
	320	* first, and then enable the chip select by writing the
	321	* base register. For CS0, you must write the base register
	322	* first, followed by the option register.
	323	*/
	324
	325	/*
	326	* Init Memory Controller:
	327	*
	328	**********************************************************
	329	* BR0 and OR0 (FLASH)
	330	*/
	331
6d0f6bcf	332	#define CONFIG_SYS_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */
cc1c8a13 WD	333
cc1c8a13 WD	334	/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
6d0f6bcf	335	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV4 \| OR_BI \| OR_SCY_3_CLK \| OR_TRLX)
cc1c8a13	336
6d0f6bcf	337	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR0_AM \| CONFIG_SYS_OR_TIMING_FLASH)
cc1c8a13 WD	338
cc1c8a13 WD	339	#define CONFIG_FLASH_16BIT
6d0f6bcf JCPV	340	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) \| BR_PS_16 \| BR_V )
6d0f6bcf JCPV	341	#define CONFIG_SYS_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */
cc1c8a13 WD	342
	343	/**********************************************************
	344	* BR1 and OR1 (FPGA)
	345	* These preliminary values are also the final values.
	346	*/
6d0f6bcf	347	#define CONFIG_SYS_OR_TIMING_FPGA \
7a8e9bed	348	(OR_CSNT_SAM \| OR_ACS_DIV2 \| OR_BI \| OR_SCY_4_CLK \| OR_EHTR \| OR_TRLX)
6d0f6bcf JCPV	349	#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FPGA_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V )
6d0f6bcf JCPV	350	#define CONFIG_SYS_OR1_PRELIM (((-CONFIG_SYS_FPGA_SIZE) & OR_AM_MSK) \| CONFIG_SYS_OR_TIMING_FPGA)
cc1c8a13 WD	351
	352	/**********************************************************
	353	* BR4 and OR4 (data flash)
	354	* These preliminary values are also the final values.
	355	*/
6d0f6bcf	356	#define CONFIG_SYS_OR_TIMING_DFLASH \
7a8e9bed	357	(OR_CSNT_SAM \| OR_ACS_DIV4 \| OR_BI \| OR_SCY_2_CLK \| OR_EHTR \| OR_TRLX)
6d0f6bcf JCPV	358	#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DFLASH_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V )
6d0f6bcf JCPV	359	#define CONFIG_SYS_OR4_PRELIM (((-CONFIG_SYS_DFLASH_SIZE) & OR_AM_MSK) \| CONFIG_SYS_OR_TIMING_DFLASH)
cc1c8a13 WD	360
	361	/**********************************************************
	362	* BR5/6 and OR5/6 (Dual UART)
	363	*/
6d0f6bcf JCPV	364	#define CONFIG_SYS_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */
	365	#define CONFIG_SYS_DUARTA_BASE 0xff010000
	366	#define CONFIG_SYS_DUARTB_BASE 0xff018000
cc1c8a13 WD	367
cc1c8a13 WD	368	#define DUART_MBMR 0
6d0f6bcf	369	#define DUART_OR_VALUE (ORMASK(CONFIG_SYS_DUART_SIZE) \| OR_G5LS\| OR_BI)
cc1c8a13	370	#define DUART_BR_VALUE (BR_MS_UPMB \| BR_PS_8 \| BR_V)
6d0f6bcf JCPV	371	#define DUART_BR5_VALUE ((CONFIG_SYS_DUARTA_BASE & BR_BA_MSK ) \| DUART_BR_VALUE)
6d0f6bcf JCPV	372	#define DUART_BR6_VALUE ((CONFIG_SYS_DUARTB_BASE & BR_BA_MSK ) \| DUART_BR_VALUE)
cc1c8a13	373
cc1c8a13 WD	374	#define CONFIG_RESET_ON_PANIC /* reset if system panic() */
cc1c8a13 WD	375
5a1aceb0 JCPV	376	#define CONFIG_ENV_IS_IN_FLASH
5a1aceb0 JCPV	377	#ifdef CONFIG_ENV_IS_IN_FLASH
7205e407	378	/* environment is in FLASH */
0e8d1586 JCPV	379	#define CONFIG_ENV_ADDR 0xF8040000 /* AM29LV641 or AM29LV800BT */
	380	#define CONFIG_ENV_ADDR_REDUND 0xF8050000 /* AM29LV641 or AM29LV800BT */
	381	#define CONFIG_ENV_SECT_SIZE 0x00010000
	382	#define CONFIG_ENV_SIZE 0x00002000
7205e407 WD	383	#else
7205e407 WD	384	/* environment is in EEPROM */
bb1f8b4f	385	#define CONFIG_ENV_IS_IN_EEPROM 1
0e8d1586 JCPV	386	#define CONFIG_ENV_OFFSET 0 /* at beginning of EEPROM */
0e8d1586 JCPV	387	#define CONFIG_ENV_SIZE 1024 /* Use only a part of it*/
cc1c8a13 WD	388	#endif
	389
	390	#if 1
	391	#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
c37207d7	392	#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
cc1c8a13 WD	393	#define CONFIG_AUTOBOOT_DELAY_STR "delayabit"
	394	#define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */
	395	#endif
	396
	397	#endif /* __CONFIG_H */