[J-u-boot.git] / include / configs / SXNI855T.h

/*
 * U-Boot configuration for SIXNET SXNI855T CPU board.
 * This board is based (loosely) on the Motorola FADS board, so this
 * file is based (loosely) on config_FADS860T.h, see it for additional
 * credits.
 *
 * Copyright (c) 2000-2002 Dave Ellis, SIXNET, [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

/*
 * Memory map:
 *
 *   ff100000 -> ff13ffff : FPGA        CS1
 *   ff030000 -> ff03ffff : EXPANSION   CS7
 *   ff020000 -> ff02ffff : DATA FLASH  CS4
 *   ff018000 -> ff01ffff : UART B      CS6/UPMB
 *   ff010000 -> ff017fff : UART A      CS5/UPMB
 *   ff000000 -> ff00ffff : IMAP                   internal to the MPC855T
 *   f8000000 -> fbffffff : FLASH       CS0        up to 64MB
 *   f4000000 -> f7ffffff : NVSRAM      CS2        up to 64MB
 *   00000000 -> 0fffffff : SDRAM       CS3/UPMA   up to 256MB
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#include <mpc8xx_irq.h>

#define CONFIG_SXNI855T		1	/* SIXNET IPm 855T CPU module */

/* The 855T is just a stripped 860T and needs code for 860, so for now
 * at least define 860, 860T and 855T
 */
#define CONFIG_MPC860		1
#define CONFIG_MPC860T		1
#define CONFIG_MPC855T		1

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_SCC1
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		9600
#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/

#define MPC8XX_FACT		10	/* 50 MHz is 5 MHz in times 10	*/

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

/*-----------------------------------------------------------------------
 * Definitions for status LED
 */
#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/

# define STATUS_LED_PAR		im_ioport.iop_papar
# define STATUS_LED_DIR		im_ioport.iop_padir
# define STATUS_LED_ODR		im_ioport.iop_paodr
# define STATUS_LED_DAT		im_ioport.iop_padat

# define STATUS_LED_BIT		0x8000		/* LED 0 is on PA.0 */
# define STATUS_LED_PERIOD	((CFG_HZ / 2) / 5)	/* blink at 5 Hz */
# define STATUS_LED_STATE	STATUS_LED_BLINKING

# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/

# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */

#ifdef DEV	/* development (debug) settings */
#define CONFIG_BOOT_LED_STATE	STATUS_LED_OFF
#else		/* production settings */
#define CONFIG_BOOT_LED_STATE	STATUS_LED_ON
#endif

#define CONFIG_SHOW_BOOT_PROGRESS 1

#define CONFIG_BOOTCOMMAND	"bootm f8040000 f8100000" /* autoboot command */
#define CONFIG_BOOTARGS		"root=/dev/ram ip=off"

#define CONFIG_MISC_INIT_R		/* have misc_init_r() function */
#define CONFIG_BOARD_POSTCLK_INIT	/* have board_postclk_init() function */

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_RTC_DS1306		/* Dallas 1306 real time clock	*/

#define	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

# define CFG_I2C_SPEED		50000
# define CFG_I2C_SLAVE		0xFE
# define CFG_I2C_EEPROM_ADDR	0x50	/* Atmel 24C64			*/
# define CFG_I2C_EEPROM_ADDR_LEN 2	/* two byte address		*/

#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */

#define CFG_DISCOVER_PHY

#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		| \
				 CFG_CMD_EEPROM		| \
				 CFG_CMD_NAND		| \
				 CFG_CMD_DATE)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/* NAND flash support */
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices	*/
#define SECTORSIZE 512

#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3

#define NAND_ChipID_UNKNOWN 	0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1

/* DFBUSY is available on Port C, bit 12; 0 if busy */
#define NAND_WAIT_READY(nand)	\
	while (!(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x0008));
#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr))
#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr))
#define WRITE_NAND(d, adr)	\
	 do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0)
#define READ_NAND(adr) (*(volatile uint8_t *)(adr))
#define	CLE_LO	0x01	/* 0 selects CLE mode (CLE high) */
#define	ALE_LO	0x02	/* 0 selects ALE mode (ALE high) */
#define	CE_LO	0x04	/* 1 selects chip (CE low) */
#define	nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0)
#define NAND_DISABLE_CE(nand) \
	nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO)
#define NAND_ENABLE_CE(nand) \
	nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO)
#define NAND_CTL_CLRALE(nandptr) \
	nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
#define NAND_CTL_SETALE(nandptr) \
	nand_setcr((nandptr) + 1, CE_LO | CLE_LO)
#define NAND_CTL_CLRCLE(nandptr) \
	nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
#define NAND_CTL_SETCLE(nandptr) \
	nand_setcr((nandptr) + 1, CE_LO | ALE_LO)

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save a little memory */
#define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/

#define CFG_LOAD_ADDR	 	0x00100000

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFF000000
#define CFG_IMMR_SIZE		((uint)(64 * 1024))

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#define	CFG_SRAM_BASE		0xF4000000
#define	CFG_SRAM_SIZE		0x04000000	/* autosize up to 64Mbyte */

#define CFG_FLASH_BASE		0xF8000000
#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */

#define CFG_DFLASH_BASE		0xff020000 /* DiskOnChip or NAND FLASH */
#define CFG_DFLASH_SIZE		0x00010000

#define CFG_FPGA_BASE		0xFF100000	/* Xilinx FPGA */
#define CFG_FPGA_PROG		0xFF130000	/* Programming address */
#define CFG_FPGA_SIZE		0x00040000	/* 256KiB usable */

#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
 * AMD 29LV641 has 128 64K sectors in 8MB
 */
#define CFG_MAX_FLASH_SECT	135	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control					11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration					11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control					11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
 *-----------------------------------------------------------------------
 * set the PLL, the low-power modes and the reset control (15-29)
 */
#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)

 /*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER		0

/* Because of the way the 860 starts up and assigns CS0 the
 * entire address space, we have to set the memory controller
 * differently.  Normally, you write the option register
 * first, and then enable the chip select by writing the
 * base register.  For CS0, you must write the base register
 * first, followed by the option register.
 */

/*
 * Init Memory Controller:
 *
 **********************************************************
 * BR0 and OR0 (FLASH)
 */

#define CFG_PRELIM_OR0_AM	0xFC000000	/* OR addr mask */

/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)

#define CFG_OR0_PRELIM	(CFG_PRELIM_OR0_AM | CFG_OR_TIMING_FLASH)

#define CONFIG_FLASH_16BIT
#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
#define CFG_FLASH_PROTECTION	/* need to lock/unlock sectors in hardware */

/**********************************************************
 * BR1 and OR1 (FPGA)
 * These preliminary values are also the final values.
 */
#define CFG_OR_TIMING_FPGA \
	(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX)
#define CFG_BR1_PRELIM	((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
#define CFG_OR1_PRELIM	(((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA)

/**********************************************************
 * BR4 and OR4 (data flash)
 * These preliminary values are also the final values.
 */
#define CFG_OR_TIMING_DFLASH \
	(OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX)
#define CFG_BR4_PRELIM	((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
#define CFG_OR4_PRELIM	(((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH)

/**********************************************************
 * BR5/6 and OR5/6 (Dual UART)
 */
#define CFG_DUART_SIZE	0x8000	/* 32K window, only uses 8 bytes */
#define CFG_DUARTA_BASE	0xff010000
#define CFG_DUARTB_BASE	0xff018000

#define DUART_MBMR	0
#define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) | OR_G5LS| OR_BI)
#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
#define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
#define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)

/**********************************************************
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#define CONFIG_RESET_ON_PANIC		/* reset if system panic() */

/* to put environment in EEROM */
#define	CFG_ENV_IS_IN_EEPROM	1
#define CFG_ENV_OFFSET		0	/* Start right at beginning of NVRAM */
#define CFG_ENV_SIZE		1024	/* Use only a part of it*/

#if 1
#define CONFIG_BOOT_RETRY_TIME	60	/* boot if no command in 60 seconds */
#endif

#if 1
#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n"
#define CONFIG_AUTOBOOT_DELAY_STR	"delayabit"
#define CONFIG_AUTOBOOT_STOP_STR	" " /* easy to stop for now */
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
cc1c8a13 WD	1	/*
	2	* U-Boot configuration for SIXNET SXNI855T CPU board.
	3	* This board is based (loosely) on the Motorola FADS board, so this
	4	* file is based (loosely) on config_FADS860T.h, see it for additional
	5	* credits.
	6	*
	7	* Copyright (c) 2000-2002 Dave Ellis, SIXNET, [email protected]
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*
	27	*/
	28
	29	/*
	30	* Memory map:
	31	*
	32	* ff100000 -> ff13ffff : FPGA CS1
	33	* ff030000 -> ff03ffff : EXPANSION CS7
	34	* ff020000 -> ff02ffff : DATA FLASH CS4
	35	* ff018000 -> ff01ffff : UART B CS6/UPMB
	36	* ff010000 -> ff017fff : UART A CS5/UPMB
	37	* ff000000 -> ff00ffff : IMAP internal to the MPC855T
	38	* f8000000 -> fbffffff : FLASH CS0 up to 64MB
	39	* f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB
	40	* 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB
	41	*/
	42
	43	/* ------------------------------------------------------------------------- */
	44
	45	/*
	46	* board/config.h - configuration options, board specific
	47	*/
	48
	49	#ifndef __CONFIG_H
	50	#define __CONFIG_H
	51
	52	/*
	53	* High Level Configuration Options
	54	* (easy to change)
	55	*/
	56	#include <mpc8xx_irq.h>
	57
	58	#define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */
	59
	60	/* The 855T is just a stripped 860T and needs code for 860, so for now
	61	* at least define 860, 860T and 855T
	62	*/
	63	#define CONFIG_MPC860 1
	64	#define CONFIG_MPC860T 1
65	#define CONFIG_MPC855T 1
66
67	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
68	#undef CONFIG_8xx_CONS_SMC2
69	#undef CONFIG_8xx_CONS_SCC1
70	#undef CONFIG_8xx_CONS_NONE
71	#define CONFIG_BAUDRATE 9600
72	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
73
74	#define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */
75
76	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
77
78	#if 0
79	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
80	#else
81	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
82	#endif
83
506f0441 WD	84	/*-----------------------------------------------------------------------
	85	* Definitions for status LED
	86	*/
	87	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	88
	89	# define STATUS_LED_PAR im_ioport.iop_papar
	90	# define STATUS_LED_DIR im_ioport.iop_padir
	91	# define STATUS_LED_ODR im_ioport.iop_paodr
	92	# define STATUS_LED_DAT im_ioport.iop_padat
	93
	94	# define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */
	95	# define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
	96	# define STATUS_LED_STATE STATUS_LED_BLINKING
	97
	98	# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
	99
	100	# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
	101
	102	#ifdef DEV /* development (debug) settings */
	103	#define CONFIG_BOOT_LED_STATE STATUS_LED_OFF
	104	#else /* production settings */
	105	#define CONFIG_BOOT_LED_STATE STATUS_LED_ON
	106	#endif
	107
	108	#define CONFIG_SHOW_BOOT_PROGRESS 1
	109
cc1c8a13 WD	110	#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */
	111	#define CONFIG_BOOTARGS "root=/dev/ram ip=off"
	112
	113	#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
	114	#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
	115
	116	#undef CONFIG_WATCHDOG /* watchdog disabled */
	117
	118	#define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */
	119
	120	#define CONFIG_SOFT_I2C /* I2C bit-banged */
	121	/*
	122	* Software (bit-bang) I2C driver configuration
	123	*/
	124	#define PB_SCL 0x00000020 /* PB 26 */
	125	#define PB_SDA 0x00000010 /* PB 27 */
	126
	127	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	128	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	129	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	130	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	131	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	132	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	133	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	134	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	135	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	136
	137	# define CFG_I2C_SPEED 50000
	138	# define CFG_I2C_SLAVE 0xFE
	139	# define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */
	140	# define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
	141
	142	#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
	143
	144	#define CFG_DISCOVER_PHY
	145
7a8e9bed WD	146	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	147	CFG_CMD_EEPROM \| \
	148	CFG_CMD_NAND \| \
	149	CFG_CMD_DATE)
cc1c8a13 WD	150
	151	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	152	#include <cmd_confdefs.h>
	153
7a8e9bed WD	154	/* NAND flash support */
	155	#define CONFIG_MTD_NAND_ECC_JFFS2
	156	#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
	157	#define SECTORSIZE 512
	158
	159	#define ADDR_COLUMN 1
	160	#define ADDR_PAGE 2
	161	#define ADDR_COLUMN_PAGE 3
	162
	163	#define NAND_ChipID_UNKNOWN 0x00
	164	#define NAND_MAX_FLOORS 1
	165	#define NAND_MAX_CHIPS 1
	166
	167	/* DFBUSY is available on Port C, bit 12; 0 if busy */
	168	#define NAND_WAIT_READY(nand) \
	169	while (!(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x0008));
	170	#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr))
	171	#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr))
	172	#define WRITE_NAND(d, adr) \
	173	do { ((volatile uint8_t )(adr) = (uint8_t)(d)); } while (0)
	174	#define READ_NAND(adr) ((volatile uint8_t )(adr))
	175	#define CLE_LO 0x01 /* 0 selects CLE mode (CLE high) */
	176	#define ALE_LO 0x02 /* 0 selects ALE mode (ALE high) */
	177	#define CE_LO 0x04 /* 1 selects chip (CE low) */
	178	#define nand_setcr(cr, val) do {(volatile uint8_t)(cr) = (val);} while (0)
	179	#define NAND_DISABLE_CE(nand) \
	180	nand_setcr((nand)->IO_ADDR + 1, ALE_LO \| CLE_LO)
	181	#define NAND_ENABLE_CE(nand) \
	182	nand_setcr((nand)->IO_ADDR + 1, CE_LO \| ALE_LO \| CLE_LO)
	183	#define NAND_CTL_CLRALE(nandptr) \
	184	nand_setcr((nandptr) + 1, CE_LO \| ALE_LO \| CLE_LO)
	185	#define NAND_CTL_SETALE(nandptr) \
	186	nand_setcr((nandptr) + 1, CE_LO \| CLE_LO)
	187	#define NAND_CTL_CLRCLE(nandptr) \
	188	nand_setcr((nandptr) + 1, CE_LO \| ALE_LO \| CLE_LO)
	189	#define NAND_CTL_SETCLE(nandptr) \
	190	nand_setcr((nandptr) + 1, CE_LO \| ALE_LO)
	191
cc1c8a13 WD	192	/*
	193	* Miscellaneous configurable options
	194	*/
	195	#define CFG_LONGHELP /* undef to save a little memory */
	196	#define CFG_PROMPT "=>" /* Monitor Command Prompt */
	197	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	198	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	199	#else
	200	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	201	#endif
	202	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	203	#define CFG_MAXARGS 16 /* max number of command args */
	204	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	205
	206	#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
	207	#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
	208
	209	#define CFG_LOAD_ADDR 0x00100000
	210
	211	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	212
	213	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	214
	215	/*
	216	* Low Level Configuration Settings
	217	* (address mappings, register initial values, etc.)
	218	* You should know what you are doing if you make changes here.
	219	*/
	220	/*-----------------------------------------------------------------------
	221	* Internal Memory Mapped Register
	222	*/
	223	#define CFG_IMMR 0xFF000000
	224	#define CFG_IMMR_SIZE ((uint)(64 * 1024))
	225
	226	/*-----------------------------------------------------------------------
	227	* Definitions for initial stack pointer and data area (in DPRAM)
	228	*/
	229	#define CFG_INIT_RAM_ADDR CFG_IMMR
	230	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	231	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	232	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	233	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	234
	235	/*-----------------------------------------------------------------------
	236	* Start addresses for the final memory configuration
	237	* (Set up by the startup code)
	238	* Please note that CFG_SDRAM_BASE _must_ start at 0
	239	*/
	240	#define CFG_SDRAM_BASE 0x00000000
	241	#define CFG_SRAM_BASE 0xF4000000
	242	#define CFG_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */
	243
	244	#define CFG_FLASH_BASE 0xF8000000
	245	#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
	246
	247	#define CFG_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */
	248	#define CFG_DFLASH_SIZE 0x00010000
	249
	250	#define CFG_FPGA_BASE 0xFF100000 /* Xilinx FPGA */
	251	#define CFG_FPGA_PROG 0xFF130000 /* Programming address */
	252	#define CFG_FPGA_SIZE 0x00040000 /* 256KiB usable */
	253
	254	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	255	#define CFG_MONITOR_BASE CFG_FLASH_BASE
256	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
257
258	/*
259	* For booting Linux, the board info and command line data
260	* have to be in the first 8 MB of memory, since this is
261	* the maximum mapped by the Linux kernel during initialization.
262	*/
263	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
264	/*-----------------------------------------------------------------------
265	* FLASH organization
266	*/
267	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
268	/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
269	* AMD 29LV641 has 128 64K sectors in 8MB
270	*/
271	#define CFG_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
272
273	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
274	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
275
276	/*-----------------------------------------------------------------------
277	* Cache Configuration
278	*/
279	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
280	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
281	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
282	#endif
283
284	/*-----------------------------------------------------------------------
285	* SYPCR - System Protection Control 11-9
286	* SYPCR can only be written once after reset!
287	*-----------------------------------------------------------------------
288	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
289	*/
290	#if defined(CONFIG_WATCHDOG)
291	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
292	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
293	#else
294	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
295	#endif
296
297	/*-----------------------------------------------------------------------
298	* SIUMCR - SIU Module Configuration 11-6
299	*-----------------------------------------------------------------------
300	* PCMCIA config., multi-function pin tri-state
301	*/
302	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
303
304	/*-----------------------------------------------------------------------
305	* TBSCR - Time Base Status and Control 11-26
306	*-----------------------------------------------------------------------
307	* Clear Reference Interrupt Status, Timebase freezing enabled
308	*/
309	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
310
311	/*-----------------------------------------------------------------------
312	* PISCR - Periodic Interrupt Status and Control 11-31
313	*-----------------------------------------------------------------------
314	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
315	*/
316	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
317
318	/*-----------------------------------------------------------------------
319	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
320	*-----------------------------------------------------------------------
321	* set the PLL, the low-power modes and the reset control (15-29)
322	*/
323	#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) \| \
324	PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
325
326	/*-----------------------------------------------------------------------
327	* SCCR - System Clock and reset Control Register 15-27
328	*-----------------------------------------------------------------------
329	* Set clock output, timebase and RTC source and divider,
330	* power management and some other internal clocks
331	*/
332	#define SCCR_MASK SCCR_EBDF11
333	#define CFG_SCCR (SCCR_TBS\|SCCR_COM00\|SCCR_DFSYNC00\|SCCR_DFBRG00\|SCCR_DFNL000\|SCCR_DFNH000\|SCCR_DFLCD000\|SCCR_DFALCD00)
334
335	/*-----------------------------------------------------------------------
336	*
337	*-----------------------------------------------------------------------
338	*
339	*/
340	#define CFG_DER 0
341
342	/* Because of the way the 860 starts up and assigns CS0 the
343	* entire address space, we have to set the memory controller
344	* differently. Normally, you write the option register
345	* first, and then enable the chip select by writing the
346	* base register. For CS0, you must write the base register
347	* first, followed by the option register.
348	*/
349
350	/*
351	* Init Memory Controller:
352	*
353	**********************************************************
354	* BR0 and OR0 (FLASH)
355	*/
356
357	#define CFG_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */
358
359	/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
360	#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV4 \| OR_BI \| OR_SCY_3_CLK \| OR_TRLX)
361
362	#define CFG_OR0_PRELIM (CFG_PRELIM_OR0_AM \| CFG_OR_TIMING_FLASH)
363
364	#define CONFIG_FLASH_16BIT
365	#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) \| BR_PS_16 \| BR_V )
366	#define CFG_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */
367
368	/**********************************************************
369	* BR1 and OR1 (FPGA)
370	* These preliminary values are also the final values.
371	*/
372	#define CFG_OR_TIMING_FPGA \
7a8e9bed	373	(OR_CSNT_SAM \| OR_ACS_DIV2 \| OR_BI \| OR_SCY_4_CLK \| OR_EHTR \| OR_TRLX)
cc1c8a13 WD	374	#define CFG_BR1_PRELIM ((CFG_FPGA_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V )
	375	#define CFG_OR1_PRELIM (((-CFG_FPGA_SIZE) & OR_AM_MSK) \| CFG_OR_TIMING_FPGA)
	376
	377	/**********************************************************
	378	* BR4 and OR4 (data flash)
	379	* These preliminary values are also the final values.
	380	*/
	381	#define CFG_OR_TIMING_DFLASH \
7a8e9bed	382	(OR_CSNT_SAM \| OR_ACS_DIV4 \| OR_BI \| OR_SCY_2_CLK \| OR_EHTR \| OR_TRLX)
cc1c8a13 WD	383	#define CFG_BR4_PRELIM ((CFG_DFLASH_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V )
	384	#define CFG_OR4_PRELIM (((-CFG_DFLASH_SIZE) & OR_AM_MSK) \| CFG_OR_TIMING_DFLASH)
	385
	386	/**********************************************************
	387	* BR5/6 and OR5/6 (Dual UART)
	388	*/
	389	#define CFG_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */
	390	#define CFG_DUARTA_BASE 0xff010000
	391	#define CFG_DUARTB_BASE 0xff018000
	392
	393	#define DUART_MBMR 0
	394	#define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) \| OR_G5LS\| OR_BI)
	395	#define DUART_BR_VALUE (BR_MS_UPMB \| BR_PS_8 \| BR_V)
	396	#define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) \| DUART_BR_VALUE)
	397	#define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) \| DUART_BR_VALUE)
	398
	399	/**********************************************************
	400	*
	401	* Boot Flags
	402	*/
	403	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	404	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	405
	406	#define CONFIG_RESET_ON_PANIC /* reset if system panic() */
	407
	408	/* to put environment in EEROM */
	409	#define CFG_ENV_IS_IN_EEPROM 1
	410	#define CFG_ENV_OFFSET 0 /* Start right at beginning of NVRAM */
	411	#define CFG_ENV_SIZE 1024 /* Use only a part of it*/
	412
	413	#if 1
	414	#define CONFIG_BOOT_RETRY_TIME 60 /* boot if no command in 60 seconds */
	415	#endif
	416
	417	#if 1
	418	#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
	419	#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
	420	#define CONFIG_AUTOBOOT_DELAY_STR "delayabit"
	421	#define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */
	422	#endif
	423
	424	#endif /* __CONFIG_H */