[J-u-boot.git] / include / configs / IP860.h

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
#define CONFIG_IP860		1	/* ...on a IP860 board		*/

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \
"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 $(filesize)\0"

#define CONFIG_ETHADDR	00:30:bf:01:02:d2
#define CONFIG_IPADDR	10.0.0.5
#define CONFIG_SERVERIP	10.0.0.2

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "	\
	"bootm"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/


/* enable I2C and select the hardware/software driver */
#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */


# define CFG_I2C_SPEED		50000
# define CFG_I2C_SLAVE		0xFE
# define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM X24C16		*/
# define CFG_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"    */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS	4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec */

#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
				 CFG_CMD_BEDBUG	| \
				 CFG_CMD_I2C	| \
				 CFG_CMD_EEPROM)

#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT

/*----------------------------------------------------------------------*/

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*----------------------------------------------------------------------*/

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/

#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/

#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/

#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xF1000000	/* Non-standard value!!	*/

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x10000000
#ifdef	DEBUG
#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
#else
#if 0 /* need more space for I2C tests */
#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
#else
#define	CFG_MONITOR_LEN		(256 << 10)
#endif
#endif
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#undef	CFG_ENV_IS_IN_FLASH
#undef	CFG_ENV_IS_IN_NVRAM
#undef  CFG_ENV_IS_IN_NVRAM
#undef	DEBUG_I2C
#define	CFG_ENV_IS_IN_EEPROM

#ifdef	CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_ADDR		0x20000000	/* use SRAM	*/
#define CFG_ENV_SIZE		(16<<10)	/* use 16 kB	*/
#endif	/* CFG_ENV_IS_IN_NVRAM */

#ifdef	CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_OFFSET		 512	/* Leave 512 bytes free for other data	*/
#define CFG_ENV_SIZE		1536	/* Use remaining space			*/
#endif	/* CFG_ENV_IS_IN_EEPROM */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 * +0x0004
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * +0x0000 => 0x80600800
 */
#define CFG_SIUMCR	(SIUMCR_EARB   | SIUMCR_EARP0 | \
			 SIUMCR_DBGC11 | SIUMCR_MLRC10)

/*-----------------------------------------------------------------------
 * Clock Setting - the IP860 has no 32kHz clock, so automatic detection fails
 *-----------------------------------------------------------------------
 */
#define	CONFIG_8xx_GCLK_FREQ	50000000

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 * +0x0200 => 0x00C2
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 * +0x0240 => 0x0082
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit, set PLL multiplication factor !
 */
/* +0x0286 => was: 0x0000D000 */
#define CFG_PLPRCR							\
		(	PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
		)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
			 SCCR_DFNH000)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
/* +0x0220 => 0x00C3 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)


/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration Register		19-4
 *-----------------------------------------------------------------------
 */
/* +0x09C4 => TIMEP=1 */
#define CFG_RCCR 0x0100

/*-----------------------------------------------------------------------
 * RMDS - RISC Microcode Development Support Control Register
 *-----------------------------------------------------------------------
 */
#define CFG_RMDS 0

/*-----------------------------------------------------------------------
 * DER - Debug Event Register
 *-----------------------------------------------------------------------
 *
 */
/*#define	CFG_DER	0x2002000F*/
#define CFG_DER	0

/*
 * Init Memory Controller:
 */

/*
 * MAMR settings for SDRAM	- 16-14
 * => 0xC3804114
 */

/* periodic timer for refresh */
#define CFG_MAMR_PTA	0xC3

#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/*
 * BR1 and OR1 (FLASH)
 */
#define FLASH_BASE		0x10000000	/* FLASH bank #0	*/

/* used to re-map FLASH
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
/* allow for max 8 MB of Flash */
#define CFG_REMAP_OR_AM		0xFF800000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */

#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
/* 16 bit, bank valid */
#define CFG_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )

#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
#define CFG_BR1_PRELIM	CFG_BR0_PRELIM

/*
 * BR2/OR2 - SDRAM
 */
#define SDRAM_BASE		0x00000000	/* SDRAM bank */
#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */

#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */

#define CFG_OR2		(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
#define CFG_BR2		((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * BR3/OR3 - SRAM (16 bit)
 */
#define	SRAM_BASE	0x20000000
#define CFG_OR3		0xFFF00130		/* BI/SCY = 5/TRLX (internal) */
#define CFG_BR3		((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
#define SRAM_SIZE	(1 + (~(CFG_OR3 & BR_BA_MSK)))
#define CFG_OR3_PRELIM	CFG_OR3			/* Make sure to map early */
#define CFG_BR3_PRELIM	CFG_BR3			/* in case it's used for ENV */

/*
 * BR4/OR4 - Board Control & Status (8 bit)
 */
#define	BCSR_BASE	0xFC000000
#define CFG_OR4		0xFFFF0120		/* BI (internal) */
#define CFG_BR4		((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)

/*
 * BR5/OR5 - IP Slot A/B (16 bit)
 */
#define	IP_SLOT_BASE	0x40000000
#define CFG_OR5		0xFE00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
#define CFG_BR5		((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)

/*
 * BR6/OR6 - VME STD  (16 bit)
 */
#define	VME_STD_BASE	0xFE000000
#define CFG_OR6		0xFF00010C		/* SETA/TRLX/BI/SCY=0  (external) */
#define CFG_BR6		((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)

/*
 * BR7/OR7 - SHORT I/O + RTC + IACK  (16 bit)
 */
#define VME_SHORT_BASE	0xFF000000
#define CFG_OR7		0xFF00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
#define CFG_BR7		((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)

/*-----------------------------------------------------------------------
 * Board Control and Status Region:
 *-----------------------------------------------------------------------
 */
#ifndef __ASSEMBLY__
typedef	struct ip860_bcsr_s {
	unsigned char	shmem_addr;	/* +00 shared memory address register	*/
	unsigned char	reserved0;
	unsigned char	mbox_addr;	/* +02 mailbox address register		*/
	unsigned char	reserved1;
	unsigned char	vme_int_mask;	/* +04 VME Bus interrupt mask register	*/
	unsigned char	reserved2;
	unsigned char	vme_int_pend;	/* +06 VME interrupt pending register	*/
	unsigned char	reserved3;
	unsigned char	bd_int_mask;	/* +08 board interrupt mask register	*/
	unsigned char	reserved4;
	unsigned char	bd_int_pend;	/* +0A board interrupt pending register	*/
	unsigned char	reserved5;
	unsigned char	bd_ctrl;	/* +0C board control register		*/
	unsigned char	reserved6;
	unsigned char	bd_status;	/* +0E board status  register		*/
	unsigned char	reserved7;
	unsigned char	vme_irq;	/* +10 VME interrupt request register	*/
	unsigned char	reserved8;
	unsigned char	vme_ivec;	/* +12 VME interrupt vector register	*/
	unsigned char	reserved9;
	unsigned char	cli_mbox;	/* +14 clear mailbox irq		*/
	unsigned char	reservedA;
	unsigned char	rtc;		/* +16 RTC control register		*/
	unsigned char	reservedB;
	unsigned char	mbox_data;	/* +18 mailbox read/write register	*/
	unsigned char	reservedC;
	unsigned char	wd_trigger;	/* +1A Watchdog trigger register	*/
	unsigned char	reservedD;
	unsigned char	rmw_req;	/* +1C RMW request register		*/
} ip860_bcsr_t;
#endif	/* __ASSEMBLY__ */

/*-----------------------------------------------------------------------
 * Board Control Register: bd_ctrl (Offset 0x0C)
 *-----------------------------------------------------------------------
 */
#define BD_CTRL_IPLSE	0x80	/* IP Slot Long Select Enable		*/
#define BD_CTRL_WDOGE	0x40	/* Watchdog Enable			*/
#define BD_CTRL_FLWE	0x20	/* Flash Write Enable			*/
#define BD_CTRL_RWDN	0x10	/* VMEBus Requester Release When Done Enable */

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
	37	#define CONFIG_IP860 1 /* ...on a IP860 board */
	38
	39	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	40	#define CONFIG_BAUDRATE 9600
	41	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	42
	43	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	44
	45	#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \
	46	"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 $(filesize)\0"
	47
	48	#define CONFIG_ETHADDR 00:30:bf:01:02:d2
	49	#define CONFIG_IPADDR 10.0.0.5
	50	#define CONFIG_SERVERIP 10.0.0.2
	51
	52	#undef CONFIG_BOOTARGS
	53	#define CONFIG_BOOTCOMMAND \
	54	"bootp; " \
	55	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	56	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
	57	"bootm"
	58
	59	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	60	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	61
	62	#undef CONFIG_WATCHDOG /* watchdog disabled */
	63
	64
65	/* enable I2C and select the hardware/software driver */
66	#undef CONFIG_HARD_I2C /* I2C with hardware support */
67	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
68	/*
69	* Software (bit-bang) I2C driver configuration
70	*/
71	#define PB_SCL 0x00000020 /* PB 26 */
72	#define PB_SDA 0x00000010 /* PB 27 */
73
74	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
75	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
76	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
77	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
78	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
79	else immr->im_cpm.cp_pbdat &= ~PB_SDA
80	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
81	else immr->im_cpm.cp_pbdat &= ~PB_SCL
82	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
83
84
85	# define CFG_I2C_SPEED 50000
86	# define CFG_I2C_SLAVE 0xFE
87	# define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
88	# define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
89	/* mask of address bits that overflow into the "EEPROM chip address" */
90	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
91	#define CFG_EEPROM_PAGE_WRITE_BITS 4
92	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
93
94	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
95	CFG_CMD_BEDBUG \| \
96	CFG_CMD_I2C \| \
97	CFG_CMD_EEPROM)
98
99	#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
100
101	/----------------------------------------------------------------------/
102
103	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
104	#include <cmd_confdefs.h>
105
106	/----------------------------------------------------------------------/
107
108	/*
109	* Miscellaneous configurable options
110	*/
111	#define CFG_LONGHELP /* undef to save memory */
112	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
113	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
114	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
115	#else
116	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
117	#endif
118	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
119	#define CFG_MAXARGS 16 /* max number of command args */
120	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
121
122	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
123	#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
124
125	#define CFG_LOAD_ADDR 0x00100000 /* default load address */
126
127	#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
128
129	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
130
131	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
132
133	/*
134	* Low Level Configuration Settings
135	* (address mappings, register initial values, etc.)
136	* You should know what you are doing if you make changes here.
137	*/
138	/*-----------------------------------------------------------------------
139	* Internal Memory Mapped Register
140	*/
141	#define CFG_IMMR 0xF1000000 /* Non-standard value!! */
142
143	/*-----------------------------------------------------------------------
144	* Definitions for initial stack pointer and data area (in DPRAM)
145	*/
146	#define CFG_INIT_RAM_ADDR CFG_IMMR
147	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
148	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
149	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
150	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
151
152	/*-----------------------------------------------------------------------
153	* Start addresses for the final memory configuration
154	* (Set up by the startup code)
155	* Please note that CFG_SDRAM_BASE _must_ start at 0
156	*/
157	#define CFG_SDRAM_BASE 0x00000000
158	#define CFG_FLASH_BASE 0x10000000
159	#ifdef DEBUG
160	#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
161	#else
162	#if 0 /* need more space for I2C tests */
163	#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
164	#else
165	#define CFG_MONITOR_LEN (256 << 10)
166	#endif
167	#endif
168	#define CFG_MONITOR_BASE CFG_FLASH_BASE
169	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
170
171	/*
172	* For booting Linux, the board info and command line data
173	* have to be in the first 8 MB of memory, since this is
174	* the maximum mapped by the Linux kernel during initialization.
175	*/
176	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
177	/*-----------------------------------------------------------------------
178	* FLASH organization
179	*/
180	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
181	#define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
182
183	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
184	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
185
186	#undef CFG_ENV_IS_IN_FLASH
187	#undef CFG_ENV_IS_IN_NVRAM
188	#undef CFG_ENV_IS_IN_NVRAM
189	#undef DEBUG_I2C
190	#define CFG_ENV_IS_IN_EEPROM
191
192	#ifdef CFG_ENV_IS_IN_NVRAM
193	#define CFG_ENV_ADDR 0x20000000 /* use SRAM */
194	#define CFG_ENV_SIZE (16<<10) /* use 16 kB */
195	#endif /* CFG_ENV_IS_IN_NVRAM */
196
197	#ifdef CFG_ENV_IS_IN_EEPROM
198	#define CFG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */
199	#define CFG_ENV_SIZE 1536 /* Use remaining space */
200	#endif /* CFG_ENV_IS_IN_EEPROM */
201
202	/*-----------------------------------------------------------------------
203	* Cache Configuration
204	*/
205	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
206	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
207	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
208	#endif
209
210	/*-----------------------------------------------------------------------
211	* SYPCR - System Protection Control 11-9
212	* SYPCR can only be written once after reset!
213	*-----------------------------------------------------------------------
214	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
215	* +0x0004
216	*/
217	#if defined(CONFIG_WATCHDOG)
218	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
219	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
220	#else
221	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
222	#endif
223
224	/*-----------------------------------------------------------------------
225	* SIUMCR - SIU Module Configuration 11-6
226	*-----------------------------------------------------------------------
227	* +0x0000 => 0x80600800
228	*/
229	#define CFG_SIUMCR (SIUMCR_EARB \| SIUMCR_EARP0 \| \
230	SIUMCR_DBGC11 \| SIUMCR_MLRC10)
231
232	/*-----------------------------------------------------------------------
233	* Clock Setting - the IP860 has no 32kHz clock, so automatic detection fails
234	*-----------------------------------------------------------------------
235	*/
236	#define CONFIG_8xx_GCLK_FREQ 50000000
237
238	/*-----------------------------------------------------------------------
239	* TBSCR - Time Base Status and Control 11-26
240	*-----------------------------------------------------------------------
241	* Clear Reference Interrupt Status, Timebase freezing enabled
242	* +0x0200 => 0x00C2
243	*/
244	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
245
246	/*-----------------------------------------------------------------------
247	* PISCR - Periodic Interrupt Status and Control 11-31
248	*-----------------------------------------------------------------------
249	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
250	* +0x0240 => 0x0082
251	*/
252	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
253
254	/*-----------------------------------------------------------------------
255	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
256	*-----------------------------------------------------------------------
257	* Reset PLL lock status sticky bit, timer expired status bit and timer
258	* interrupt status bit, set PLL multiplication factor !
259	*/
260	/* +0x0286 => was: 0x0000D000 */
261	#define CFG_PLPRCR \
262	( PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST \| \
263	/PLPRCR_CSRC\|/ PLPRCR_LPM_NORMAL \| \
264	PLPRCR_CSR \| PLPRCR_LOLRE /\|PLPRCR_FIOPD/ \
265	)
266
267	/*-----------------------------------------------------------------------
268	* SCCR - System Clock and reset Control Register 15-27
269	*-----------------------------------------------------------------------
270	* Set clock output, timebase and RTC source and divider,
271	* power management and some other internal clocks
272	*/
273	#define SCCR_MASK SCCR_EBDF11
274	#define CFG_SCCR (SCCR_COM00 \| SCCR_TBS \| \
275	SCCR_RTDIV \| SCCR_RTSEL \| \
276	/SCCR_CRQEN\|/ /SCCR_PRQEN\|/ \
277	SCCR_EBDF00 \| SCCR_DFSYNC00 \| \
278	SCCR_DFBRG00 \| SCCR_DFNL000 \| \
279	SCCR_DFNH000)
280
281	/*-----------------------------------------------------------------------
282	* RTCSC - Real-Time Clock Status and Control Register 11-27
283	*-----------------------------------------------------------------------
284	*/
285	/* +0x0220 => 0x00C3 */
286	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
287
288
289	/*-----------------------------------------------------------------------
290	* RCCR - RISC Controller Configuration Register 19-4
291	*-----------------------------------------------------------------------
292	*/
293	/* +0x09C4 => TIMEP=1 */
294	#define CFG_RCCR 0x0100
295
296	/*-----------------------------------------------------------------------
297	* RMDS - RISC Microcode Development Support Control Register
298	*-----------------------------------------------------------------------
299	*/
300	#define CFG_RMDS 0
301
302	/*-----------------------------------------------------------------------
303	* DER - Debug Event Register
304	*-----------------------------------------------------------------------
305	*
306	*/
307	/#define CFG_DER 0x2002000F/
308	#define CFG_DER 0
309
310	/*
311	* Init Memory Controller:
312	*/
313
314	/*
315	* MAMR settings for SDRAM - 16-14
316	* => 0xC3804114
317	*/
318
319	/* periodic timer for refresh */
320	#define CFG_MAMR_PTA 0xC3
321
322	#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
323	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
324	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
325	/*
326	* BR1 and OR1 (FLASH)
327	*/
328	#define FLASH_BASE 0x10000000 /* FLASH bank #0 */
329
330	/* used to re-map FLASH
331	* restrict access enough to keep SRAM working (if any)
332	* but not too much to meddle with FLASH accesses
333	*/
334	/* allow for max 8 MB of Flash */
335	#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */
336	#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
337
338	#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV2 \| OR_BI \| OR_SCY_6_CLK)
339
340	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
341	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
342	/* 16 bit, bank valid */
343	#define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) \| BR_PS_32 \| BR_V )
344
345	#define CFG_OR1_PRELIM CFG_OR0_PRELIM
346	#define CFG_BR1_PRELIM CFG_BR0_PRELIM
347
348	/*
349	* BR2/OR2 - SDRAM
350	*/
351	#define SDRAM_BASE 0x00000000 /* SDRAM bank */
352	#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
353	#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
354
355	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
356
357	#define CFG_OR2 (SDRAM_PRELIM_OR_AM \| SDRAM_TIMING )
358	#define CFG_BR2 ((SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
359
360	/*
361	* BR3/OR3 - SRAM (16 bit)
362	*/
363	#define SRAM_BASE 0x20000000
364	#define CFG_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */
365	#define CFG_BR3 ((SRAM_BASE & BR_BA_MSK) \| BR_PS_16 \| BR_V)
366	#define SRAM_SIZE (1 + (~(CFG_OR3 & BR_BA_MSK)))
367	#define CFG_OR3_PRELIM CFG_OR3 /* Make sure to map early */
368	#define CFG_BR3_PRELIM CFG_BR3 /* in case it's used for ENV */
369
370	/*
371	* BR4/OR4 - Board Control & Status (8 bit)
372	*/
373	#define BCSR_BASE 0xFC000000
374	#define CFG_OR4 0xFFFF0120 /* BI (internal) */
375	#define CFG_BR4 ((BCSR_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V)
376
377	/*
378	* BR5/OR5 - IP Slot A/B (16 bit)
379	*/
380	#define IP_SLOT_BASE 0x40000000
381	#define CFG_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */
382	#define CFG_BR5 ((IP_SLOT_BASE & BR_BA_MSK) \| BR_PS_16 \| BR_V)
383
384	/*
385	* BR6/OR6 - VME STD (16 bit)
386	*/
387	#define VME_STD_BASE 0xFE000000
388	#define CFG_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */
389	#define CFG_BR6 ((VME_STD_BASE & BR_BA_MSK) \| BR_PS_16 \| BR_V)
390
391	/*
392	* BR7/OR7 - SHORT I/O + RTC + IACK (16 bit)
393	*/
394	#define VME_SHORT_BASE 0xFF000000
395	#define CFG_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */
396	#define CFG_BR7 ((VME_SHORT_BASE & BR_BA_MSK) \| BR_PS_16 \| BR_V)
397
398	/*-----------------------------------------------------------------------
399	* Board Control and Status Region:
400	*-----------------------------------------------------------------------
401	*/
402	#ifndef __ASSEMBLY__
403	typedef struct ip860_bcsr_s {
404	unsigned char shmem_addr; /* +00 shared memory address register */
405	unsigned char reserved0;
406	unsigned char mbox_addr; /* +02 mailbox address register */
407	unsigned char reserved1;
408	unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */
409	unsigned char reserved2;
410	unsigned char vme_int_pend; /* +06 VME interrupt pending register */
411	unsigned char reserved3;
412	unsigned char bd_int_mask; /* +08 board interrupt mask register */
413	unsigned char reserved4;
414	unsigned char bd_int_pend; /* +0A board interrupt pending register */
415	unsigned char reserved5;
416	unsigned char bd_ctrl; /* +0C board control register */
417	unsigned char reserved6;
418	unsigned char bd_status; /* +0E board status register */
419	unsigned char reserved7;
420	unsigned char vme_irq; /* +10 VME interrupt request register */
421	unsigned char reserved8;
422	unsigned char vme_ivec; /* +12 VME interrupt vector register */
423	unsigned char reserved9;
424	unsigned char cli_mbox; /* +14 clear mailbox irq */
425	unsigned char reservedA;
426	unsigned char rtc; /* +16 RTC control register */
427	unsigned char reservedB;
428	unsigned char mbox_data; /* +18 mailbox read/write register */
429	unsigned char reservedC;
430	unsigned char wd_trigger; /* +1A Watchdog trigger register */
431	unsigned char reservedD;
432	unsigned char rmw_req; /* +1C RMW request register */
433	} ip860_bcsr_t;
434	#endif /* __ASSEMBLY__ */
435
436	/*-----------------------------------------------------------------------
437	* Board Control Register: bd_ctrl (Offset 0x0C)
438	*-----------------------------------------------------------------------
439	*/
440	#define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */
441	#define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */
442	#define BD_CTRL_FLWE 0x20 /* Flash Write Enable */
443	#define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */
444
445	/*-----------------------------------------------------------------------
446	*
447	*-----------------------------------------------------------------------
448	*
449	*/
450
451	/*
452	* Internal Definitions
453	*
454	* Boot Flags
455	*/
456	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
457	#define BOOTFLAG_WARM 0x02 /* Software reboot */
458
459	#endif /* __CONFIG_H */