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Merge tag 'v2023.10-rc4' into next
[J-u-boot.git] / board / sunxi / board.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
cba69eee
IC		 2/*
3 * (C) Copyright 2012-2013 Henrik Nordstrom <[email protected]>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <[email protected]>
5 *
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <[email protected]>
9 *
10 * Some board init for the Allwinner A10-evb board.
cba69eee
IC		 11 */
12
13#include <common.h>
2f8a6db5 14#include <clock_legacy.h>
237050fc 15#include <dm.h>
c7694dd4 16#include <env.h>
db41d65a 17#include <hang.h>
4d72caa5 18#include <image.h>
9b4a205f 19#include <init.h>
f7ae49fc 20#include <log.h>
e79c7c88 21#include <mmc.h>
6944aff1 22#include <axp_pmic.h>
237050fc
JT		 23#include <generic-phy.h>
24#include <phy-sun4i-usb.h>
cba69eee 25#include <asm/arch/clock.h>
b41d7d05 26#include <asm/arch/cpu.h>
2d7a084b 27#include <asm/arch/display.h>
cba69eee 28#include <asm/arch/dram.h>
e24ea55c 29#include <asm/arch/mmc.h>
8a8b73b6 30#include <asm/arch/prcm.h>
52bcc4f0 31#include <asm/arch/pmic_bus.h>
4a8c7c1f 32#include <asm/arch/spl.h>
e943753d 33#include <asm/arch/sys_proto.h>
401d1c4f 34#include <asm/global_data.h>
c05ed00a 35#include <linux/delay.h>
d96ebc46
SS		 36#ifndef CONFIG_ARM64
37#include <asm/armv7.h>
38#endif
4f7e01c9 39#include <asm/gpio.h>
b41d7d05 40#include <asm/io.h>
a740ee91 41#include <u-boot/crc.h>
f3998fdc 42#include <env_internal.h>
b08c8c48 43#include <linux/libfdt.h>
9267ff89 44#include <fdt_support.h>
f62bfa56 45#include <nand.h>
b41d7d05 46#include <net.h>
f4c3523c 47#include <spl.h>
0d8382ae 48#include <sy8106a.h>
5d982856 49#include <asm/setup.h>
8f872bb3 50#include <status_led.h>
cba69eee
IC		 51
52DECLARE_GLOBAL_DATA_PTR;
53
acbc7e0a
JS		 54void i2c_init_board(void)
55{
56#ifdef CONFIG_I2C0_ENABLE
57#if defined(CONFIG_MACH_SUN4I) || \
58 defined(CONFIG_MACH_SUN5I) || \
59 defined(CONFIG_MACH_SUN7I) || \
60 defined(CONFIG_MACH_SUN8I_R40)
61 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
62 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
63 clock_twi_onoff(0, 1);
64#elif defined(CONFIG_MACH_SUN6I)
65 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
66 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
67 clock_twi_onoff(0, 1);
8c51c652
IZ		 68#elif defined(CONFIG_MACH_SUN8I_V3S)
69 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
70 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
71 clock_twi_onoff(0, 1);
acbc7e0a
JS		 72#elif defined(CONFIG_MACH_SUN8I)
73 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
74 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
75 clock_twi_onoff(0, 1);
da1ae590
SM		 76#elif defined(CONFIG_MACH_SUN50I)
77 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
78 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
79 clock_twi_onoff(0, 1);
acbc7e0a
JS		 80#endif
81#endif
82
83#ifdef CONFIG_I2C1_ENABLE
84#if defined(CONFIG_MACH_SUN4I) || \
85 defined(CONFIG_MACH_SUN7I) || \
86 defined(CONFIG_MACH_SUN8I_R40)
87 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
88 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
89 clock_twi_onoff(1, 1);
90#elif defined(CONFIG_MACH_SUN5I)
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
92 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
93 clock_twi_onoff(1, 1);
94#elif defined(CONFIG_MACH_SUN6I)
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
96 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
97 clock_twi_onoff(1, 1);
98#elif defined(CONFIG_MACH_SUN8I)
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
100 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
101 clock_twi_onoff(1, 1);
da1ae590
SM		 102#elif defined(CONFIG_MACH_SUN50I)
103 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
105 clock_twi_onoff(1, 1);
acbc7e0a
JS		 106#endif
107#endif
108
acbc7e0a 109#ifdef CONFIG_R_I2C_ENABLE
31a4ac4d
VK		 110#ifdef CONFIG_MACH_SUN50I
111 clock_twi_onoff(5, 1);
112 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
113 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
d0b07c15
JS		 114#elif CONFIG_MACH_SUN50I_H616
115 clock_twi_onoff(5, 1);
116 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
117 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
31a4ac4d 118#else
acbc7e0a
JS		 119 clock_twi_onoff(5, 1);
120 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
121 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
122#endif
31a4ac4d 123#endif
acbc7e0a
JS		 124}
125
e42dad41
AP		 126/*
127 * Try to use the environment from the boot source first.
128 * For MMC, this means a FAT partition on the boot device (SD or eMMC).
129 * If the raw MMC environment is also enabled, this is tried next.
e008e513 130 * When booting from NAND we try UBI first, then NAND directly.
e42dad41
AP		 131 * SPI flash falls back to FAT (on SD card).
132 */
b39117ca
MR		 133enum env_location env_get_location(enum env_operation op, int prio)
134{
e008e513
SH		 135 if (prio > 1)
136 return ENVL_UNKNOWN;
e42dad41 137
e008e513
SH		 138 /* NOWHERE is exclusive, no other option can be defined. */
139 if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
140 return ENVL_NOWHERE;
e42dad41
AP		 141
142 switch (sunxi_get_boot_device()) {
143 case BOOT_DEVICE_MMC1:
144 case BOOT_DEVICE_MMC2:
e008e513
SH		 145 if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
146 return ENVL_FAT;
147 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
148 return ENVL_MMC;
e42dad41
AP		 149 break;
150 case BOOT_DEVICE_NAND:
e008e513
SH		 151 if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
152 return ENVL_UBI;
e42dad41 153 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
e008e513 154 return ENVL_NAND;
e42dad41
AP		 155 break;
156 case BOOT_DEVICE_SPI:
e008e513
SH		 157 if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
158 return ENVL_SPI_FLASH;
159 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
160 return ENVL_FAT;
e42dad41
AP		 161 break;
162 case BOOT_DEVICE_BOARD:
163 break;
b39117ca 164 default:
e42dad41 165 break;
b39117ca 166 }
e42dad41 167
e008e513
SH		 168 /*
169 * If we come here for the first time, we *must* return a valid
170 * environment location other than ENVL_UNKNOWN, or the setup sequence
171 * in board_f() will silently hang. This is arguably a bug in
172 * env_init(), but for now pick one environment for which we know for
173 * sure to have a driver for. For all defconfigs this is either FAT
174 * or UBI, or NOWHERE, which is already handled above.
175 */
176 if (prio == 0) {
177 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
e42dad41 178 return ENVL_FAT;
e008e513
SH		 179 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
180 return ENVL_UBI;
e42dad41
AP		 181 }
182
183 return ENVL_UNKNOWN;
b39117ca 184}
b39117ca 185
cba69eee
IC		 186/* add board specific code here */
187int board_init(void)
188{
f5fd7886 189 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
cba69eee
IC		 190
191 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
192
116e1ed1 193#if !defined(CONFIG_ARM64) && !defined(CONFIG_MACH_SUNIV)
cba69eee
IC		 194 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
195 debug("id_pfr1: 0x%08x\n", id_pfr1);
196 /* Generic Timer Extension available? */
d96ebc46
SS		 197 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
198 uint32_t freq;
199
cba69eee 200 debug("Setting CNTFRQ\n");
d96ebc46
SS		 201
202 /*
203 * CNTFRQ is a secure register, so we will crash if we try to
204 * write this from the non-secure world (read is OK, though).
205 * In case some bootcode has already set the correct value,
206 * we avoid the risk of writing to it.
207 */
208 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
151a0300 209 if (freq != CONFIG_COUNTER_FREQUENCY) {
d96ebc46 210 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
151a0300 211 freq, CONFIG_COUNTER_FREQUENCY);
d96ebc46
SS		 212#ifdef CONFIG_NON_SECURE
213 printf("arch timer frequency is wrong, but cannot adjust it\n");
214#else
215 asm volatile("mcr p15, 0, %0, c14, c0, 0"
151a0300 216 : : "r"(CONFIG_COUNTER_FREQUENCY));
d96ebc46
SS		 217#endif
218 }
cba69eee 219 }
116e1ed1 220#endif /* !CONFIG_ARM64 && !CONFIG_MACH_SUNIV */
cba69eee 221
2fcf033d
HG		 222 ret = axp_gpio_init();
223 if (ret)
224 return ret;
225
e9ad1b8d
AP		 226 /* strcmp() would look better, but doesn't get optimised away. */
227 if (CONFIG_SATAPWR[0]) {
228 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
229 if (satapwr_pin >= 0) {
230 gpio_request(satapwr_pin, "satapwr");
231 gpio_direction_output(satapwr_pin, 1);
232
233 /*
234 * Give the attached SATA device time to power-up
235 * to avoid link timeouts
236 */
237 mdelay(500);
238 }
239 }
240
241 if (CONFIG_MACPWR[0]) {
242 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
243 if (macpwr_pin >= 0) {
244 gpio_request(macpwr_pin, "macpwr");
245 gpio_direction_output(macpwr_pin, 1);
246 }
247 }
fc8991c6 248
2147a169 249#if CONFIG_IS_ENABLED(DM_I2C)
a8f01ccf
JS		 250 /*
251 * Temporary workaround for enabling I2C clocks until proper sunxi DM
252 * clk, reset and pinctrl drivers land.
253 */
254 i2c_init_board();
255#endif
256
e943753d
AP		 257 eth_init_board();
258
2421497c 259 return 0;
cba69eee
IC		 260}
261
cff5c138
AP		 262/*
263 * On older SoCs the SPL is actually at address zero, so using NULL as
264 * an error value does not work.
265 */
266#define INVALID_SPL_HEADER ((void *)~0UL)
267
268static struct boot_file_head * get_spl_header(uint8_t req_version)
269{
270 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
271 uint8_t spl_header_version = spl->spl_signature[3];
272
273 /* Is there really the SPL header (still) there? */
274 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
275 return INVALID_SPL_HEADER;
276
277 if (spl_header_version < req_version) {
278 printf("sunxi SPL version mismatch: expected %u, got %u\n",
279 req_version, spl_header_version);
280 return INVALID_SPL_HEADER;
281 }
282
283 return spl;
284}
285
467b7e52
SH		 286static const char *get_spl_dt_name(void)
287{
288 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
289
290 /* Check if there is a DT name stored in the SPL header. */
291 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
292 return (char *)spl + spl->dt_name_offset;
293
294 return NULL;
295}
467b7e52 296
cba69eee
IC		 297int dram_init(void)
298{
5776610e
AP		 299 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
300
301 if (spl == INVALID_SPL_HEADER)
302 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
303 PHYS_SDRAM_0_SIZE);
304 else
305 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
306
307 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
308 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
cba69eee
IC		 309
310 return 0;
311}
312
21b790fd 313#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
ad008299
KG		 314static void nand_pinmux_setup(void)
315{
316 unsigned int pin;
ad008299 317
022a99d8 318 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
ad008299
KG		 319 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
320
022a99d8
HG		 321#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
322 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
323 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
324#endif
325 /* sun4i / sun7i do have a PC23, but it is not used for nand,
326 * only sun7i has a PC24 */
327#ifdef CONFIG_MACH_SUN7I
ad008299 328 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
022a99d8 329#endif
ad008299
KG		 330}
331
332static void nand_clock_setup(void)
333{
334 struct sunxi_ccm_reg *const ccm =
335 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
31c21471 336
ad008299 337 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
ba1c98ba
MR		 338#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
339 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
340 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
31c21471 341#endif
ad008299
KG		 342 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
343}
f62bfa56
HG		 344
345void board_nand_init(void)
346{
347 nand_pinmux_setup();
348 nand_clock_setup();
349}
64531496 350#endif /* CONFIG_NAND_SUNXI */
ad008299 351
4aa2ba3a 352#ifdef CONFIG_MMC
e24ea55c
IC		 353static void mmc_pinmux_setup(int sdc)
354{
355 unsigned int pin;
356
357 switch (sdc) {
358 case 0:
8deacca9 359 /* SDC0: PF0-PF5 */
e24ea55c 360 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
487b3277 361 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
e24ea55c
IC		 362 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
363 sunxi_gpio_set_drv(pin, 2);
364 }
365 break;
366
367 case 1:
8094a4a2
CYT		 368#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
369 defined(CONFIG_MACH_SUN8I_R40)
dda9fa73 370 if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) {
8deacca9
PK		 371 /* SDC1: PH22-PH-27 */
372 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
373 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
374 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
375 sunxi_gpio_set_drv(pin, 2);
376 }
377 } else {
378 /* SDC1: PG0-PG5 */
379 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
380 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
381 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
382 sunxi_gpio_set_drv(pin, 2);
383 }
384 }
385#elif defined(CONFIG_MACH_SUN5I)
386 /* SDC1: PG3-PG8 */
bbff84b3 387 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
487b3277 388 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
e24ea55c
IC		 389 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
390 sunxi_gpio_set_drv(pin, 2);
391 }
8deacca9
PK		 392#elif defined(CONFIG_MACH_SUN6I)
393 /* SDC1: PG0-PG5 */
394 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
395 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
396 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
397 sunxi_gpio_set_drv(pin, 2);
398 }
399#elif defined(CONFIG_MACH_SUN8I)
dda9fa73
SH		 400 /* SDC1: PG0-PG5 */
401 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
402 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
403 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
404 sunxi_gpio_set_drv(pin, 2);
8deacca9
PK		 405 }
406#endif
e24ea55c
IC		 407 break;
408
409 case 2:
8deacca9
PK		 410#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
411 /* SDC2: PC6-PC11 */
e24ea55c 412 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
487b3277 413 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
e24ea55c
IC		 414 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
415 sunxi_gpio_set_drv(pin, 2);
416 }
8deacca9 417#elif defined(CONFIG_MACH_SUN5I)
dda9fa73
SH		 418 /* SDC2: PC6-PC15 */
419 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
420 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
421 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
422 sunxi_gpio_set_drv(pin, 2);
8deacca9
PK		 423 }
424#elif defined(CONFIG_MACH_SUN6I)
dda9fa73
SH		 425 /* SDC2: PC6-PC15, PC24 */
426 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
427 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
428 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
429 sunxi_gpio_set_drv(pin, 2);
8deacca9 430 }
dda9fa73
SH		 431
432 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
433 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
434 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
8094a4a2
CYT		 435#elif defined(CONFIG_MACH_SUN8I_R40)
436 /* SDC2: PC6-PC15, PC24 */
437 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
438 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
439 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
440 sunxi_gpio_set_drv(pin, 2);
441 }
442
443 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
444 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
445 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
d96ebc46 446#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
8deacca9
PK		 447 /* SDC2: PC5-PC6, PC8-PC16 */
448 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
449 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
450 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
451 sunxi_gpio_set_drv(pin, 2);
452 }
453
454 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
455 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
456 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
457 sunxi_gpio_set_drv(pin, 2);
42956f1b
IZ		 458 }
459#elif defined(CONFIG_MACH_SUN50I_H6)
460 /* SDC2: PC4-PC14 */
461 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
462 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
463 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
464 sunxi_gpio_set_drv(pin, 2);
8deacca9 465 }
212224ed
AP		 466#elif defined(CONFIG_MACH_SUN50I_H616)
467 /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */
468 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) {
469 if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5))
470 continue;
471 if (pin == SUNXI_GPC(7) || pin == SUNXI_GPC(12))
472 continue;
473 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
474 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
475 sunxi_gpio_set_drv(pin, 3);
476 }
3ebb4567
PT		 477#elif defined(CONFIG_MACH_SUN9I)
478 /* SDC2: PC6-PC16 */
479 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
480 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
481 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
482 sunxi_gpio_set_drv(pin, 2);
483 }
212224ed
AP		 484#else
485 puts("ERROR: No pinmux setup defined for MMC2!\n");
8deacca9 486#endif
e24ea55c
IC		 487 break;
488
489 case 3:
8094a4a2
CYT		 490#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
491 defined(CONFIG_MACH_SUN8I_R40)
8deacca9 492 /* SDC3: PI4-PI9 */
e24ea55c 493 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
8deacca9 494 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
e24ea55c
IC		 495 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
496 sunxi_gpio_set_drv(pin, 2);
497 }
8deacca9 498#elif defined(CONFIG_MACH_SUN6I)
dda9fa73
SH		 499 /* SDC3: PC6-PC15, PC24 */
500 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
501 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
502 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
503 sunxi_gpio_set_drv(pin, 2);
8deacca9 504 }
dda9fa73
SH		 505
506 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
507 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
508 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
8deacca9 509#endif
e24ea55c
IC		 510 break;
511
512 default:
513 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
514 break;
515 }
516}
517
b75d8dc5 518int board_mmc_init(struct bd_info *bis)
e24ea55c 519{
ed82586c
AP		 520 /*
521 * The BROM always accesses MMC port 0 (typically an SD card), and
522 * most boards seem to have such a slot. The others haven't reported
523 * any problem with unconditionally enabling this in the SPL.
524 */
3ba0a25c 525 if (!IS_ENABLED(CONFIG_UART0_PORT_F)) {
ed82586c
AP		 526 mmc_pinmux_setup(0);
527 if (!sunxi_mmc_init(0))
3ba0a25c
SH		 528 return -1;
529 }
e79c7c88 530
3ba0a25c
SH		 531 if (CONFIG_MMC_SUNXI_SLOT_EXTRA != -1) {
532 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
533 if (!sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA))
534 return -1;
535 }
e79c7c88 536
e24ea55c
IC		 537 return 0;
538}
1011ebc7
SH		 539
540#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
541int mmc_get_env_dev(void)
542{
543 switch (sunxi_get_boot_device()) {
544 case BOOT_DEVICE_MMC1:
545 return 0;
546 case BOOT_DEVICE_MMC2:
547 return 1;
548 default:
549 return CONFIG_SYS_MMC_ENV_DEV;
550 }
551}
552#endif
64531496 553#endif /* CONFIG_MMC */
e24ea55c 554
cba69eee 555#ifdef CONFIG_SPL_BUILD
5776610e
AP		 556
557static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
558{
559 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
560
561 if (spl == INVALID_SPL_HEADER)
562 return;
563
564 /* Promote the header version for U-Boot proper, if needed. */
565 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
566 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
567
568 spl->dram_size = dram_size >> 20;
569}
570
cba69eee
IC		 571void sunxi_board_init(void)
572{
14bc66bd 573 int power_failed = 0;
cba69eee 574
8f872bb3
AF		 575#ifdef CONFIG_LED_STATUS
576 if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
577 status_led_init();
578#endif
579
0d8382ae
JW		 580#ifdef CONFIG_SY8106A_POWER
581 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
582#endif
583
95ab8fee 584#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
fbd37d8d
JS		 585 defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
586 defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
6944aff1
HG		 587 power_failed = axp_init();
588
52bcc4f0
CM		 589 if (IS_ENABLED(CONFIG_AXP_DISABLE_BOOT_ON_POWERON) && !power_failed) {
590 u8 boot_reason;
591
592 pmic_bus_read(AXP_POWER_STATUS, &boot_reason);
593 if (boot_reason & AXP_POWER_STATUS_ALDO_IN) {
594 printf("Power on by plug-in, shutting down.\n");
595 pmic_bus_write(0x32, BIT(7));
596 }
597 }
598
795857df
CYT		 599#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
600 defined CONFIG_AXP818_POWER
6944aff1 601 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
24289208 602#endif
fbd37d8d 603#if !defined(CONFIG_AXP305_POWER)
6944aff1
HG		 604 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
605 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
fbd37d8d 606#endif
95ab8fee 607#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
6944aff1 608 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
5c7f10fd 609#endif
795857df
CYT		 610#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
611 defined CONFIG_AXP818_POWER
6944aff1 612 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
14bc66bd
HN		 613#endif
614
795857df
CYT		 615#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
616 defined CONFIG_AXP818_POWER
6944aff1
HG		 617 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
618#endif
fbd37d8d 619#if !defined(CONFIG_AXP305_POWER)
6944aff1 620 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
fbd37d8d
JS		 621#endif
622#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
6944aff1
HG		 623 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
624#endif
625#ifdef CONFIG_AXP209_POWER
626 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
627#endif
628
795857df
CYT		 629#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
630 defined(CONFIG_AXP818_POWER)
3517a27d
CYT		 631 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
632 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
795857df 633#if !defined CONFIG_AXP809_POWER
3517a27d
CYT		 634 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
635 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
795857df 636#endif
6944aff1
HG		 637 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
638 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
639 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
640#endif
38491d9c
CYT		 641
642#ifdef CONFIG_AXP818_POWER
643 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
644 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
645 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
795857df
CYT		 646#endif
647
648#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
15278ccb 649 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
38491d9c 650#endif
6944aff1 651#endif
44c214dc
FKP		 652 printf("DRAM:");
653 gd->ram_size = sunxi_dram_init();
654 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
655 if (!gd->ram_size)
656 hang();
657
658 sunxi_spl_store_dram_size(gd->ram_size);
5776610e 659
14bc66bd
HN		 660 /*
661 * Only clock up the CPU to full speed if we are reasonably
662 * assured it's being powered with suitable core voltage
663 */
664 if (!power_failed)
2f8a6db5 665 clock_set_pll1(get_board_sys_clk());
14bc66bd 666 else
44c214dc 667 printf("Failed to set core voltage! Can't set CPU frequency\n");
cba69eee 668}
64531496 669#endif /* CONFIG_SPL_BUILD */
b41d7d05 670
f1df758d
PK		 671#ifdef CONFIG_USB_GADGET
672int g_dnl_board_usb_cable_connected(void)
673{
237050fc
JT		 674 struct udevice *dev;
675 struct phy phy;
676 int ret;
677
01311624 678 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
237050fc
JT		 679 if (ret) {
680 pr_err("%s: Cannot find USB device\n", __func__);
681 return ret;
682 }
683
684 ret = generic_phy_get_by_name(dev, "usb", &phy);
685 if (ret) {
686 pr_err("failed to get %s USB PHY\n", dev->name);
687 return ret;
688 }
689
690 ret = generic_phy_init(&phy);
691 if (ret) {
f286e37c 692 pr_debug("failed to init %s USB PHY\n", dev->name);
237050fc
JT		 693 return ret;
694 }
695
fbd9207e 696 return sun4i_usb_phy_vbus_detect(&phy);
f1df758d 697}
64531496 698#endif /* CONFIG_USB_GADGET */
f1df758d 699
9f852211
PK		 700#ifdef CONFIG_SERIAL_TAG
701void get_board_serial(struct tag_serialnr *serialnr)
702{
703 char *serial_string;
704 unsigned long long serial;
705
00caae6d 706 serial_string = env_get("serial#");
9f852211
PK		 707
708 if (serial_string) {
709 serial = simple_strtoull(serial_string, NULL, 16);
710
711 serialnr->high = (unsigned int) (serial >> 32);
712 serialnr->low = (unsigned int) (serial & 0xffffffff);
713 } else {
714 serialnr->high = 0;
715 serialnr->low = 0;
716 }
717}
718#endif
719
af654d14
BN		 720/*
721 * Check the SPL header for the "sunxi" variant. If found: parse values
722 * that might have been passed by the loader ("fel" utility), and update
723 * the environment accordingly.
724 */
725static void parse_spl_header(const uint32_t spl_addr)
726{
cff5c138 727 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
320e0570 728
cff5c138 729 if (spl == INVALID_SPL_HEADER)
320e0570 730 return;
cff5c138 731
320e0570
BN		 732 if (!spl->fel_script_address)
733 return;
734
735 if (spl->fel_uEnv_length != 0) {
736 /*
737 * data is expected in uEnv.txt compatible format, so "env
738 * import -t" the string(s) at fel_script_address right away.
739 */
5a74a391 740 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
320e0570
BN		 741 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
742 return;
af654d14 743 }
320e0570 744 /* otherwise assume .scr format (mkimage-type script) */
018f5303 745 env_set_hex("fel_scriptaddr", spl->fel_script_address);
af654d14 746}
af654d14 747
928f4f48
AH		 748static bool get_unique_sid(unsigned int *sid)
749{
750 if (sunxi_get_sid(sid) != 0)
751 return false;
752
753 if (!sid[0])
754 return false;
755
756 /*
757 * The single words 1 - 3 of the SID have quite a few bits
758 * which are the same on many models, so we take a crc32
759 * of all 3 words, to get a more unique value.
760 *
761 * Note we only do this on newer SoCs as we cannot change
762 * the algorithm on older SoCs since those have been using
763 * fixed mac-addresses based on only using word 3 for a
764 * long time and changing a fixed mac-address with an
765 * u-boot update is not good.
766 */
767#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
768 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
769 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
770 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
771#endif
772
773 /* Ensure the NIC specific bytes of the mac are not all 0 */
774 if ((sid[3] & 0xffffff) == 0)
775 sid[3] |= 0x800000;
776
777 return true;
778}
779
f221961e
HG		 780/*
781 * Note this function gets called multiple times.
782 * It must not make any changes to env variables which already exist.
783 */
784static void setup_environment(const void *fdt)
b41d7d05 785{
8c816573 786 char serial_string[17] = { 0 };
cac5b1cc 787 unsigned int sid[4];
8c816573 788 uint8_t mac_addr[6];
f221961e 789 char ethaddr[16];
928f4f48 790 int i;
3f8ea3b0 791
928f4f48
AH		 792 if (!get_unique_sid(sid))
793 return;
97322c3e 794
928f4f48
AH		 795 for (i = 0; i < 4; i++) {
796 sprintf(ethaddr, "ethernet%d", i);
797 if (!fdt_get_alias(fdt, ethaddr))
798 continue;
f221961e 799
928f4f48
AH		 800 if (i == 0)
801 strcpy(ethaddr, "ethaddr");
802 else
803 sprintf(ethaddr, "eth%daddr", i);
f221961e 804
928f4f48
AH		 805 if (env_get(ethaddr))
806 continue;
f221961e 807
928f4f48
AH		 808 /* Non OUI / registered MAC address */
809 mac_addr[0] = (i << 4) | 0x02;
810 mac_addr[1] = (sid[0] >> 0) & 0xff;
811 mac_addr[2] = (sid[3] >> 24) & 0xff;
812 mac_addr[3] = (sid[3] >> 16) & 0xff;
813 mac_addr[4] = (sid[3] >> 8) & 0xff;
814 mac_addr[5] = (sid[3] >> 0) & 0xff;
8c816573 815
928f4f48
AH		 816 eth_env_set_enetaddr(ethaddr, mac_addr);
817 }
b41d7d05 818
928f4f48
AH		 819 if (!env_get("serial#")) {
820 snprintf(serial_string, sizeof(serial_string),
821 "%08x%08x", sid[0], sid[3]);
b41d7d05 822
928f4f48 823 env_set("serial#", serial_string);
b41d7d05 824 }
f221961e
HG		 825}
826
f221961e
HG		 827int misc_init_r(void)
828{
20f3ee31 829 const char *spl_dt_name;
f4c3523c 830 uint boot;
f221961e 831
382bee57
SG		 832 env_set("fel_booted", NULL);
833 env_set("fel_scriptaddr", NULL);
de86fc38 834 env_set("mmc_bootdev", NULL);
f4c3523c
MR		 835
836 boot = sunxi_get_boot_device();
f221961e 837 /* determine if we are running in FEL mode */
f4c3523c 838 if (boot == BOOT_DEVICE_BOARD) {
382bee57 839 env_set("fel_booted", "1");
f221961e 840 parse_spl_header(SPL_ADDR);
de86fc38
MR		 841 /* or if we booted from MMC, and which one */
842 } else if (boot == BOOT_DEVICE_MMC1) {
843 env_set("mmc_bootdev", "0");
844 } else if (boot == BOOT_DEVICE_MMC2) {
845 env_set("mmc_bootdev", "1");
f221961e 846 }
f221961e 847
20f3ee31
SH		 848 /* Set fdtfile to match the FIT configuration chosen in SPL. */
849 spl_dt_name = get_spl_dt_name();
850 if (spl_dt_name) {
851 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
852 char str[64];
853
854 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
855 env_set("fdtfile", str);
856 }
857
f221961e 858 setup_environment(gd->fdt_blob);
b41d7d05 859
92600edb
AS		 860 return 0;
861}
862
863int board_late_init(void)
864{
e6ee85a6 865#ifdef CONFIG_USB_ETHER
90dd2f19 866 usb_ether_init();
e6ee85a6 867#endif
90dd2f19 868
b41d7d05
JL		 869 return 0;
870}
2d7a084b 871
9267ff89
AH		 872static void bluetooth_dt_fixup(void *blob)
873{
874 /* Some devices ship with a Bluetooth controller default address.
875 * Set a valid address through the device tree.
876 */
877 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
878 unsigned int sid[4];
879 int i;
880
881 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
882 return;
883
884 if (eth_env_get_enetaddr("bdaddr", tmp)) {
885 /* Convert between the binary formats of the corresponding stacks */
886 for (i = 0; i < ETH_ALEN; ++i)
887 bdaddr[i] = tmp[ETH_ALEN - i - 1];
888 } else {
889 if (!get_unique_sid(sid))
890 return;
891
892 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
893 bdaddr[1] = (sid[3] >> 8) & 0xff;
894 bdaddr[2] = (sid[3] >> 16) & 0xff;
895 bdaddr[3] = (sid[3] >> 24) & 0xff;
896 bdaddr[4] = (sid[0] >> 0) & 0xff;
897 bdaddr[5] = 0x02;
898 }
899
900 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
901 "local-bd-address", bdaddr, ETH_ALEN, 1);
902}
903
b75d8dc5 904int ft_board_setup(void *blob, struct bd_info *bd)
2d7a084b 905{
d75111a7
HG		 906 int __maybe_unused r;
907
f221961e 908 /*
2753b072
IZ		 909 * Call setup_environment and fdt_fixup_ethernet again
910 * in case the boot fdt has ethernet aliases the u-boot
911 * copy does not have.
f221961e
HG		 912 */
913 setup_environment(blob);
2753b072 914 fdt_fixup_ethernet(blob);
f221961e 915
9267ff89
AH		 916 bluetooth_dt_fixup(blob);
917
2d7a084b 918#ifdef CONFIG_VIDEO_DT_SIMPLEFB
d75111a7
HG		 919 r = sunxi_simplefb_setup(blob);
920 if (r)
921 return r;
2d7a084b 922#endif
d75111a7 923 return 0;
2d7a084b 924}
9ea3c35a
AP		 925
926#ifdef CONFIG_SPL_LOAD_FIT
41530cf6
SH		 927static void set_spl_dt_name(const char *name)
928{
929 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
930
931 if (spl == INVALID_SPL_HEADER)
932 return;
933
934 /* Promote the header version for U-Boot proper, if needed. */
935 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
936 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
937
938 strcpy((char *)&spl->string_pool, name);
939 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
940}
941
9ea3c35a
AP		 942int board_fit_config_name_match(const char *name)
943{
467b7e52 944 const char *best_dt_name = get_spl_dt_name();
41530cf6 945 int ret;
9ea3c35a
AP		 946
947#ifdef CONFIG_DEFAULT_DEVICE_TREE
467b7e52 948 if (best_dt_name == NULL)
2fcd7489 949 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
9ea3c35a
AP		 950#endif
951
467b7e52
SH		 952 if (best_dt_name == NULL) {
953 /* No DT name was provided, so accept the first config. */
954 return 0;
955 }
c6c2c85e 956#ifdef CONFIG_PINE64_DT_SELECTION
54ac5aa1
SH		 957 if (strstr(best_dt_name, "-pine64-plus")) {
958 /* Differentiate the Pine A64 boards by their DRAM size. */
959 if ((gd->ram_size == 512 * 1024 * 1024))
960 best_dt_name = "sun50i-a64-pine64";
9ea3c35a 961 }
c6c2c85e 962#endif
8a8b73b6
SH		 963#ifdef CONFIG_PINEPHONE_DT_SELECTION
964 if (strstr(best_dt_name, "-pinephone")) {
965 /* Differentiate the PinePhone revisions by GPIO inputs. */
966 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
967 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
968 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
969 udelay(100);
970
971 /* PL6 is pulled low by the modem on v1.2. */
972 if (gpio_get_value(SUNXI_GPL(6)) == 0)
973 best_dt_name = "sun50i-a64-pinephone-1.2";
974 else
975 best_dt_name = "sun50i-a64-pinephone-1.1";
976
977 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
978 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
979 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
980 }
981#endif
982
41530cf6
SH		 983 ret = strcmp(name, best_dt_name);
984
985 /*
986 * If one of the FIT configurations matches the most accurate DT name,
987 * update the SPL header to provide that DT name to U-Boot proper.
988 */
989 if (ret == 0)
990 set_spl_dt_name(best_dt_name);
991
992 return ret;
9ea3c35a 993}
64531496 994#endif /* CONFIG_SPL_LOAD_FIT */
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