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Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mips
[J-u-boot.git] / board / sunxi / board.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
cba69eee
IC		 2/*
3 * (C) Copyright 2012-2013 Henrik Nordstrom <[email protected]>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <[email protected]>
5 *
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <[email protected]>
9 *
10 * Some board init for the Allwinner A10-evb board.
cba69eee
IC		 11 */
12
13#include <common.h>
237050fc 14#include <dm.h>
e79c7c88 15#include <mmc.h>
6944aff1 16#include <axp_pmic.h>
237050fc
JT		 17#include <generic-phy.h>
18#include <phy-sun4i-usb.h>
cba69eee 19#include <asm/arch/clock.h>
b41d7d05 20#include <asm/arch/cpu.h>
2d7a084b 21#include <asm/arch/display.h>
cba69eee 22#include <asm/arch/dram.h>
e24ea55c
IC		 23#include <asm/arch/gpio.h>
24#include <asm/arch/mmc.h>
4a8c7c1f 25#include <asm/arch/spl.h>
d96ebc46
SS		 26#ifndef CONFIG_ARM64
27#include <asm/armv7.h>
28#endif
4f7e01c9 29#include <asm/gpio.h>
b41d7d05 30#include <asm/io.h>
a740ee91 31#include <u-boot/crc.h>
4a8c7c1f 32#include <environment.h>
b08c8c48 33#include <linux/libfdt.h>
f62bfa56 34#include <nand.h>
b41d7d05 35#include <net.h>
f4c3523c 36#include <spl.h>
0d8382ae 37#include <sy8106a.h>
5d982856 38#include <asm/setup.h>
cba69eee 39
55410089
HG		 40#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
41/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
42int soft_i2c_gpio_sda;
43int soft_i2c_gpio_scl;
4f7e01c9
HG		 44
45static int soft_i2c_board_init(void)
46{
47 int ret;
48
49 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
50 if (soft_i2c_gpio_sda < 0) {
51 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
52 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
53 return soft_i2c_gpio_sda;
54 }
55 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
56 if (ret) {
57 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
58 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
59 return ret;
60 }
61
62 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
63 if (soft_i2c_gpio_scl < 0) {
64 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
65 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
66 return soft_i2c_gpio_scl;
67 }
68 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
69 if (ret) {
70 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
71 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
72 return ret;
73 }
74
75 return 0;
76}
77#else
78static int soft_i2c_board_init(void) { return 0; }
55410089
HG		 79#endif
80
cba69eee
IC		 81DECLARE_GLOBAL_DATA_PTR;
82
acbc7e0a
JS		 83void i2c_init_board(void)
84{
85#ifdef CONFIG_I2C0_ENABLE
86#if defined(CONFIG_MACH_SUN4I) || \
87 defined(CONFIG_MACH_SUN5I) || \
88 defined(CONFIG_MACH_SUN7I) || \
89 defined(CONFIG_MACH_SUN8I_R40)
90 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
92 clock_twi_onoff(0, 1);
93#elif defined(CONFIG_MACH_SUN6I)
94 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
96 clock_twi_onoff(0, 1);
97#elif defined(CONFIG_MACH_SUN8I)
98 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
100 clock_twi_onoff(0, 1);
101#endif
102#endif
103
104#ifdef CONFIG_I2C1_ENABLE
105#if defined(CONFIG_MACH_SUN4I) || \
106 defined(CONFIG_MACH_SUN7I) || \
107 defined(CONFIG_MACH_SUN8I_R40)
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
110 clock_twi_onoff(1, 1);
111#elif defined(CONFIG_MACH_SUN5I)
112 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
114 clock_twi_onoff(1, 1);
115#elif defined(CONFIG_MACH_SUN6I)
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
118 clock_twi_onoff(1, 1);
119#elif defined(CONFIG_MACH_SUN8I)
120 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
121 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
122 clock_twi_onoff(1, 1);
123#endif
124#endif
125
126#ifdef CONFIG_I2C2_ENABLE
127#if defined(CONFIG_MACH_SUN4I) || \
128 defined(CONFIG_MACH_SUN7I) || \
129 defined(CONFIG_MACH_SUN8I_R40)
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
131 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
132 clock_twi_onoff(2, 1);
133#elif defined(CONFIG_MACH_SUN5I)
134 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
135 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
136 clock_twi_onoff(2, 1);
137#elif defined(CONFIG_MACH_SUN6I)
138 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
139 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
140 clock_twi_onoff(2, 1);
141#elif defined(CONFIG_MACH_SUN8I)
142 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
143 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
144 clock_twi_onoff(2, 1);
145#endif
146#endif
147
148#ifdef CONFIG_I2C3_ENABLE
149#if defined(CONFIG_MACH_SUN6I)
150 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
151 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
152 clock_twi_onoff(3, 1);
153#elif defined(CONFIG_MACH_SUN7I) || \
154 defined(CONFIG_MACH_SUN8I_R40)
155 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
156 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
157 clock_twi_onoff(3, 1);
158#endif
159#endif
160
161#ifdef CONFIG_I2C4_ENABLE
162#if defined(CONFIG_MACH_SUN7I) || \
163 defined(CONFIG_MACH_SUN8I_R40)
164 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
165 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
166 clock_twi_onoff(4, 1);
167#endif
168#endif
169
170#ifdef CONFIG_R_I2C_ENABLE
31a4ac4d
VK		 171#ifdef CONFIG_MACH_SUN50I
172 clock_twi_onoff(5, 1);
173 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
174 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
175#else
acbc7e0a
JS		 176 clock_twi_onoff(5, 1);
177 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
178 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
179#endif
31a4ac4d 180#endif
acbc7e0a
JS		 181}
182
b39117ca
MR		 183#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
184enum env_location env_get_location(enum env_operation op, int prio)
185{
186 switch (prio) {
187 case 0:
188 return ENVL_FAT;
189
190 case 1:
191 return ENVL_MMC;
192
193 default:
194 return ENVL_UNKNOWN;
195 }
196}
197#endif
198
cba69eee
IC		 199/* add board specific code here */
200int board_init(void)
201{
f5fd7886 202 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
cba69eee
IC		 203
204 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
205
d96ebc46 206#ifndef CONFIG_ARM64
cba69eee
IC		 207 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
208 debug("id_pfr1: 0x%08x\n", id_pfr1);
209 /* Generic Timer Extension available? */
d96ebc46
SS		 210 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
211 uint32_t freq;
212
cba69eee 213 debug("Setting CNTFRQ\n");
d96ebc46
SS		 214
215 /*
216 * CNTFRQ is a secure register, so we will crash if we try to
217 * write this from the non-secure world (read is OK, though).
218 * In case some bootcode has already set the correct value,
219 * we avoid the risk of writing to it.
220 */
221 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
e4916e85 222 if (freq != COUNTER_FREQUENCY) {
d96ebc46 223 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
e4916e85 224 freq, COUNTER_FREQUENCY);
d96ebc46
SS		 225#ifdef CONFIG_NON_SECURE
226 printf("arch timer frequency is wrong, but cannot adjust it\n");
227#else
228 asm volatile("mcr p15, 0, %0, c14, c0, 0"
e4916e85 229 : : "r"(COUNTER_FREQUENCY));
d96ebc46
SS		 230#endif
231 }
cba69eee 232 }
d96ebc46 233#endif /* !CONFIG_ARM64 */
cba69eee 234
2fcf033d
HG		 235 ret = axp_gpio_init();
236 if (ret)
237 return ret;
238
9fbb0c3a 239#ifdef CONFIG_SATAPWR
d7b560e6
MJ		 240 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
241 gpio_request(satapwr_pin, "satapwr");
242 gpio_direction_output(satapwr_pin, 1);
8e2c2d41
WB		 243 /* Give attached sata device time to power-up to avoid link timeouts */
244 mdelay(500);
9fbb0c3a 245#endif
fc8991c6 246#ifdef CONFIG_MACPWR
f5fd7886
MJ		 247 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
248 gpio_request(macpwr_pin, "macpwr");
249 gpio_direction_output(macpwr_pin, 1);
fc8991c6
HG		 250#endif
251
a8f01ccf
JS		 252#ifdef CONFIG_DM_I2C
253 /*
254 * Temporary workaround for enabling I2C clocks until proper sunxi DM
255 * clk, reset and pinctrl drivers land.
256 */
257 i2c_init_board();
258#endif
259
4f7e01c9
HG		 260 /* Uses dm gpio code so do this here and not in i2c_init_board() */
261 return soft_i2c_board_init();
cba69eee
IC		 262}
263
cff5c138
AP		 264/*
265 * On older SoCs the SPL is actually at address zero, so using NULL as
266 * an error value does not work.
267 */
268#define INVALID_SPL_HEADER ((void *)~0UL)
269
270static struct boot_file_head * get_spl_header(uint8_t req_version)
271{
272 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
273 uint8_t spl_header_version = spl->spl_signature[3];
274
275 /* Is there really the SPL header (still) there? */
276 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
277 return INVALID_SPL_HEADER;
278
279 if (spl_header_version < req_version) {
280 printf("sunxi SPL version mismatch: expected %u, got %u\n",
281 req_version, spl_header_version);
282 return INVALID_SPL_HEADER;
283 }
284
285 return spl;
286}
287
cba69eee
IC		 288int dram_init(void)
289{
5776610e
AP		 290 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
291
292 if (spl == INVALID_SPL_HEADER)
293 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
294 PHYS_SDRAM_0_SIZE);
295 else
296 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
297
298 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
299 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
cba69eee
IC		 300
301 return 0;
302}
303
4ccae81c 304#if defined(CONFIG_NAND_SUNXI)
ad008299
KG		 305static void nand_pinmux_setup(void)
306{
307 unsigned int pin;
ad008299 308
022a99d8 309 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
ad008299
KG		 310 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
311
022a99d8
HG		 312#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
313 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
314 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
315#endif
316 /* sun4i / sun7i do have a PC23, but it is not used for nand,
317 * only sun7i has a PC24 */
318#ifdef CONFIG_MACH_SUN7I
ad008299 319 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
022a99d8 320#endif
ad008299
KG		 321}
322
323static void nand_clock_setup(void)
324{
325 struct sunxi_ccm_reg *const ccm =
326 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
31c21471 327
ad008299 328 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
ba1c98ba
MR		 329#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
330 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
331 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
31c21471 332#endif
ad008299
KG		 333 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
334}
f62bfa56
HG		 335
336void board_nand_init(void)
337{
338 nand_pinmux_setup();
339 nand_clock_setup();
4ccae81c
BB		 340#ifndef CONFIG_SPL_BUILD
341 sunxi_nand_init();
342#endif
f62bfa56 343}
ad008299
KG		 344#endif
345
4aa2ba3a 346#ifdef CONFIG_MMC
e24ea55c
IC		 347static void mmc_pinmux_setup(int sdc)
348{
349 unsigned int pin;
8deacca9 350 __maybe_unused int pins;
e24ea55c
IC		 351
352 switch (sdc) {
353 case 0:
8deacca9 354 /* SDC0: PF0-PF5 */
e24ea55c 355 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
487b3277 356 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
e24ea55c
IC		 357 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
358 sunxi_gpio_set_drv(pin, 2);
359 }
360 break;
361
362 case 1:
8deacca9
PK		 363 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
364
8094a4a2
CYT		 365#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
366 defined(CONFIG_MACH_SUN8I_R40)
8deacca9
PK		 367 if (pins == SUNXI_GPIO_H) {
368 /* SDC1: PH22-PH-27 */
369 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
370 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
371 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
372 sunxi_gpio_set_drv(pin, 2);
373 }
374 } else {
375 /* SDC1: PG0-PG5 */
376 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
377 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
378 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
379 sunxi_gpio_set_drv(pin, 2);
380 }
381 }
382#elif defined(CONFIG_MACH_SUN5I)
383 /* SDC1: PG3-PG8 */
bbff84b3 384 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
487b3277 385 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
e24ea55c
IC		 386 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
387 sunxi_gpio_set_drv(pin, 2);
388 }
8deacca9
PK		 389#elif defined(CONFIG_MACH_SUN6I)
390 /* SDC1: PG0-PG5 */
391 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
392 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
393 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
394 sunxi_gpio_set_drv(pin, 2);
395 }
396#elif defined(CONFIG_MACH_SUN8I)
397 if (pins == SUNXI_GPIO_D) {
398 /* SDC1: PD2-PD7 */
399 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
400 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
401 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
402 sunxi_gpio_set_drv(pin, 2);
403 }
404 } else {
405 /* SDC1: PG0-PG5 */
406 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
407 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
408 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
409 sunxi_gpio_set_drv(pin, 2);
410 }
411 }
412#endif
e24ea55c
IC		 413 break;
414
415 case 2:
8deacca9
PK		 416 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
417
418#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
419 /* SDC2: PC6-PC11 */
e24ea55c 420 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
487b3277 421 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
e24ea55c
IC		 422 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
423 sunxi_gpio_set_drv(pin, 2);
424 }
8deacca9
PK		 425#elif defined(CONFIG_MACH_SUN5I)
426 if (pins == SUNXI_GPIO_E) {
427 /* SDC2: PE4-PE9 */
428 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
429 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
430 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
431 sunxi_gpio_set_drv(pin, 2);
432 }
433 } else {
434 /* SDC2: PC6-PC15 */
435 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
436 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
437 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
438 sunxi_gpio_set_drv(pin, 2);
439 }
440 }
441#elif defined(CONFIG_MACH_SUN6I)
442 if (pins == SUNXI_GPIO_A) {
443 /* SDC2: PA9-PA14 */
444 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
445 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
446 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
447 sunxi_gpio_set_drv(pin, 2);
448 }
449 } else {
450 /* SDC2: PC6-PC15, PC24 */
451 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
452 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
453 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
454 sunxi_gpio_set_drv(pin, 2);
455 }
456
457 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
458 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
459 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
460 }
8094a4a2
CYT		 461#elif defined(CONFIG_MACH_SUN8I_R40)
462 /* SDC2: PC6-PC15, PC24 */
463 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
464 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
465 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
466 sunxi_gpio_set_drv(pin, 2);
467 }
468
469 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
470 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
471 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
d96ebc46 472#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
8deacca9
PK		 473 /* SDC2: PC5-PC6, PC8-PC16 */
474 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
475 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
476 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
477 sunxi_gpio_set_drv(pin, 2);
478 }
479
480 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
481 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
482 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
483 sunxi_gpio_set_drv(pin, 2);
42956f1b
IZ		 484 }
485#elif defined(CONFIG_MACH_SUN50I_H6)
486 /* SDC2: PC4-PC14 */
487 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
488 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
489 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
490 sunxi_gpio_set_drv(pin, 2);
8deacca9 491 }
3ebb4567
PT		 492#elif defined(CONFIG_MACH_SUN9I)
493 /* SDC2: PC6-PC16 */
494 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
495 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
496 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
497 sunxi_gpio_set_drv(pin, 2);
498 }
8deacca9 499#endif
e24ea55c
IC		 500 break;
501
502 case 3:
8deacca9
PK		 503 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
504
8094a4a2
CYT		 505#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
506 defined(CONFIG_MACH_SUN8I_R40)
8deacca9 507 /* SDC3: PI4-PI9 */
e24ea55c 508 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
8deacca9 509 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
e24ea55c
IC		 510 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
511 sunxi_gpio_set_drv(pin, 2);
512 }
8deacca9
PK		 513#elif defined(CONFIG_MACH_SUN6I)
514 if (pins == SUNXI_GPIO_A) {
515 /* SDC3: PA9-PA14 */
516 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
517 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
518 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
519 sunxi_gpio_set_drv(pin, 2);
520 }
521 } else {
522 /* SDC3: PC6-PC15, PC24 */
523 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
524 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
525 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
526 sunxi_gpio_set_drv(pin, 2);
527 }
528
529 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
530 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
531 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
532 }
533#endif
e24ea55c
IC		 534 break;
535
536 default:
537 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
538 break;
539 }
540}
541
542int board_mmc_init(bd_t *bis)
543{
e79c7c88 544 __maybe_unused struct mmc *mmc0, *mmc1;
e79c7c88 545
e24ea55c 546 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
e79c7c88
HG		 547 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
548 if (!mmc0)
549 return -1;
550
2ccfac01 551#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
e24ea55c 552 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
e79c7c88
HG		 553 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
554 if (!mmc1)
555 return -1;
556#endif
557
e24ea55c
IC		 558 return 0;
559}
560#endif
561
cba69eee 562#ifdef CONFIG_SPL_BUILD
5776610e
AP		 563
564static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
565{
566 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
567
568 if (spl == INVALID_SPL_HEADER)
569 return;
570
571 /* Promote the header version for U-Boot proper, if needed. */
572 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
573 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
574
575 spl->dram_size = dram_size >> 20;
576}
577
cba69eee
IC		 578void sunxi_board_init(void)
579{
14bc66bd 580 int power_failed = 0;
cba69eee 581
0d8382ae
JW		 582#ifdef CONFIG_SY8106A_POWER
583 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
584#endif
585
95ab8fee 586#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
795857df
CYT		 587 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
588 defined CONFIG_AXP818_POWER
6944aff1
HG		 589 power_failed = axp_init();
590
795857df
CYT		 591#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
592 defined CONFIG_AXP818_POWER
6944aff1 593 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
24289208 594#endif
6944aff1
HG		 595 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
596 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
95ab8fee 597#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
6944aff1 598 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
5c7f10fd 599#endif
795857df
CYT		 600#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
601 defined CONFIG_AXP818_POWER
6944aff1 602 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
14bc66bd
HN		 603#endif
604
795857df
CYT		 605#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
606 defined CONFIG_AXP818_POWER
6944aff1
HG		 607 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
608#endif
609 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
f3c5045a 610#if !defined(CONFIG_AXP152_POWER)
6944aff1
HG		 611 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
612#endif
613#ifdef CONFIG_AXP209_POWER
614 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
615#endif
616
795857df
CYT		 617#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
618 defined(CONFIG_AXP818_POWER)
3517a27d
CYT		 619 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
620 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
795857df 621#if !defined CONFIG_AXP809_POWER
3517a27d
CYT		 622 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
623 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
795857df 624#endif
6944aff1
HG		 625 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
626 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
627 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
628#endif
38491d9c
CYT		 629
630#ifdef CONFIG_AXP818_POWER
631 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
632 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
633 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
795857df
CYT		 634#endif
635
636#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
15278ccb 637 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
38491d9c 638#endif
6944aff1 639#endif
44c214dc
FKP		 640 printf("DRAM:");
641 gd->ram_size = sunxi_dram_init();
642 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
643 if (!gd->ram_size)
644 hang();
645
646 sunxi_spl_store_dram_size(gd->ram_size);
5776610e 647
14bc66bd
HN		 648 /*
649 * Only clock up the CPU to full speed if we are reasonably
650 * assured it's being powered with suitable core voltage
651 */
652 if (!power_failed)
e71b422b 653 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
14bc66bd 654 else
44c214dc 655 printf("Failed to set core voltage! Can't set CPU frequency\n");
cba69eee
IC		 656}
657#endif
b41d7d05 658
f1df758d
PK		 659#ifdef CONFIG_USB_GADGET
660int g_dnl_board_usb_cable_connected(void)
661{
237050fc
JT		 662 struct udevice *dev;
663 struct phy phy;
664 int ret;
665
01311624 666 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
237050fc
JT		 667 if (ret) {
668 pr_err("%s: Cannot find USB device\n", __func__);
669 return ret;
670 }
671
672 ret = generic_phy_get_by_name(dev, "usb", &phy);
673 if (ret) {
674 pr_err("failed to get %s USB PHY\n", dev->name);
675 return ret;
676 }
677
678 ret = generic_phy_init(&phy);
679 if (ret) {
680 pr_err("failed to init %s USB PHY\n", dev->name);
681 return ret;
682 }
683
684 ret = sun4i_usb_phy_vbus_detect(&phy);
685 if (ret == 1) {
686 pr_err("A charger is plugged into the OTG\n");
687 return -ENODEV;
688 }
689
690 return ret;
f1df758d
PK		 691}
692#endif
693
9f852211
PK		 694#ifdef CONFIG_SERIAL_TAG
695void get_board_serial(struct tag_serialnr *serialnr)
696{
697 char *serial_string;
698 unsigned long long serial;
699
00caae6d 700 serial_string = env_get("serial#");
9f852211
PK		 701
702 if (serial_string) {
703 serial = simple_strtoull(serial_string, NULL, 16);
704
705 serialnr->high = (unsigned int) (serial >> 32);
706 serialnr->low = (unsigned int) (serial & 0xffffffff);
707 } else {
708 serialnr->high = 0;
709 serialnr->low = 0;
710 }
711}
712#endif
713
af654d14
BN		 714/*
715 * Check the SPL header for the "sunxi" variant. If found: parse values
716 * that might have been passed by the loader ("fel" utility), and update
717 * the environment accordingly.
718 */
719static void parse_spl_header(const uint32_t spl_addr)
720{
cff5c138 721 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
320e0570 722
cff5c138 723 if (spl == INVALID_SPL_HEADER)
320e0570 724 return;
cff5c138 725
320e0570
BN		 726 if (!spl->fel_script_address)
727 return;
728
729 if (spl->fel_uEnv_length != 0) {
730 /*
731 * data is expected in uEnv.txt compatible format, so "env
732 * import -t" the string(s) at fel_script_address right away.
733 */
5a74a391 734 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
320e0570
BN		 735 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
736 return;
af654d14 737 }
320e0570 738 /* otherwise assume .scr format (mkimage-type script) */
018f5303 739 env_set_hex("fel_scriptaddr", spl->fel_script_address);
af654d14 740}
af654d14 741
f221961e
HG		 742/*
743 * Note this function gets called multiple times.
744 * It must not make any changes to env variables which already exist.
745 */
746static void setup_environment(const void *fdt)
b41d7d05 747{
8c816573 748 char serial_string[17] = { 0 };
cac5b1cc 749 unsigned int sid[4];
8c816573 750 uint8_t mac_addr[6];
f221961e
HG		 751 char ethaddr[16];
752 int i, ret;
af654d14 753
8c816573 754 ret = sunxi_get_sid(sid);
3f8ea3b0
HG		 755 if (ret == 0 && sid[0] != 0) {
756 /*
757 * The single words 1 - 3 of the SID have quite a few bits
758 * which are the same on many models, so we take a crc32
759 * of all 3 words, to get a more unique value.
760 *
761 * Note we only do this on newer SoCs as we cannot change
762 * the algorithm on older SoCs since those have been using
763 * fixed mac-addresses based on only using word 3 for a
764 * long time and changing a fixed mac-address with an
765 * u-boot update is not good.
766 */
767#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
768 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
769 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
770 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
771#endif
772
97322c3e
HG		 773 /* Ensure the NIC specific bytes of the mac are not all 0 */
774 if ((sid[3] & 0xffffff) == 0)
775 sid[3] |= 0x800000;
776
f221961e
HG		 777 for (i = 0; i < 4; i++) {
778 sprintf(ethaddr, "ethernet%d", i);
779 if (!fdt_get_alias(fdt, ethaddr))
780 continue;
781
782 if (i == 0)
783 strcpy(ethaddr, "ethaddr");
784 else
785 sprintf(ethaddr, "eth%daddr", i);
786
00caae6d 787 if (env_get(ethaddr))
f221961e
HG		 788 continue;
789
8c816573 790 /* Non OUI / registered MAC address */
f221961e 791 mac_addr[0] = (i << 4) | 0x02;
8c816573
PK		 792 mac_addr[1] = (sid[0] >> 0) & 0xff;
793 mac_addr[2] = (sid[3] >> 24) & 0xff;
794 mac_addr[3] = (sid[3] >> 16) & 0xff;
795 mac_addr[4] = (sid[3] >> 8) & 0xff;
796 mac_addr[5] = (sid[3] >> 0) & 0xff;
797
fd1e959e 798 eth_env_set_enetaddr(ethaddr, mac_addr);
8c816573 799 }
b41d7d05 800
00caae6d 801 if (!env_get("serial#")) {
8c816573
PK		 802 snprintf(serial_string, sizeof(serial_string),
803 "%08x%08x", sid[0], sid[3]);
b41d7d05 804
382bee57 805 env_set("serial#", serial_string);
8c816573 806 }
b41d7d05 807 }
f221961e
HG		 808}
809
f221961e
HG		 810int misc_init_r(void)
811{
f4c3523c 812 uint boot;
f221961e 813
382bee57
SG		 814 env_set("fel_booted", NULL);
815 env_set("fel_scriptaddr", NULL);
de86fc38 816 env_set("mmc_bootdev", NULL);
f4c3523c
MR		 817
818 boot = sunxi_get_boot_device();
f221961e 819 /* determine if we are running in FEL mode */
f4c3523c 820 if (boot == BOOT_DEVICE_BOARD) {
382bee57 821 env_set("fel_booted", "1");
f221961e 822 parse_spl_header(SPL_ADDR);
de86fc38
MR		 823 /* or if we booted from MMC, and which one */
824 } else if (boot == BOOT_DEVICE_MMC1) {
825 env_set("mmc_bootdev", "0");
826 } else if (boot == BOOT_DEVICE_MMC2) {
827 env_set("mmc_bootdev", "1");
f221961e 828 }
f221961e
HG		 829
830 setup_environment(gd->fdt_blob);
b41d7d05 831
e6ee85a6 832#ifdef CONFIG_USB_ETHER
90dd2f19 833 usb_ether_init();
e6ee85a6 834#endif
90dd2f19 835
b41d7d05
JL		 836 return 0;
837}
2d7a084b 838
2d7a084b
LV		 839int ft_board_setup(void *blob, bd_t *bd)
840{
d75111a7
HG		 841 int __maybe_unused r;
842
f221961e
HG		 843 /*
844 * Call setup_environment again in case the boot fdt has
845 * ethernet aliases the u-boot copy does not have.
846 */
847 setup_environment(blob);
848
2d7a084b 849#ifdef CONFIG_VIDEO_DT_SIMPLEFB
d75111a7
HG		 850 r = sunxi_simplefb_setup(blob);
851 if (r)
852 return r;
2d7a084b 853#endif
d75111a7 854 return 0;
2d7a084b 855}
9ea3c35a
AP		 856
857#ifdef CONFIG_SPL_LOAD_FIT
858int board_fit_config_name_match(const char *name)
859{
cff5c138
AP		 860 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
861 const char *cmp_str = (const char *)spl;
9ea3c35a 862
54254ba7 863 /* Check if there is a DT name stored in the SPL header and use that. */
cff5c138 864 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
54254ba7
AP		 865 cmp_str += spl->dt_name_offset;
866 } else {
9ea3c35a 867#ifdef CONFIG_DEFAULT_DEVICE_TREE
54254ba7 868 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
9ea3c35a 869#else
54254ba7 870 return 0;
9ea3c35a 871#endif
54254ba7 872 };
9ea3c35a 873
c6c2c85e 874#ifdef CONFIG_PINE64_DT_SELECTION
9ea3c35a
AP		 875/* Differentiate the two Pine64 board DTs by their DRAM size. */
876 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
877 if ((gd->ram_size > 512 * 1024 * 1024))
878 return !strstr(name, "plus");
879 else
880 return !!strstr(name, "plus");
881 } else {
882 return strcmp(name, cmp_str);
883 }
c6c2c85e
IZ		 884#endif
885 return strcmp(name, cmp_str);
9ea3c35a
AP		 886}
887#endif
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