[J-u-boot.git] / board / freescale / ls1046ardb / ddr.c

/*
 * Copyright 2016 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include "ddr.h"
#ifdef CONFIG_FSL_DEEP_SLEEP
#include <fsl_sleep.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

void fsl_ddr_board_options(memctl_options_t *popts,
			   dimm_params_t *pdimm,
			   unsigned int ctrl_num)
{
	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
	ulong ddr_freq;

	if (ctrl_num > 1) {
		printf("Not supported controller number %d\n", ctrl_num);
		return;
	}
	if (!pdimm->n_ranks)
		return;

	pbsp = udimms[0];

	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
	 * freqency and n_banks specified in board_specific_parameters table.
	 */
	ddr_freq = get_ddr_freq(0) / 1000000;
	while (pbsp->datarate_mhz_high) {
		if (pbsp->n_ranks == pdimm->n_ranks) {
			if (ddr_freq <= pbsp->datarate_mhz_high) {
				popts->clk_adjust = pbsp->clk_adjust;
				popts->wrlvl_start = pbsp->wrlvl_start;
				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
				goto found;
			}
			pbsp_highest = pbsp;
		}
		pbsp++;
	}

	if (pbsp_highest) {
		printf("Error: board specific timing not found for %lu MT/s\n",
		       ddr_freq);
		printf("Trying to use the highest speed (%u) parameters\n",
		       pbsp_highest->datarate_mhz_high);
		popts->clk_adjust = pbsp_highest->clk_adjust;
		popts->wrlvl_start = pbsp_highest->wrlvl_start;
		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
	} else {
		panic("DIMM is not supported by this board");
	}
found:
	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);

	popts->data_bus_width = 0;	/* 64-bit data bus */
	popts->otf_burst_chop_en = 0;
	popts->burst_length = DDR_BL8;
	popts->bstopre = 0;		/* enable auto precharge */

	/*
	 * Factors to consider for half-strength driver enable:
	 *	- number of DIMMs installed
	 */
	popts->half_strength_driver_enable = 0;
	/*
	 * Write leveling override
	 */
	popts->wrlvl_override = 1;
	popts->wrlvl_sample = 0xf;

	/*
	 * Rtt and Rtt_WR override
	 */
	popts->rtt_override = 0;

	/* Enable ZQ calibration */
	popts->zq_en = 1;

	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
			  DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
}

phys_size_t initdram(int board_type)
{
	phys_size_t dram_size;

#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
	return fsl_ddr_sdram_size();
#else
	puts("Initializing DDR....using SPD\n");

	dram_size = fsl_ddr_sdram();
#endif

	erratum_a008850_post();

	return dram_size;
}

void dram_init_banksize(void)
{
	/*
	 * gd->arch.secure_ram tracks the location of secure memory.
	 * It was set as if the memory starts from 0.
	 * The address needs to add the offset of its bank.
	 */
	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
		gd->bd->bi_dram[1].size = gd->ram_size -
					  CONFIG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
				 gd->arch.secure_ram -
				 CONFIG_SYS_DDR_BLOCK1_SIZE;
		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif
	} else {
		gd->bd->bi_dram[0].size = gd->ram_size;
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
				 gd->arch.secure_ram;
		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
#endif
	}
}
Commit	Line	Data
dd02936f MH	1	/*
	2	* Copyright 2016 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <fsl_ddr_sdram.h>
	9	#include <fsl_ddr_dimm_params.h>
	10	#include "ddr.h"
	11	#ifdef CONFIG_FSL_DEEP_SLEEP
	12	#include <fsl_sleep.h>
	13	#endif
	14
	15	DECLARE_GLOBAL_DATA_PTR;
	16
	17	void fsl_ddr_board_options(memctl_options_t *popts,
	18	dimm_params_t *pdimm,
	19	unsigned int ctrl_num)
	20	{
	21	const struct board_specific_parameters pbsp, pbsp_highest = NULL;
	22	ulong ddr_freq;
	23
	24	if (ctrl_num > 1) {
	25	printf("Not supported controller number %d\n", ctrl_num);
	26	return;
	27	}
	28	if (!pdimm->n_ranks)
	29	return;
	30
	31	pbsp = udimms[0];
	32
	33	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
	34	* freqency and n_banks specified in board_specific_parameters table.
	35	*/
	36	ddr_freq = get_ddr_freq(0) / 1000000;
	37	while (pbsp->datarate_mhz_high) {
	38	if (pbsp->n_ranks == pdimm->n_ranks) {
	39	if (ddr_freq <= pbsp->datarate_mhz_high) {
	40	popts->clk_adjust = pbsp->clk_adjust;
	41	popts->wrlvl_start = pbsp->wrlvl_start;
	42	popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
	43	popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
	44	goto found;
	45	}
	46	pbsp_highest = pbsp;
	47	}
	48	pbsp++;
	49	}
	50
	51	if (pbsp_highest) {
	52	printf("Error: board specific timing not found for %lu MT/s\n",
	53	ddr_freq);
	54	printf("Trying to use the highest speed (%u) parameters\n",
	55	pbsp_highest->datarate_mhz_high);
	56	popts->clk_adjust = pbsp_highest->clk_adjust;
	57	popts->wrlvl_start = pbsp_highest->wrlvl_start;
	58	popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
	59	popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
	60	} else {
	61	panic("DIMM is not supported by this board");
	62	}
	63	found:
	64	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
65	pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
66
67	popts->data_bus_width = 0; /* 64-bit data bus */
68	popts->otf_burst_chop_en = 0;
69	popts->burst_length = DDR_BL8;
70	popts->bstopre = 0; /* enable auto precharge */
71
72	/*
73	* Factors to consider for half-strength driver enable:
74	* - number of DIMMs installed
75	*/
76	popts->half_strength_driver_enable = 0;
77	/*
78	* Write leveling override
79	*/
80	popts->wrlvl_override = 1;
81	popts->wrlvl_sample = 0xf;
82
83	/*
84	* Rtt and Rtt_WR override
85	*/
86	popts->rtt_override = 0;
87
88	/* Enable ZQ calibration */
89	popts->zq_en = 1;
90
91	popts->ddr_cdr1 = DDR_CDR1_DHC_EN \| DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
92	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) \|
93	DDR_CDR2_VREF_TRAIN_EN \| DDR_CDR2_VREF_RANGE_2;
94	}
95
96	phys_size_t initdram(int board_type)
97	{
98	phys_size_t dram_size;
99
100	#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
101	return fsl_ddr_sdram_size();
102	#else
103	puts("Initializing DDR....using SPD\n");
104
105	dram_size = fsl_ddr_sdram();
106	#endif
107
108	erratum_a008850_post();
109
110	return dram_size;
111	}
112
113	void dram_init_banksize(void)
114	{
115	/*
116	* gd->arch.secure_ram tracks the location of secure memory.
117	* It was set as if the memory starts from 0.
118	* The address needs to add the offset of its bank.
119	*/
120	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
121	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
122	gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
123	gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
124	gd->bd->bi_dram[1].size = gd->ram_size -
125	CONFIG_SYS_DDR_BLOCK1_SIZE;
126	#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
127	gd->arch.secure_ram = gd->bd->bi_dram[1].start +
128	gd->arch.secure_ram -
129	CONFIG_SYS_DDR_BLOCK1_SIZE;
130	gd->arch.secure_ram \|= MEM_RESERVE_SECURE_MAINTAINED;
131	#endif
132	} else {
133	gd->bd->bi_dram[0].size = gd->ram_size;
134	#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
135	gd->arch.secure_ram = gd->bd->bi_dram[0].start +
136	gd->arch.secure_ram;
137	gd->arch.secure_ram \|= MEM_RESERVE_SECURE_MAINTAINED;
138	#endif
139	}
140	}