[J-u-boot.git] / arch / arm / dts / zynqmp-vp-x-a2785-00-revA.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller
 *
 * (C) Copyright 2021 - 2022, Xilinx, Inc.
 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
 *
 * Michal Simek <[email protected]>
 */
/dts-v1/;

#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>

/ {
	model = "ZynqMP System Controller on vp-x-a2785-00 board RevA";
	compatible = "xlnx,zynqmp-vp-x-a2785-00-revA",
		     "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp";

	aliases {
		ethernet0 = &gem0;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		mmc0 = &sdhci0;
		serial0 = &uart0;
		serial1 = &dcc;
		spi0 = &qspi;
		usb0 = &usb0;
		usb1 = &usb1;
		nvmem0 = &eeprom;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0 0 0 0x80000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		key-j383 {
			label = "j383";
			gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
			linux,code = <BTN_MISC>;
			wakeup-source;
			autorepeat;
		};
	};

	leds {
		compatible = "gpio-leds";
		heartbeat-led { /* ds52 */
			label = "heartbeat";
			gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	si5332_0: si5332-0 { /* ps_ref_clk - u142 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <33333333>;
	};

	si5332_1: si5332-1 { /* clk0_sgmii - u142 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <33333333>; /* FIXME */
	};

	si5332_2: si5332-2 { /* clk1_usb - u142 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
	};
};

&qspi { /* MIO 0-5 */
	status = "okay";
	flash@0 {
		compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		spi-tx-bus-width = <4>; /* maybe 4 here */
		spi-rx-bus-width = <4>;
		spi-max-frequency = <108000000>;
		partition@0 { /* for testing purpose */
			label = "qspi";
			reg = <0 0x4000000>;
		};
	};
};

&sdhci1 { /* sd MIO 45-51 */
	status = "okay";
	no-1-8-v;
	disable-wp;
	xlnx,mio-bank = <1>;
};

&uart0 { /* uart0 MIO38-39 */
	status = "okay";
	bootph-all;
};

&gem0 {
	status = "okay";
	phy-handle = <&phy0>;
	phy-mode = "sgmii"; /* DTG generates this properly 1512 */
	/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
	mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		/* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
		phy0: ethernet-phy@0 { /* u131 - M88e1512 */
			reg = <0>;
		};
	};
};

&gpio {
	status = "okay";
	gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
		  "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
		  "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */
		  "", "", "", "", "", /* 15 - 19 */
		  "", "", "", "", "", /* 20 - 24 */
		  "", "", "", "", "", /* 25 - 29 */
		  "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
		  "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
		  "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
		  "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
		  "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
		  "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
		  "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
		  "", "", "", "", "", /* 65 - 69 */
		  "", "", "", "", "", /* 70 - 74 */
		  "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
		  "", "", /* 78 - 79 */
		  "", "", "", "", "", /* 80 - 84 */
		  "", "", "", "", "", /* 85 - 89 */
		  "", "", "", "", "", /* 90 - 94 */
		  "", "", "", "", "", /* 95 - 99 */
		  "", "", "", "", "", /* 100 - 104 */
		  "", "", "", "", "", /* 105 - 109 */
		  "", "", "", "", "", /* 110 - 114 */
		  "", "", "", "", "", /* 115 - 119 */
		  "", "", "", "", "", /* 120 - 124 */
		  "", "", "", "", "", /* 125 - 129 */
		  "", "", "", "", "", /* 130 - 134 */
		  "", "", "", "", "", /* 135 - 139 */
		  "", "", "", "", "", /* 140 - 144 */
		  "", "", "", "", "", /* 145 - 149 */
		  "", "", "", "", "", /* 150 - 154 */
		  "", "", "", "", "", /* 155 - 159 */
		  "", "", "", "", "", /* 160 - 164 */
		  "", "", "", "", "", /* 165 - 169 */
		  "", "", "", ""; /* 170 - 173 */
};

&i2c0 { /* MIO 34-35 - can't stay here */
	status = "okay";
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c0_default>;
	pinctrl-1 = <&pinctrl_i2c0_gpio>;
	scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller; /* interrupt not connected */
		#gpio-cells = <2>;
		gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */
				  "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
				  "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */
				  "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
	};

	i2c-mux@74 { /* u33 */
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x74>;
		/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
		pmbus_i2c: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			/* On connector J325 */
			reg_vccint: tps53681@60 { /* u266 - 0xc0 */
				compatible = "ti,tps53681", "ti,tps53679";
				reg = <0x60>;
			};
			reg_vcc1v1_lp4: tps544@d { /* u85 */
				compatible = "ti,tps544b25";
				reg = <0xd>;
			};
			reg_mgtyavcc: tps544@10 { /* u274 */
				compatible = "ti,tps544b25";
				reg = <0x10>;
			};
			reg_mgtyavtt: tps544@11 { /* u275 */
				compatible = "ti,tps544b25";
				reg = <0x11>;
			};
			reg_vccaux: tps544@12 { /* u276 */
				compatible = "ti,tps544b25";
				reg = <0x12>;
			};
			reg_vcc_cpm: tps544@14 { /* u272 */
				compatible = "ti,tps544b25";
				reg = <0x14>;
			};
			reg_util_3v3: tps544@1d { /* u278 */
				compatible = "ti,tps544b25";
				reg = <0x1d>;
			};
		};
		pmbus1_ina226_i2c: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			/* FIXME check alerts coming to SC */
			vcc_cpm: ina226@44 { /* u273 */
				compatible = "ti,ina226";
				reg = <0x44>;
				shunt-resistor = <1000>;
			};
		};
		i2c@2 { /* NC */ /* FIXME maybe remove */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};
		pcie_smbus: i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};
		pcie2_smbus: i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
		};
		i2c@5 { /* NC */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
		};
		user_si570: i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
		};
		/* 7 unused */
	};
};

&i2c1 { /* i2c1 MIO 36-37 */
	status = "okay";
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1_default>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	i2c-mux@74 { /* u35 */
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x74>;
		/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
		dc_i2c: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			/* Use for storing information about SC board */
			eeprom: eeprom@54 { /* u34 - m24128 16kB */
				compatible = "st,24c128", "atmel,24c128";
				reg = <0x54>; /* & 0x5c */
			};
			si570_ref_clk: clock-generator@5d { /* u32 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x5d>;
				temperature-stability = <50>;
				factory-fout = <33333333>;
				clock-frequency = <33333333>;
				clock-output-names = "ref_clk";
				silabs,skip-recall;
			};
		};
		i2c@1 { /* NC - FIXME */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
		i2c@2 { /* NC - FIXME */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};
		i2c@3 { /* NC - FIXME */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};
		lpddr4_si570_clk2_i2c: i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
			lpddr4_clk2: clock-generator@60 { /* u3 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x60>;
				temperature-stability = <50>;
				factory-fout = <200000000>;
				clock-frequency = <200000000>;
				clock-output-names = "lpddr4_clk2";
			};
		};
		lpddr4_si570_clk1_i2c: i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
			lpddr4_clk1: clock-generator@60 { /* u248 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x60>;
				temperature-stability = <50>;
				factory-fout = <200000000>;
				clock-frequency = <200000000>;
				clock-output-names = "lpddr4_clk1";
			};
		};
		/* 6-7 unused */
	};
};

&usb0 { /* MIO52 - MIO63 */
	status = "okay";
	phy-names = "usb3-phy";
	phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
};

&psgtr {
	status = "okay";
	/* sgmii, usb3 */
	clocks = <&si5332_1>, <&si5332_2>;
	clock-names = "ref0", "ref1";
};

&dwc3_0 {
	status = "okay";
	dr_mode = "peripheral";
	snps,dis_u2_susphy_quirk;
	snps,dis_u3_susphy_quirk;
	maximum-speed = "super-speed";
};

&xilinx_ams {
	status = "okay";
};

&ams_ps {
	status = "okay";
};

&ams_pl {
	status = "okay";
};

&pinctrl0 {
	status = "okay";
	pinctrl_i2c0_default: i2c0-default {
		mux {
			groups = "i2c0_8_grp";
			function = "i2c0";
		};

		conf {
			groups = "i2c0_8_grp";
			bias-pull-up;
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};
	};

	pinctrl_i2c0_gpio: i2c0-gpio-grp {
		mux {
			groups = "gpio0_34_grp", "gpio0_35_grp";
			function = "gpio0";
		};

		conf {
			groups = "gpio0_34_grp", "gpio0_35_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};
	};

	pinctrl_i2c1_default: i2c1-default {
		mux {
			groups = "i2c1_9_grp";
			function = "i2c1";
		};

		conf {
			groups = "i2c1_9_grp";
			bias-pull-up;
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};
	};

	pinctrl_i2c1_gpio: i2c1-gpio-grp {
		mux {
			groups = "gpio0_36_grp", "gpio0_37_grp";
			function = "gpio0";
		};

		conf {
			groups = "gpio0_36_grp", "gpio0_37_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};
	};
};
Commit	Line	Data
eb357b75 MS	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller
	4	*
	5	* (C) Copyright 2021 - 2022, Xilinx, Inc.
	6	* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
	7	*
	8	* Michal Simek <[email protected]>
	9	*/
	10	/dts-v1/;
	11
	12	#include "zynqmp.dtsi"
	13	#include "zynqmp-clk-ccf.dtsi"
	14	#include <dt-bindings/input/input.h>
	15	#include <dt-bindings/gpio/gpio.h>
	16	#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
	17	#include <dt-bindings/phy/phy.h>
	18
	19	/ {
	20	model = "ZynqMP System Controller on vp-x-a2785-00 board RevA";
	21	compatible = "xlnx,zynqmp-vp-x-a2785-00-revA",
	22	"xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp";
	23
	24	aliases {
	25	ethernet0 = &gem0;
	26	i2c0 = &i2c0;
	27	i2c1 = &i2c1;
	28	mmc0 = &sdhci0;
	29	serial0 = &uart0;
	30	serial1 = &dcc;
	31	spi0 = &qspi;
	32	usb0 = &usb0;
	33	usb1 = &usb1;
	34	nvmem0 = &eeprom;
	35	};
	36
	37	chosen {
	38	bootargs = "earlycon";
	39	stdout-path = "serial0:115200n8";
	40	};
	41
	42	memory@0 {
	43	device_type = "memory";
	44	reg = <0 0 0 0x80000000>;
	45	};
	46
	47	gpio-keys {
	48	compatible = "gpio-keys";
	49	autorepeat;
0f25a5a5	50	key-j383 {
eb357b75 MS	51	label = "j383";
	52	gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
	53	linux,code = <BTN_MISC>;
	54	wakeup-source;
	55	autorepeat;
	56	};
	57	};
	58
	59	leds {
	60	compatible = "gpio-leds";
	61	heartbeat-led { /* ds52 */
	62	label = "heartbeat";
	63	gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
	64	linux,default-trigger = "heartbeat";
	65	};
	66	};
	67
e5d9df95	68	si5332_0: si5332-0 { /* ps_ref_clk - u142 */
eb357b75 MS	69	compatible = "fixed-clock";
	70	#clock-cells = <0>;
	71	clock-frequency = <33333333>;
	72	};
	73
e5d9df95	74	si5332_1: si5332-1 { /* clk0_sgmii - u142 */
eb357b75 MS	75	compatible = "fixed-clock";
	76	#clock-cells = <0>;
	77	clock-frequency = <33333333>; /* FIXME */
	78	};
	79
e5d9df95	80	si5332_2: si5332-2 { /* clk1_usb - u142 */
eb357b75 MS	81	compatible = "fixed-clock";
	82	#clock-cells = <0>;
	83	clock-frequency = <27000000>;
	84	};
	85	};
	86
	87	&qspi { /* MIO 0-5 */
	88	status = "okay";
	89	flash@0 {
	90	compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */
	91	#address-cells = <1>;
	92	#size-cells = <1>;
	93	reg = <0>;
	94	spi-tx-bus-width = <4>; /* maybe 4 here */
	95	spi-rx-bus-width = <4>;
	96	spi-max-frequency = <108000000>;
	97	partition@0 { /* for testing purpose */
	98	label = "qspi";
	99	reg = <0 0x4000000>;
	100	};
	101	};
	102	};
	103
	104	&sdhci1 { /* sd MIO 45-51 */
	105	status = "okay";
	106	no-1-8-v;
	107	disable-wp;
	108	xlnx,mio-bank = <1>;
	109	};
	110
	111	&uart0 { /* uart0 MIO38-39 */
	112	status = "okay";
	113	bootph-all;
	114	};
	115
	116	&gem0 {
	117	status = "okay";
	118	phy-handle = <&phy0>;
	119	phy-mode = "sgmii"; /* DTG generates this properly 1512 */
eb357b75	120	/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
f87696af MS	121	mdio: mdio {
	122	#address-cells = <1>;
	123	#size-cells = <0>;
	124	/* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
	125	phy0: ethernet-phy@0 { /* u131 - M88e1512 */
	126	reg = <0>;
	127	};
eb357b75 MS	128	};
	129	};
	130
	131	&gpio {
	132	status = "okay";
	133	gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
	134	"QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
	135	"SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */
	136	"", "", "", "", "", /* 15 - 19 */
	137	"", "", "", "", "", /* 20 - 24 */
	138	"", "", "", "", "", /* 25 - 29 */
	139	"", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
	140	"LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
	141	"", "", "ETH_RESET_B", "", "", /* 40 - 44 */
	142	"SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
	143	"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
	144	"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
	145	"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
	146	"", "", "", "", "", /* 65 - 69 */
	147	"", "", "", "", "", /* 70 - 74 */
	148	"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
	149	"", "", /* 78 - 79 */
	150	"", "", "", "", "", /* 80 - 84 */
	151	"", "", "", "", "", /* 85 - 89 */
	152	"", "", "", "", "", /* 90 - 94 */
	153	"", "", "", "", "", /* 95 - 99 */
	154	"", "", "", "", "", /* 100 - 104 */
	155	"", "", "", "", "", /* 105 - 109 */
	156	"", "", "", "", "", /* 110 - 114 */
	157	"", "", "", "", "", /* 115 - 119 */
	158	"", "", "", "", "", /* 120 - 124 */
	159	"", "", "", "", "", /* 125 - 129 */
	160	"", "", "", "", "", /* 130 - 134 */
	161	"", "", "", "", "", /* 135 - 139 */
	162	"", "", "", "", "", /* 140 - 144 */
	163	"", "", "", "", "", /* 145 - 149 */
	164	"", "", "", "", "", /* 150 - 154 */
	165	"", "", "", "", "", /* 155 - 159 */
	166	"", "", "", "", "", /* 160 - 164 */
	167	"", "", "", "", "", /* 165 - 169 */
	168	"", "", "", ""; /* 170 - 173 */
	169	};
	170
	171	&i2c0 { /* MIO 34-35 - can't stay here */
	172	status = "okay";
	173	clock-frequency = <400000>;
	174	pinctrl-names = "default", "gpio";
	175	pinctrl-0 = <&pinctrl_i2c0_default>;
	176	pinctrl-1 = <&pinctrl_i2c0_gpio>;
	177	scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	178	sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
	179
	180	tca6416_u233: gpio@20 { /* u233 / / FIXME - address maybe wrong */
	181	compatible = "ti,tca6416";
	182	reg = <0x20>;
	183	gpio-controller; /* interrupt not connected */
	184	#gpio-cells = <2>;
	185	gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */
	186	"", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
	187	"", "", "", "VCCINT_FAULT_B", /* 10 - 13 */
	188	"VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
	189	};
	190
	191	i2c-mux@74 { /* u33 */
192	compatible = "nxp,pca9548";
193	#address-cells = <1>;
194	#size-cells = <0>;
195	reg = <0x74>;
196	/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
197	pmbus_i2c: i2c@0 {
198	#address-cells = <1>;
199	#size-cells = <0>;
200	reg = <0>;
201	/* On connector J325 */
202	reg_vccint: tps53681@60 { /* u266 - 0xc0 */
203	compatible = "ti,tps53681", "ti,tps53679";
204	reg = <0x60>;
205	};
206	reg_vcc1v1_lp4: tps544@d { /* u85 */
207	compatible = "ti,tps544b25";
208	reg = <0xd>;
209	};
210	reg_mgtyavcc: tps544@10 { /* u274 */
211	compatible = "ti,tps544b25";
212	reg = <0x10>;
213	};
214	reg_mgtyavtt: tps544@11 { /* u275 */
215	compatible = "ti,tps544b25";
216	reg = <0x11>;
217	};
218	reg_vccaux: tps544@12 { /* u276 */
219	compatible = "ti,tps544b25";
220	reg = <0x12>;
221	};
222	reg_vcc_cpm: tps544@14 { /* u272 */
223	compatible = "ti,tps544b25";
224	reg = <0x14>;
225	};
226	reg_util_3v3: tps544@1d { /* u278 */
227	compatible = "ti,tps544b25";
228	reg = <0x1d>;
229	};
230	};
231	pmbus1_ina226_i2c: i2c@1 {
232	#address-cells = <1>;
233	#size-cells = <0>;
234	reg = <1>;
235	/* FIXME check alerts coming to SC */
236	vcc_cpm: ina226@44 { /* u273 */
237	compatible = "ti,ina226";
238	reg = <0x44>;
239	shunt-resistor = <1000>;
240	};
241	};
242	i2c@2 { /* NC / / FIXME maybe remove */
243	#address-cells = <1>;
244	#size-cells = <0>;
245	reg = <2>;
246	};
247	pcie_smbus: i2c@3 {
248	#address-cells = <1>;
249	#size-cells = <0>;
250	reg = <3>;
251	};
252	pcie2_smbus: i2c@4 {
253	#address-cells = <1>;
254	#size-cells = <0>;
255	reg = <4>;
256	};
257	i2c@5 { /* NC */
258	#address-cells = <1>;
259	#size-cells = <0>;
260	reg = <5>;
261	};
262	user_si570: i2c@6 {
263	#address-cells = <1>;
264	#size-cells = <0>;
265	reg = <6>;
266	};
267	/* 7 unused */
268	};
269	};
270
271	&i2c1 { /* i2c1 MIO 36-37 */
272	status = "okay";
273	clock-frequency = <400000>;
274	pinctrl-names = "default", "gpio";
275	pinctrl-0 = <&pinctrl_i2c1_default>;
276	pinctrl-1 = <&pinctrl_i2c1_gpio>;
277	scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
278	sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
279
280	i2c-mux@74 { /* u35 */
281	compatible = "nxp,pca9548";
282	#address-cells = <1>;
283	#size-cells = <0>;
284	reg = <0x74>;
285	/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
286	dc_i2c: i2c@0 {
287	#address-cells = <1>;
288	#size-cells = <0>;
289	reg = <0>;
290	/* Use for storing information about SC board */
291	eeprom: eeprom@54 { /* u34 - m24128 16kB */
292	compatible = "st,24c128", "atmel,24c128";
293	reg = <0x54>; /* & 0x5c */
294	};
295	si570_ref_clk: clock-generator@5d { /* u32 */
296	#clock-cells = <0>;
297	compatible = "silabs,si570";
298	reg = <0x5d>;
299	temperature-stability = <50>;
300	factory-fout = <33333333>;
301	clock-frequency = <33333333>;
302	clock-output-names = "ref_clk";
303	silabs,skip-recall;
304	};
305	};
306	i2c@1 { /* NC - FIXME */
307	#address-cells = <1>;
308	#size-cells = <0>;
309	reg = <1>;
310	};
311	i2c@2 { /* NC - FIXME */
312	#address-cells = <1>;
313	#size-cells = <0>;
314	reg = <2>;
315	};
316	i2c@3 { /* NC - FIXME */
317	#address-cells = <1>;
318	#size-cells = <0>;
319	reg = <3>;
320	};
321	lpddr4_si570_clk2_i2c: i2c@4 {
322	#address-cells = <1>;
323	#size-cells = <0>;
324	reg = <4>;
325	lpddr4_clk2: clock-generator@60 { /* u3 */
326	#clock-cells = <0>;
327	compatible = "silabs,si570";
328	reg = <0x60>;
329	temperature-stability = <50>;
330	factory-fout = <200000000>;
331	clock-frequency = <200000000>;
332	clock-output-names = "lpddr4_clk2";
333	};
334	};
335	lpddr4_si570_clk1_i2c: i2c@5 {
336	#address-cells = <1>;
337	#size-cells = <0>;
338	reg = <5>;
339	lpddr4_clk1: clock-generator@60 { /* u248 */
340	#clock-cells = <0>;
341	compatible = "silabs,si570";
342	reg = <0x60>;
343	temperature-stability = <50>;
344	factory-fout = <200000000>;
345	clock-frequency = <200000000>;
346	clock-output-names = "lpddr4_clk1";
347	};
348	};
349	/* 6-7 unused */
350	};
351	};
352
353	&usb0 { /* MIO52 - MIO63 */
354	status = "okay";
355	phy-names = "usb3-phy";
356	phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
357	};
358
359	&psgtr {
360	status = "okay";
361	/* sgmii, usb3 */
362	clocks = <&si5332_1>, <&si5332_2>;
363	clock-names = "ref0", "ref1";
364	};
365
366	&dwc3_0 {
367	status = "okay";
368	dr_mode = "peripheral";
369	snps,dis_u2_susphy_quirk;
370	snps,dis_u3_susphy_quirk;
371	maximum-speed = "super-speed";
372	};
373
374	&xilinx_ams {
375	status = "okay";
376	};
377
378	&ams_ps {
379	status = "okay";
380	};
381
382	&ams_pl {
383	status = "okay";
384	};
385
386	&pinctrl0 {
387	status = "okay";
388	pinctrl_i2c0_default: i2c0-default {
389	mux {
390	groups = "i2c0_8_grp";
391	function = "i2c0";
392	};
393
394	conf {
395	groups = "i2c0_8_grp";
396	bias-pull-up;
397	slew-rate = <SLEW_RATE_SLOW>;
398	power-source = <IO_STANDARD_LVCMOS18>;
399	};
400	};
401
8026aa61	402	pinctrl_i2c0_gpio: i2c0-gpio-grp {
eb357b75 MS	403	mux {
	404	groups = "gpio0_34_grp", "gpio0_35_grp";
	405	function = "gpio0";
	406	};
	407
	408	conf {
	409	groups = "gpio0_34_grp", "gpio0_35_grp";
	410	slew-rate = <SLEW_RATE_SLOW>;
	411	power-source = <IO_STANDARD_LVCMOS18>;
	412	};
	413	};
	414
	415	pinctrl_i2c1_default: i2c1-default {
	416	mux {
	417	groups = "i2c1_9_grp";
	418	function = "i2c1";
	419	};
	420
	421	conf {
	422	groups = "i2c1_9_grp";
	423	bias-pull-up;
	424	slew-rate = <SLEW_RATE_SLOW>;
	425	power-source = <IO_STANDARD_LVCMOS18>;
	426	};
	427	};
	428
8026aa61	429	pinctrl_i2c1_gpio: i2c1-gpio-grp {
eb357b75 MS	430	mux {
	431	groups = "gpio0_36_grp", "gpio0_37_grp";
	432	function = "gpio0";
	433	};
	434
	435	conf {
	436	groups = "gpio0_36_grp", "gpio0_37_grp";
	437	slew-rate = <SLEW_RATE_SLOW>;
	438	power-source = <IO_STANDARD_LVCMOS18>;
	439	};
	440	};
	441	};