[J-u-boot.git] / arch / arm / dts / zynqmp-vp-x-a2785-00-revA.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller
 *
 * (C) Copyright 2021 - 2022, Xilinx, Inc.
 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
 *
 * Michal Simek <[email protected]>
 */
/dts-v1/;

#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>

/ {
	model = "ZynqMP System Controller on vp-x-a2785-00 board RevA";
	compatible = "xlnx,zynqmp-vp-x-a2785-00-revA",
		     "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp";

	aliases {
		ethernet0 = &gem0;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		mmc0 = &sdhci0;
		serial0 = &uart0;
		serial1 = &dcc;
		spi0 = &qspi;
		usb0 = &usb0;
		usb1 = &usb1;
		nvmem0 = &eeprom;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0 0 0 0x80000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		j383 {
			label = "j383";
			gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
			linux,code = <BTN_MISC>;
			wakeup-source;
			autorepeat;
		};
	};

	leds {
		compatible = "gpio-leds";
		heartbeat-led { /* ds52 */
			label = "heartbeat";
			gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	si5332_0: si5332_0 { /* ps_ref_clk - u142 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <33333333>;
	};

	si5332_1: si5332_1 { /* clk0_sgmii - u142 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <33333333>; /* FIXME */
	};

	si5332_2: si5332_2 { /* clk1_usb - u142 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
	};
};

&qspi { /* MIO 0-5 */
	status = "okay";
	flash@0 {
		compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		spi-tx-bus-width = <4>; /* maybe 4 here */
		spi-rx-bus-width = <4>;
		spi-max-frequency = <108000000>;
		partition@0 { /* for testing purpose */
			label = "qspi";
			reg = <0 0x4000000>;
		};
	};
};

&sdhci1 { /* sd MIO 45-51 */
	status = "okay";
	no-1-8-v;
	disable-wp;
	xlnx,mio-bank = <1>;
};

&uart0 { /* uart0 MIO38-39 */
	status = "okay";
	bootph-all;
};

&gem0 {
	status = "okay";
	phy-handle = <&phy0>;
	phy-mode = "sgmii"; /* DTG generates this properly 1512 */
	is-internal-pcspma;
	/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
	/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
	phy0: ethernet-phy@0 { /* u131 - M88e1512 */
		reg = <0>;
	};
};

&gpio {
	status = "okay";
	gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
		  "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
		  "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */
		  "", "", "", "", "", /* 15 - 19 */
		  "", "", "", "", "", /* 20 - 24 */
		  "", "", "", "", "", /* 25 - 29 */
		  "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
		  "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
		  "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
		  "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
		  "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
		  "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
		  "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
		  "", "", "", "", "", /* 65 - 69 */
		  "", "", "", "", "", /* 70 - 74 */
		  "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
		  "", "", /* 78 - 79 */
		  "", "", "", "", "", /* 80 - 84 */
		  "", "", "", "", "", /* 85 - 89 */
		  "", "", "", "", "", /* 90 - 94 */
		  "", "", "", "", "", /* 95 - 99 */
		  "", "", "", "", "", /* 100 - 104 */
		  "", "", "", "", "", /* 105 - 109 */
		  "", "", "", "", "", /* 110 - 114 */
		  "", "", "", "", "", /* 115 - 119 */
		  "", "", "", "", "", /* 120 - 124 */
		  "", "", "", "", "", /* 125 - 129 */
		  "", "", "", "", "", /* 130 - 134 */
		  "", "", "", "", "", /* 135 - 139 */
		  "", "", "", "", "", /* 140 - 144 */
		  "", "", "", "", "", /* 145 - 149 */
		  "", "", "", "", "", /* 150 - 154 */
		  "", "", "", "", "", /* 155 - 159 */
		  "", "", "", "", "", /* 160 - 164 */
		  "", "", "", "", "", /* 165 - 169 */
		  "", "", "", ""; /* 170 - 173 */
};

&i2c0 { /* MIO 34-35 - can't stay here */
	status = "okay";
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c0_default>;
	pinctrl-1 = <&pinctrl_i2c0_gpio>;
	scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller; /* interrupt not connected */
		#gpio-cells = <2>;
		gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */
				  "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
				  "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */
				  "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
	};

	i2c-mux@74 { /* u33 */
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x74>;
		/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
		pmbus_i2c: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			/* On connector J325 */
			reg_vccint: tps53681@60 { /* u266 - 0xc0 */
				compatible = "ti,tps53681", "ti,tps53679";
				reg = <0x60>;
			};
			reg_vcc1v1_lp4: tps544@d { /* u85 */
				compatible = "ti,tps544b25";
				reg = <0xd>;
			};
			reg_mgtyavcc: tps544@10 { /* u274 */
				compatible = "ti,tps544b25";
				reg = <0x10>;
			};
			reg_mgtyavtt: tps544@11 { /* u275 */
				compatible = "ti,tps544b25";
				reg = <0x11>;
			};
			reg_vccaux: tps544@12 { /* u276 */
				compatible = "ti,tps544b25";
				reg = <0x12>;
			};
			reg_vcc_cpm: tps544@14 { /* u272 */
				compatible = "ti,tps544b25";
				reg = <0x14>;
			};
			reg_util_3v3: tps544@1d { /* u278 */
				compatible = "ti,tps544b25";
				reg = <0x1d>;
			};
		};
		pmbus1_ina226_i2c: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			/* FIXME check alerts coming to SC */
			vcc_cpm: ina226@44 { /* u273 */
				compatible = "ti,ina226";
				reg = <0x44>;
				shunt-resistor = <1000>;
			};
		};
		i2c@2 { /* NC */ /* FIXME maybe remove */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};
		pcie_smbus: i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};
		pcie2_smbus: i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
		};
		i2c@5 { /* NC */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
		};
		user_si570: i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
		};
		/* 7 unused */
	};
};

&i2c1 { /* i2c1 MIO 36-37 */
	status = "okay";
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1_default>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	i2c-mux@74 { /* u35 */
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x74>;
		/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
		dc_i2c: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			/* Use for storing information about SC board */
			eeprom: eeprom@54 { /* u34 - m24128 16kB */
				compatible = "st,24c128", "atmel,24c128";
				reg = <0x54>; /* & 0x5c */
			};
			si570_ref_clk: clock-generator@5d { /* u32 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x5d>;
				temperature-stability = <50>;
				factory-fout = <33333333>;
				clock-frequency = <33333333>;
				clock-output-names = "ref_clk";
				silabs,skip-recall;
			};
		};
		i2c@1 { /* NC - FIXME */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
		i2c@2 { /* NC - FIXME */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};
		i2c@3 { /* NC - FIXME */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};
		lpddr4_si570_clk2_i2c: i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
			lpddr4_clk2: clock-generator@60 { /* u3 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x60>;
				temperature-stability = <50>;
				factory-fout = <200000000>;
				clock-frequency = <200000000>;
				clock-output-names = "lpddr4_clk2";
			};
		};
		lpddr4_si570_clk1_i2c: i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
			lpddr4_clk1: clock-generator@60 { /* u248 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x60>;
				temperature-stability = <50>;
				factory-fout = <200000000>;
				clock-frequency = <200000000>;
				clock-output-names = "lpddr4_clk1";
			};
		};
		/* 6-7 unused */
	};
};

&usb0 { /* MIO52 - MIO63 */
	status = "okay";
	phy-names = "usb3-phy";
	phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
};

&psgtr {
	status = "okay";
	/* sgmii, usb3 */
	clocks = <&si5332_1>, <&si5332_2>;
	clock-names = "ref0", "ref1";
};

&dwc3_0 {
	status = "okay";
	dr_mode = "peripheral";
	snps,dis_u2_susphy_quirk;
	snps,dis_u3_susphy_quirk;
	maximum-speed = "super-speed";
};

&xilinx_ams {
	status = "okay";
};

&ams_ps {
	status = "okay";
};

&ams_pl {
	status = "okay";
};

&pinctrl0 {
	status = "okay";
	pinctrl_i2c0_default: i2c0-default {
		mux {
			groups = "i2c0_8_grp";
			function = "i2c0";
		};

		conf {
			groups = "i2c0_8_grp";
			bias-pull-up;
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};
	};

	pinctrl_i2c0_gpio: i2c0-gpio {
		mux {
			groups = "gpio0_34_grp", "gpio0_35_grp";
			function = "gpio0";
		};

		conf {
			groups = "gpio0_34_grp", "gpio0_35_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};
	};

	pinctrl_i2c1_default: i2c1-default {
		mux {
			groups = "i2c1_9_grp";
			function = "i2c1";
		};

		conf {
			groups = "i2c1_9_grp";
			bias-pull-up;
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};
	};

	pinctrl_i2c1_gpio: i2c1-gpio {
		mux {
			groups = "gpio0_36_grp", "gpio0_37_grp";
			function = "gpio0";
		};

		conf {
			groups = "gpio0_36_grp", "gpio0_37_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};
	};
};
Commit	Line	Data
eb357b75 MS	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller
	4	*
	5	* (C) Copyright 2021 - 2022, Xilinx, Inc.
	6	* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
	7	*
	8	* Michal Simek <[email protected]>
	9	*/
	10	/dts-v1/;
	11
	12	#include "zynqmp.dtsi"
	13	#include "zynqmp-clk-ccf.dtsi"
	14	#include <dt-bindings/input/input.h>
	15	#include <dt-bindings/gpio/gpio.h>
	16	#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
	17	#include <dt-bindings/phy/phy.h>
	18
	19	/ {
	20	model = "ZynqMP System Controller on vp-x-a2785-00 board RevA";
	21	compatible = "xlnx,zynqmp-vp-x-a2785-00-revA",
	22	"xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp";
	23
	24	aliases {
	25	ethernet0 = &gem0;
	26	i2c0 = &i2c0;
	27	i2c1 = &i2c1;
	28	mmc0 = &sdhci0;
	29	serial0 = &uart0;
	30	serial1 = &dcc;
	31	spi0 = &qspi;
	32	usb0 = &usb0;
	33	usb1 = &usb1;
	34	nvmem0 = &eeprom;
	35	};
	36
	37	chosen {
	38	bootargs = "earlycon";
	39	stdout-path = "serial0:115200n8";
	40	};
	41
	42	memory@0 {
	43	device_type = "memory";
	44	reg = <0 0 0 0x80000000>;
	45	};
	46
	47	gpio-keys {
	48	compatible = "gpio-keys";
	49	autorepeat;
	50	j383 {
	51	label = "j383";
	52	gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
	53	linux,code = <BTN_MISC>;
	54	wakeup-source;
	55	autorepeat;
	56	};
	57	};
	58
	59	leds {
	60	compatible = "gpio-leds";
	61	heartbeat-led { /* ds52 */
	62	label = "heartbeat";
	63	gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
	64	linux,default-trigger = "heartbeat";
65	};
66	};
67
68	si5332_0: si5332_0 { /* ps_ref_clk - u142 */
69	compatible = "fixed-clock";
70	#clock-cells = <0>;
71	clock-frequency = <33333333>;
72	};
73
74	si5332_1: si5332_1 { /* clk0_sgmii - u142 */
75	compatible = "fixed-clock";
76	#clock-cells = <0>;
77	clock-frequency = <33333333>; /* FIXME */
78	};
79
80	si5332_2: si5332_2 { /* clk1_usb - u142 */
81	compatible = "fixed-clock";
82	#clock-cells = <0>;
83	clock-frequency = <27000000>;
84	};
85	};
86
87	&qspi { /* MIO 0-5 */
88	status = "okay";
89	flash@0 {
90	compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */
91	#address-cells = <1>;
92	#size-cells = <1>;
93	reg = <0>;
94	spi-tx-bus-width = <4>; /* maybe 4 here */
95	spi-rx-bus-width = <4>;
96	spi-max-frequency = <108000000>;
97	partition@0 { /* for testing purpose */
98	label = "qspi";
99	reg = <0 0x4000000>;
100	};
101	};
102	};
103
104	&sdhci1 { /* sd MIO 45-51 */
105	status = "okay";
106	no-1-8-v;
107	disable-wp;
108	xlnx,mio-bank = <1>;
109	};
110
111	&uart0 { /* uart0 MIO38-39 */
112	status = "okay";
113	bootph-all;
114	};
115
116	&gem0 {
117	status = "okay";
118	phy-handle = <&phy0>;
119	phy-mode = "sgmii"; /* DTG generates this properly 1512 */
120	is-internal-pcspma;
121	/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
122	/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
123	phy0: ethernet-phy@0 { /* u131 - M88e1512 */
124	reg = <0>;
125	};
126	};
127
128	&gpio {
129	status = "okay";
130	gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
131	"QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
132	"SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */
133	"", "", "", "", "", /* 15 - 19 */
134	"", "", "", "", "", /* 20 - 24 */
135	"", "", "", "", "", /* 25 - 29 */
136	"", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
137	"LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
138	"", "", "ETH_RESET_B", "", "", /* 40 - 44 */
139	"SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
140	"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
141	"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
142	"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
143	"", "", "", "", "", /* 65 - 69 */
144	"", "", "", "", "", /* 70 - 74 */
145	"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
146	"", "", /* 78 - 79 */
147	"", "", "", "", "", /* 80 - 84 */
148	"", "", "", "", "", /* 85 - 89 */
149	"", "", "", "", "", /* 90 - 94 */
150	"", "", "", "", "", /* 95 - 99 */
151	"", "", "", "", "", /* 100 - 104 */
152	"", "", "", "", "", /* 105 - 109 */
153	"", "", "", "", "", /* 110 - 114 */
154	"", "", "", "", "", /* 115 - 119 */
155	"", "", "", "", "", /* 120 - 124 */
156	"", "", "", "", "", /* 125 - 129 */
157	"", "", "", "", "", /* 130 - 134 */
158	"", "", "", "", "", /* 135 - 139 */
159	"", "", "", "", "", /* 140 - 144 */
160	"", "", "", "", "", /* 145 - 149 */
161	"", "", "", "", "", /* 150 - 154 */
162	"", "", "", "", "", /* 155 - 159 */
163	"", "", "", "", "", /* 160 - 164 */
164	"", "", "", "", "", /* 165 - 169 */
165	"", "", "", ""; /* 170 - 173 */
166	};
167
168	&i2c0 { /* MIO 34-35 - can't stay here */
169	status = "okay";
170	clock-frequency = <400000>;
171	pinctrl-names = "default", "gpio";
172	pinctrl-0 = <&pinctrl_i2c0_default>;
173	pinctrl-1 = <&pinctrl_i2c0_gpio>;
174	scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
175	sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
176
177	tca6416_u233: gpio@20 { /* u233 / / FIXME - address maybe wrong */
178	compatible = "ti,tca6416";
179	reg = <0x20>;
180	gpio-controller; /* interrupt not connected */
181	#gpio-cells = <2>;
182	gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */
183	"", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
184	"", "", "", "VCCINT_FAULT_B", /* 10 - 13 */
185	"VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
186	};
187
188	i2c-mux@74 { /* u33 */
189	compatible = "nxp,pca9548";
190	#address-cells = <1>;
191	#size-cells = <0>;
192	reg = <0x74>;
193	/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
194	pmbus_i2c: i2c@0 {
195	#address-cells = <1>;
196	#size-cells = <0>;
197	reg = <0>;
198	/* On connector J325 */
199	reg_vccint: tps53681@60 { /* u266 - 0xc0 */
200	compatible = "ti,tps53681", "ti,tps53679";
201	reg = <0x60>;
202	};
203	reg_vcc1v1_lp4: tps544@d { /* u85 */
204	compatible = "ti,tps544b25";
205	reg = <0xd>;
206	};
207	reg_mgtyavcc: tps544@10 { /* u274 */
208	compatible = "ti,tps544b25";
209	reg = <0x10>;
210	};
211	reg_mgtyavtt: tps544@11 { /* u275 */
212	compatible = "ti,tps544b25";
213	reg = <0x11>;
214	};
215	reg_vccaux: tps544@12 { /* u276 */
216	compatible = "ti,tps544b25";
217	reg = <0x12>;
218	};
219	reg_vcc_cpm: tps544@14 { /* u272 */
220	compatible = "ti,tps544b25";
221	reg = <0x14>;
222	};
223	reg_util_3v3: tps544@1d { /* u278 */
224	compatible = "ti,tps544b25";
225	reg = <0x1d>;
226	};
227	};
228	pmbus1_ina226_i2c: i2c@1 {
229	#address-cells = <1>;
230	#size-cells = <0>;
231	reg = <1>;
232	/* FIXME check alerts coming to SC */
233	vcc_cpm: ina226@44 { /* u273 */
234	compatible = "ti,ina226";
235	reg = <0x44>;
236	shunt-resistor = <1000>;
237	};
238	};
239	i2c@2 { /* NC / / FIXME maybe remove */
240	#address-cells = <1>;
241	#size-cells = <0>;
242	reg = <2>;
243	};
244	pcie_smbus: i2c@3 {
245	#address-cells = <1>;
246	#size-cells = <0>;
247	reg = <3>;
248	};
249	pcie2_smbus: i2c@4 {
250	#address-cells = <1>;
251	#size-cells = <0>;
252	reg = <4>;
253	};
254	i2c@5 { /* NC */
255	#address-cells = <1>;
256	#size-cells = <0>;
257	reg = <5>;
258	};
259	user_si570: i2c@6 {
260	#address-cells = <1>;
261	#size-cells = <0>;
262	reg = <6>;
263	};
264	/* 7 unused */
265	};
266	};
267
268	&i2c1 { /* i2c1 MIO 36-37 */
269	status = "okay";
270	clock-frequency = <400000>;
271	pinctrl-names = "default", "gpio";
272	pinctrl-0 = <&pinctrl_i2c1_default>;
273	pinctrl-1 = <&pinctrl_i2c1_gpio>;
274	scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
275	sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH \| GPIO_OPEN_DRAIN)>;
276
277	i2c-mux@74 { /* u35 */
278	compatible = "nxp,pca9548";
279	#address-cells = <1>;
280	#size-cells = <0>;
281	reg = <0x74>;
282	/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
283	dc_i2c: i2c@0 {
284	#address-cells = <1>;
285	#size-cells = <0>;
286	reg = <0>;
287	/* Use for storing information about SC board */
288	eeprom: eeprom@54 { /* u34 - m24128 16kB */
289	compatible = "st,24c128", "atmel,24c128";
290	reg = <0x54>; /* & 0x5c */
291	};
292	si570_ref_clk: clock-generator@5d { /* u32 */
293	#clock-cells = <0>;
294	compatible = "silabs,si570";
295	reg = <0x5d>;
296	temperature-stability = <50>;
297	factory-fout = <33333333>;
298	clock-frequency = <33333333>;
299	clock-output-names = "ref_clk";
300	silabs,skip-recall;
301	};
302	};
303	i2c@1 { /* NC - FIXME */
304	#address-cells = <1>;
305	#size-cells = <0>;
306	reg = <1>;
307	};
308	i2c@2 { /* NC - FIXME */
309	#address-cells = <1>;
310	#size-cells = <0>;
311	reg = <2>;
312	};
313	i2c@3 { /* NC - FIXME */
314	#address-cells = <1>;
315	#size-cells = <0>;
316	reg = <3>;
317	};
318	lpddr4_si570_clk2_i2c: i2c@4 {
319	#address-cells = <1>;
320	#size-cells = <0>;
321	reg = <4>;
322	lpddr4_clk2: clock-generator@60 { /* u3 */
323	#clock-cells = <0>;
324	compatible = "silabs,si570";
325	reg = <0x60>;
326	temperature-stability = <50>;
327	factory-fout = <200000000>;
328	clock-frequency = <200000000>;
329	clock-output-names = "lpddr4_clk2";
330	};
331	};
332	lpddr4_si570_clk1_i2c: i2c@5 {
333	#address-cells = <1>;
334	#size-cells = <0>;
335	reg = <5>;
336	lpddr4_clk1: clock-generator@60 { /* u248 */
337	#clock-cells = <0>;
338	compatible = "silabs,si570";
339	reg = <0x60>;
340	temperature-stability = <50>;
341	factory-fout = <200000000>;
342	clock-frequency = <200000000>;
343	clock-output-names = "lpddr4_clk1";
344	};
345	};
346	/* 6-7 unused */
347	};
348	};
349
350	&usb0 { /* MIO52 - MIO63 */
351	status = "okay";
352	phy-names = "usb3-phy";
353	phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
354	};
355
356	&psgtr {
357	status = "okay";
358	/* sgmii, usb3 */
359	clocks = <&si5332_1>, <&si5332_2>;
360	clock-names = "ref0", "ref1";
361	};
362
363	&dwc3_0 {
364	status = "okay";
365	dr_mode = "peripheral";
366	snps,dis_u2_susphy_quirk;
367	snps,dis_u3_susphy_quirk;
368	maximum-speed = "super-speed";
369	};
370
371	&xilinx_ams {
372	status = "okay";
373	};
374
375	&ams_ps {
376	status = "okay";
377	};
378
379	&ams_pl {
380	status = "okay";
381	};
382
383	&pinctrl0 {
384	status = "okay";
385	pinctrl_i2c0_default: i2c0-default {
386	mux {
387	groups = "i2c0_8_grp";
388	function = "i2c0";
389	};
390
391	conf {
392	groups = "i2c0_8_grp";
393	bias-pull-up;
394	slew-rate = <SLEW_RATE_SLOW>;
395	power-source = <IO_STANDARD_LVCMOS18>;
396	};
397	};
398
399	pinctrl_i2c0_gpio: i2c0-gpio {
400	mux {
401	groups = "gpio0_34_grp", "gpio0_35_grp";
402	function = "gpio0";
403	};
404
405	conf {
406	groups = "gpio0_34_grp", "gpio0_35_grp";
407	slew-rate = <SLEW_RATE_SLOW>;
408	power-source = <IO_STANDARD_LVCMOS18>;
409	};
410	};
411
412	pinctrl_i2c1_default: i2c1-default {
413	mux {
414	groups = "i2c1_9_grp";
415	function = "i2c1";
416	};
417
418	conf {
419	groups = "i2c1_9_grp";
420	bias-pull-up;
421	slew-rate = <SLEW_RATE_SLOW>;
422	power-source = <IO_STANDARD_LVCMOS18>;
423	};
424	};
425
426	pinctrl_i2c1_gpio: i2c1-gpio {
427	mux {
428	groups = "gpio0_36_grp", "gpio0_37_grp";
429	function = "gpio0";
430	};
431
432	conf {
433	groups = "gpio0_36_grp", "gpio0_37_grp";
434	slew-rate = <SLEW_RATE_SLOW>;
435	power-source = <IO_STANDARD_LVCMOS18>;
436	};
437	};
438	};