[J-u-boot.git] / include / configs / quantum.h

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 * changes for 16M board
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#undef CONFIG_MPC860
#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
#define CONFIG_RPXLITE		1	/* QUANTUM is the RPXlite clone */
#define CONFIG_RMU		1   /* The QUNATUM is based on our RMU */

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

/* default developmenmt environment */

#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passed to Linux in MHz. Needed for old kernels (2.4) crashes for new kernels */

#define CONFIG_ETHADDR 00:0B:17:00:00:00

#define CONFIG_IPADDR  10.10.69.10
#define CONFIG_SERVERIP 10.10.69.49
#define CONFIG_NETMASK	255.255.255.0
#define CONFIG_HOSTNAME QUANTUM
#define CONFIG_ROOTPATH /opt/eldk/pcc_8xx

#define CONFIG_BOOTARGS	 "root=/dev/ram rw"

#define CONFIG_BOOTCOMMAND "bootm ff000000"

#define CONFIG_EXTRA_ENV_SETTINGS \
    "serial#=12345\0"		\
	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0"	\
	"ramargs=setenv bootargs root=/dev/ram rw\0" \
    "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0"

/*
 * Select the more full-featured memory test (Barr embedded systems)
 */
#define CFG_ALT_MEMTEST

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/


/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
#define CONFIG_RTC_M48T35A 1

#if 0
#define CONFIG_WATCHDOG 1		/* watchdog enabled		*/
#else
#undef CONFIG_WATCHDOG
#endif

/*  NVRAM and RTC */
#define CFG_NVRAM_BASE_ADDR 0xFA000000
#define CFG_NVRAM_SIZE 2048


#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_DATE	| \
				CFG_CMD_DHCP	| \
		CFG_CMD_PING	| \
		CFG_CMD_REGINFO)

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define CONFIG_AUTOBOOT_KEYED	/* Enable password protection */
#define CONFIG_AUTOBOOT_PROMPT		"\nEnter password - autoboot in %d sec...\n"
#define CONFIG_AUTOBOOT_DELAY_STR	"system"
/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00040000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x01f00000	/* 256K ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFA200000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE	0xFF000000

#if 1
    #define CFG_FLASH_CFI_DRIVER
#else
    #undef CFG_FLASH_CFI_DRIVER
#endif


#ifdef CFG_FLASH_CFI_DRIVER
    #define CFG_FLASH_CFI 1
    #undef CFG_FLASH_USE_BUFFER_WRITE
    #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
#endif

/*%%% #define CFG_FLASH_BASE		0xFFF00000 */
#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
#endif
#define CFG_MONITOR_BASE	0xFFF00000
/*%%% #define CFG_MONITOR_BASE	CFG_FLASH_BASE */
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip */

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET	    0x00F40000	/*   Offset   of Environment Sector	absolute address 0xfff40000*/
#define CFG_ENV_SIZE		0x40000 /* Total Size of Environment Sector	*/
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_ENV_OFFSET)

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

/* FPGA */
#define CONFIG_MISC_INIT_R
#define CFG_FPGA_SPARTAN2
#define CFG_FPGA_PROG_FEEDBACK


/*-----------------------------------------------------------------------
 * Reset address
 */
#define CFG_RESET_ADDRESS	((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_MLRC10)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR (PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
/* up to 50 MHz we use a 1:1 clock */
#define CFG_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF00
/* up to 50 MHz we use a 1:1 clock */
#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CFG_DER 0x2002000F*/
#define CFG_DER 0

/*
 * Init Memory Controller:
 *
 * BR0 and OR0 (FLASH)
 */

#define FLASH_BASE_PRELIM	0xFE000000	/* FLASH base */
#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */

/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)

#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)

/*
 * BR1 and OR1 (SDRAM)
 *
 */
#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
#define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB */

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CFG_OR_TIMING_SDRAM	0x00000E00

#define CFG_OR1_PRELIM	(0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/* RPXLITE mem setting */
#define CFG_BR3_PRELIM	0xFA400001		/* FPGA */
#define CFG_OR3_PRELIM	0xFFFF8910

#define CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
#define CFG_OR4_PRELIM	0xFFFE0970

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CFG_MAMR_PTA	20

/*
 * Refresh clock Prescalar
 */
#define CFG_MPTPR	MPTPR_PTP_DIV2

/*
 * MAMR settings for SDRAM
 */

/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02	/* Software reboot			*/

/*
 * BCSRx
 *
 * Board Status and Control Registers
 *
 */

#define BCSR0 0xFA400000
#define BCSR1 0xFA400001
#define BCSR2 0xFA400002
#define BCSR3 0xFA400003

#define BCSR0_ENMONXCVR 0x01	/* Monitor XVCR Control */
#define BCSR0_ENNVRAM	0x02	/* CS4# Control */
#define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
#define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
#define BCSR0_COLTEST	0x20
#define BCSR0_ETHLPBK	0x40
#define BCSR0_ETHEN	0x80

#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
#define BCSR1_PCVCTL6	0x02
#define BCSR1_PCVCTL5	0x04
#define BCSR1_PCVCTL4	0x08
#define BCSR1_IPB5SEL	0x10

#define BCSR2_ENPA5HDR	0x08	/* USB Control */
#define BCSR2_ENUSBCLK	0x10
#define BCSR2_USBPWREN	0x20
#define BCSR2_USBSPD	0x40
#define BCSR2_USBSUSP	0x80

#define BCSR3_BWRTC	0x01	/* Real Time Clock Battery */
#define BCSR3_BWNVR	0x02	/* NVRAM Battery */
#define BCSR3_RDY_BSY	0x04	/* Flash Operation */
#define BCSR3_RPXL	0x08	/* Reserved (reads back '1') */
#define BCSR3_D27	0x10	/* Dip Switch settings */
#define BCSR3_D26	0x20
#define BCSR3_D25	0x40
#define BCSR3_D24	0x80

#endif	/* __CONFIG_H */
Commit	Line	Data
da93ed81 WD	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	* changes for 16M board
	27	*/
	28
	29	#ifndef __CONFIG_H
	30	#define __CONFIG_H
	31
	32	/*
	33	* High Level Configuration Options
	34	* (easy to change)
	35	*/
	36
	37	#undef CONFIG_MPC860
	38	#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
	39	#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */
	40	#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */
	41
	42	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	43	#undef CONFIG_8xx_CONS_SMC2
	44	#undef CONFIG_8xx_CONS_NONE
	45	#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
	46	#if 0
	47	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	48	#else
	49	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	50	#endif
	51
	52	/* default developmenmt environment */
	53
	54	#undef CONFIG_CLOCKS_IN_MHZ /* clocks passed to Linux in MHz. Needed for old kernels (2.4) crashes for new kernels */
	55
	56	#define CONFIG_ETHADDR 00:0B:17:00:00:00
	57
	58	#define CONFIG_IPADDR 10.10.69.10
	59	#define CONFIG_SERVERIP 10.10.69.49
	60	#define CONFIG_NETMASK 255.255.255.0
	61	#define CONFIG_HOSTNAME QUANTUM
	62	#define CONFIG_ROOTPATH /opt/eldk/pcc_8xx
	63
	64	#define CONFIG_BOOTARGS "root=/dev/ram rw"
65
66	#define CONFIG_BOOTCOMMAND "bootm ff000000"
67
68	#define CONFIG_EXTRA_ENV_SETTINGS \
69	"serial#=12345\0" \
70	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
71	"ramargs=setenv bootargs root=/dev/ram rw\0" \
72	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0"
73
74	/*
75	* Select the more full-featured memory test (Barr embedded systems)
76	*/
77	#define CFG_ALT_MEMTEST
78
79	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
80	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
81
82
83	/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
84	#define CONFIG_RTC_M48T35A 1
85
86	#if 0
87	#define CONFIG_WATCHDOG 1 /* watchdog enabled */
88	#else
89	#undef CONFIG_WATCHDOG
90	#endif
91
92	/* NVRAM and RTC */
93	#define CFG_NVRAM_BASE_ADDR 0xFA000000
94	#define CFG_NVRAM_SIZE 2048
95
96
97	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
98	CFG_CMD_DATE \| \
99	CFG_CMD_DHCP \| \
100	CFG_CMD_PING \| \
101	CFG_CMD_REGINFO)
102
103	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| CONFIG_BOOTP_BOOTFILESIZE)
104
105	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
106	#include <cmd_confdefs.h>
107
108	#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
109	#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
110	#define CONFIG_AUTOBOOT_DELAY_STR "system"
111	/*
112	* Miscellaneous configurable options
113	*/
114	#define CFG_LONGHELP /* undef to save memory */
115	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
116	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
117	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
118	#else
119	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
120	#endif
121	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
122	#define CFG_MAXARGS 16 /* max number of command args */
123	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
124
125	#define CFG_MEMTEST_START 0x00040000 /* memtest works on */
126	#define CFG_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */
127
128	#define CFG_LOAD_ADDR 0x100000 /* default load address */
129
130	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
131
132	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
133
134	/*
135	* Low Level Configuration Settings
136	* (address mappings, register initial values, etc.)
137	* You should know what you are doing if you make changes here.
138	*/
139	/*-----------------------------------------------------------------------
140	* Internal Memory Mapped Register
141	*/
142	#define CFG_IMMR 0xFA200000
143
144	/*-----------------------------------------------------------------------
145	* Definitions for initial stack pointer and data area (in DPRAM)
146	*/
147	#define CFG_INIT_RAM_ADDR CFG_IMMR
148	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
149	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
150	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
151	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
152
153	/*-----------------------------------------------------------------------
154	* Start addresses for the final memory configuration
155	* (Set up by the startup code)
156	* Please note that CFG_SDRAM_BASE _must_ start at 0
157	*/
158	#define CFG_SDRAM_BASE 0x00000000
159	#define CFG_FLASH_BASE 0xFF000000
160
161	#if 1
162	#define CFG_FLASH_CFI_DRIVER
163	#else
164	#undef CFG_FLASH_CFI_DRIVER
165	#endif
166
167
168	#ifdef CFG_FLASH_CFI_DRIVER
169	#define CFG_FLASH_CFI 1
170	#undef CFG_FLASH_USE_BUFFER_WRITE
171	#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
172	#endif
173
174	/%%% #define CFG_FLASH_BASE 0xFFF00000 /
175	#if defined(DEBUG) \|\| (CONFIG_COMMANDS & CFG_CMD_IDE)
176	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
177	#else
178	#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
179	#endif
180	#define CFG_MONITOR_BASE 0xFFF00000
181	/%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE /
182	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
183
184	/*
185	* For booting Linux, the board info and command line data
186	* have to be in the first 8 MB of memory, since this is
187	* the maximum mapped by the Linux kernel during initialization.
188	*/
189	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
190
191	/*-----------------------------------------------------------------------
192	* FLASH organization
193	*/
194	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
195	#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
196
197	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
198	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
199
200	#define CFG_ENV_IS_IN_FLASH 1
201	#define CFG_ENV_OFFSET 0x00F40000 /* Offset of Environment Sector absolute address 0xfff40000*/
202	#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
203	#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
204
205	/* Address and size of Redundant Environment Sector */
206	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
207	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
208
209	/* FPGA */
210	#define CONFIG_MISC_INIT_R
211	#define CFG_FPGA_SPARTAN2
212	#define CFG_FPGA_PROG_FEEDBACK
213
214
215	/*-----------------------------------------------------------------------
216	* Reset address
217	*/
218	#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
219
220	/*-----------------------------------------------------------------------
221	* Cache Configuration
222	*/
223	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
224	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
225	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
226	#endif
227
228	/*-----------------------------------------------------------------------
229	* SYPCR - System Protection Control 11-9
230	* SYPCR can only be written once after reset!
231	*-----------------------------------------------------------------------
232	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
233	*/
234	#if defined(CONFIG_WATCHDOG)
235	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
236	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
237	#else
238	#define CFG_SYPCR (SYPCR_SWTC \| 0x00000600 \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
239	#endif
240
241	/*-----------------------------------------------------------------------
242	* SIUMCR - SIU Module Configuration 11-6
243	*-----------------------------------------------------------------------
244	* PCMCIA config., multi-function pin tri-state
245	*/
246	#define CFG_SIUMCR (SIUMCR_MLRC10)
247
248	/*-----------------------------------------------------------------------
249	* TBSCR - Time Base Status and Control 11-26
250	*-----------------------------------------------------------------------
251	* Clear Reference Interrupt Status, Timebase freezing enabled
252	*/
253	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF \| TBSCR_TBE)
254
255	/*-----------------------------------------------------------------------
256	* RTCSC - Real-Time Clock Status and Control Register 11-27
257	*-----------------------------------------------------------------------
258	*/
259	/%%%#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE) /
260	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_RTE)
261
262	/*-----------------------------------------------------------------------
263	* PISCR - Periodic Interrupt Status and Control 11-31
264	*-----------------------------------------------------------------------
265	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
266	*/
267	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
268
269	/*-----------------------------------------------------------------------
270	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
271	*-----------------------------------------------------------------------
272	* Reset PLL lock status sticky bit, timer expired status bit and timer
273	* interrupt status bit
274	*
275	* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
276	*/
277	/* up to 50 MHz we use a 1:1 clock */
278	#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) \| PLPRCR_TEXPS )
279
280	/*-----------------------------------------------------------------------
281	* SCCR - System Clock and reset Control Register 15-27
282	*-----------------------------------------------------------------------
283	* Set clock output, timebase and RTC source and divider,
284	* power management and some other internal clocks
285	*/
286	#define SCCR_MASK SCCR_EBDF00
287	/* up to 50 MHz we use a 1:1 clock */
288	#define CFG_SCCR (SCCR_COM00 \| SCCR_TBS)
289
290	/*-----------------------------------------------------------------------
291	* PCMCIA stuff
292	*-----------------------------------------------------------------------
293	*
294	*/
295	#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
296	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
297	#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
298	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
299	#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
300	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
301	#define CFG_PCMCIA_IO_ADDR (0xEC000000)
302	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
303
304	/*-----------------------------------------------------------------------
305	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
306	*-----------------------------------------------------------------------
307	*/
308
309	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
310
311	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
312	#undef CONFIG_IDE_LED /* LED for ide not supported */
313	#undef CONFIG_IDE_RESET /* reset for ide not supported */
314
315	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
316	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
317
318	#define CFG_ATA_IDE0_OFFSET 0x0000
319
320	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
321
322	/* Offset for data I/O */
323	#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
324
325	/* Offset for normal register accesses */
326	#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
327
328	/* Offset for alternate registers */
329	#define CFG_ATA_ALT_OFFSET 0x0100
330
331	/*-----------------------------------------------------------------------
332	*
333	*-----------------------------------------------------------------------
334	*
335	*/
336	/#define CFG_DER 0x2002000F/
337	#define CFG_DER 0
338
339	/*
340	* Init Memory Controller:
341	*
342	* BR0 and OR0 (FLASH)
343	*/
344
345	#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
346	#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
347
348	/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
349	#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK \| OR_BI)
350
351	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
352	#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) \| BR_V)
353
354	/*
355	* BR1 and OR1 (SDRAM)
356	*
357	*/
358	#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
359	#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
360
361	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
362	#define CFG_OR_TIMING_SDRAM 0x00000E00
363
364	#define CFG_OR1_PRELIM (0xF0000000 \| CFG_OR_TIMING_SDRAM ) /* map 256 MB */
365	#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
366
367	/* RPXLITE mem setting */
368	#define CFG_BR3_PRELIM 0xFA400001 /* FPGA */
369	#define CFG_OR3_PRELIM 0xFFFF8910
370
371	#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
372	#define CFG_OR4_PRELIM 0xFFFE0970
373
374	/*
375	* Memory Periodic Timer Prescaler
376	*/
377
378	/* periodic timer for refresh */
379	#define CFG_MAMR_PTA 20
380
381	/*
382	* Refresh clock Prescalar
383	*/
384	#define CFG_MPTPR MPTPR_PTP_DIV2
385
386	/*
387	* MAMR settings for SDRAM
388	*/
389
390	/* 9 column SDRAM */
391	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
392	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
393	MAMR_RLFA_16X \| MAMR_WLFA_16X \| MAMR_TLFA_16X)
394
395	/*
396	* Internal Definitions
397	*
398	* Boot Flags
399	*/
400	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
401	#define BOOTFLAG_WARM 0x02 /* Software reboot */
402
403	/*
404	* BCSRx
405	*
406	* Board Status and Control Registers
407	*
408	*/
409
410	#define BCSR0 0xFA400000
411	#define BCSR1 0xFA400001
412	#define BCSR2 0xFA400002
413	#define BCSR3 0xFA400003
414
415	#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
416	#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
417	#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
418	#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
419	#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
420	#define BCSR0_COLTEST 0x20
421	#define BCSR0_ETHLPBK 0x40
422	#define BCSR0_ETHEN 0x80
423
424	#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
425	#define BCSR1_PCVCTL6 0x02
426	#define BCSR1_PCVCTL5 0x04
427	#define BCSR1_PCVCTL4 0x08
428	#define BCSR1_IPB5SEL 0x10
429
430	#define BCSR2_ENPA5HDR 0x08 /* USB Control */
431	#define BCSR2_ENUSBCLK 0x10
432	#define BCSR2_USBPWREN 0x20
433	#define BCSR2_USBSPD 0x40
434	#define BCSR2_USBSUSP 0x80
435
436	#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
437	#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
438	#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
439	#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
440	#define BCSR3_D27 0x10 /* Dip Switch settings */
441	#define BCSR3_D26 0x20
442	#define BCSR3_D25 0x40
443	#define BCSR3_D24 0x80
444
445	#endif /* __CONFIG_H */