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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
2678059e SDPP |
2 | /* |
3 | * dts file for Xilinx ZynqMP Mini Configuration | |
4 | * | |
5 | * (C) Copyright 2018, Xilinx, Inc. | |
6 | * | |
7 | * Siva Durga Prasad <[email protected]> | |
2678059e SDPP |
8 | */ |
9 | ||
10 | /dts-v1/; | |
11 | ||
12 | / { | |
f3289d1f | 13 | model = "ZynqMP MINI EMMC0"; |
2678059e SDPP |
14 | compatible = "xlnx,zynqmp"; |
15 | #address-cells = <2>; | |
16 | #size-cells = <2>; | |
17 | ||
18 | aliases { | |
19 | serial0 = &dcc; | |
20 | mmc0 = &sdhci0; | |
2678059e SDPP |
21 | }; |
22 | ||
23 | chosen { | |
24 | stdout-path = "serial0:115200n8"; | |
25 | }; | |
26 | ||
27 | memory@0 { | |
28 | device_type = "memory"; | |
29 | reg = <0x0 0x0 0x0 0x20000000>; | |
30 | }; | |
31 | ||
32 | dcc: dcc { | |
33 | compatible = "arm,dcc"; | |
34 | status = "disabled"; | |
35 | u-boot,dm-pre-reloc; | |
36 | }; | |
37 | ||
bc0f4ed1 SDPP |
38 | clk_xin: clk_xin { |
39 | compatible = "fixed-clock"; | |
40 | #clock-cells = <0>; | |
41 | clock-frequency = <200000000>; | |
42 | }; | |
43 | ||
2678059e SDPP |
44 | amba: amba { |
45 | compatible = "simple-bus"; | |
46 | #address-cells = <2>; | |
47 | #size-cells = <2>; | |
48 | ranges; | |
49 | ||
50 | sdhci0: sdhci@ff160000 { | |
51 | u-boot,dm-pre-reloc; | |
52 | compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; | |
53 | status = "disabled"; | |
d5843f26 ARS |
54 | non-removable; |
55 | bus-width = <8>; | |
2678059e SDPP |
56 | reg = <0x0 0xff160000 0x0 0x1000>; |
57 | clock-names = "clk_xin", "clk_ahb"; | |
d1fb3d02 | 58 | clocks = <&clk_xin &clk_xin>; |
2678059e SDPP |
59 | xlnx,device_id = <0>; |
60 | }; | |
2678059e SDPP |
61 | }; |
62 | }; | |
63 | ||
64 | &dcc { | |
65 | status = "okay"; | |
66 | }; | |
67 | ||
68 | &sdhci0 { | |
69 | status = "okay"; | |
70 | }; |