[J-u-boot.git] / drivers / usb / dwc3 / dwc3-generic.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Generic DWC3 Glue layer
 *
 * Copyright (C) 2016 - 2018 Xilinx, Inc.
 *
 * Based on dwc3-omap.c.
 */

#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dwc3-uboot.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <malloc.h>
#include <usb.h>
#include "core.h"
#include "gadget.h"
#include <reset.h>
#include <clk.h>
#include <usb/xhci.h>

struct dwc3_glue_data {
	struct clk_bulk		clks;
	struct reset_ctl_bulk	resets;
	fdt_addr_t regs;
};

struct dwc3_generic_plat {
	fdt_addr_t base;
	u32 maximum_speed;
	enum usb_dr_mode dr_mode;
};

struct dwc3_generic_priv {
	void *base;
	struct dwc3 dwc3;
	struct phy_bulk phys;
};

struct dwc3_generic_host_priv {
	struct xhci_ctrl xhci_ctrl;
	struct dwc3_generic_priv gen_priv;
};

static int dwc3_generic_probe(struct udevice *dev,
			      struct dwc3_generic_priv *priv)
{
	int rc;
	struct dwc3_generic_plat *plat = dev_get_plat(dev);
	struct dwc3 *dwc3 = &priv->dwc3;
	struct dwc3_glue_data *glue = dev_get_plat(dev->parent);

	dwc3->dev = dev;
	dwc3->maximum_speed = plat->maximum_speed;
	dwc3->dr_mode = plat->dr_mode;
#if CONFIG_IS_ENABLED(OF_CONTROL)
	dwc3_of_parse(dwc3);
#endif

	/*
	 * It must hold whole USB3.0 OTG controller in resetting to hold pipe
	 * power state in P2 before initializing TypeC PHY on RK3399 platform.
	 */
	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
		reset_assert_bulk(&glue->resets);
		udelay(1);
	}

	rc = dwc3_setup_phy(dev, &priv->phys);
	if (rc && rc != -ENOTSUPP)
		return rc;

	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
		reset_deassert_bulk(&glue->resets);

	priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
	dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;


	rc =  dwc3_init(dwc3);
	if (rc) {
		unmap_physmem(priv->base, MAP_NOCACHE);
		return rc;
	}

	return 0;
}

static int dwc3_generic_remove(struct udevice *dev,
			       struct dwc3_generic_priv *priv)
{
	struct dwc3 *dwc3 = &priv->dwc3;

	dwc3_remove(dwc3);
	dwc3_shutdown_phy(dev, &priv->phys);
	unmap_physmem(dwc3->regs, MAP_NOCACHE);

	return 0;
}

static int dwc3_generic_of_to_plat(struct udevice *dev)
{
	struct dwc3_generic_plat *plat = dev_get_plat(dev);
	ofnode node = dev->node;

	plat->base = dev_read_addr(dev);

	plat->maximum_speed = usb_get_maximum_speed(node);
	if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
		pr_info("No USB maximum speed specified. Using super speed\n");
		plat->maximum_speed = USB_SPEED_SUPER;
	}

	plat->dr_mode = usb_get_dr_mode(node);
	if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
		pr_err("Invalid usb mode setup\n");
		return -ENODEV;
	}

	return 0;
}

#if CONFIG_IS_ENABLED(DM_USB_GADGET)
int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
	struct dwc3_generic_priv *priv = dev_get_priv(dev);
	struct dwc3 *dwc3 = &priv->dwc3;

	dwc3_gadget_uboot_handle_interrupt(dwc3);

	return 0;
}

static int dwc3_generic_peripheral_probe(struct udevice *dev)
{
	struct dwc3_generic_priv *priv = dev_get_priv(dev);

	return dwc3_generic_probe(dev, priv);
}

static int dwc3_generic_peripheral_remove(struct udevice *dev)
{
	struct dwc3_generic_priv *priv = dev_get_priv(dev);

	return dwc3_generic_remove(dev, priv);
}

U_BOOT_DRIVER(dwc3_generic_peripheral) = {
	.name	= "dwc3-generic-peripheral",
	.id	= UCLASS_USB_GADGET_GENERIC,
	.of_to_plat = dwc3_generic_of_to_plat,
	.probe = dwc3_generic_peripheral_probe,
	.remove = dwc3_generic_peripheral_remove,
	.priv_auto	= sizeof(struct dwc3_generic_priv),
	.plat_auto	= sizeof(struct dwc3_generic_plat),
};
#endif

#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
static int dwc3_generic_host_probe(struct udevice *dev)
{
	struct xhci_hcor *hcor;
	struct xhci_hccr *hccr;
	struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
	int rc;

	rc = dwc3_generic_probe(dev, &priv->gen_priv);
	if (rc)
		return rc;

	hccr = (struct xhci_hccr *)priv->gen_priv.base;
	hcor = (struct xhci_hcor *)(priv->gen_priv.base +
			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));

	return xhci_register(dev, hccr, hcor);
}

static int dwc3_generic_host_remove(struct udevice *dev)
{
	struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
	int rc;

	rc = xhci_deregister(dev);
	if (rc)
		return rc;

	return dwc3_generic_remove(dev, &priv->gen_priv);
}

U_BOOT_DRIVER(dwc3_generic_host) = {
	.name	= "dwc3-generic-host",
	.id	= UCLASS_USB,
	.of_to_plat = dwc3_generic_of_to_plat,
	.probe = dwc3_generic_host_probe,
	.remove = dwc3_generic_host_remove,
	.priv_auto	= sizeof(struct dwc3_generic_host_priv),
	.plat_auto	= sizeof(struct dwc3_generic_plat),
	.ops = &xhci_usb_ops,
	.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif

struct dwc3_glue_ops {
	void (*select_dr_mode)(struct udevice *dev, int index,
			       enum usb_dr_mode mode);
};

void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
			    enum usb_dr_mode mode)
{
#define USBOTGSS_UTMI_OTG_STATUS		0x0084
#define USBOTGSS_UTMI_OTG_OFFSET		0x0480

/* UTMI_OTG_STATUS REGISTER */
#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE	BIT(31)
#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT	BIT(9)
#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
#define USBOTGSS_UTMI_OTG_STATUS_IDDIG		BIT(4)
#define USBOTGSS_UTMI_OTG_STATUS_SESSEND	BIT(3)
#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID	BIT(2)
#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID	BIT(1)
enum dwc3_omap_utmi_mode {
	DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
	DWC3_OMAP_UTMI_MODE_HW,
	DWC3_OMAP_UTMI_MODE_SW,
};

	u32 use_id_pin;
	u32 host_mode;
	u32 reg;
	u32 utmi_mode;
	u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;

	struct dwc3_glue_data *glue = dev_get_plat(dev);
	void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);

	if (device_is_compatible(dev, "ti,am437x-dwc3"))
		utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;

	utmi_mode = dev_read_u32_default(dev, "utmi-mode",
					 DWC3_OMAP_UTMI_MODE_UNKNOWN);
	if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
		debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
		      dev->name);
		mode = USB_DR_MODE_PERIPHERAL;
	}

	switch (mode)  {
	case USB_DR_MODE_PERIPHERAL:
		use_id_pin = 0;
		host_mode = 0;
		break;
	case USB_DR_MODE_HOST:
		use_id_pin = 0;
		host_mode = 1;
		break;
	case USB_DR_MODE_OTG:
	default:
		use_id_pin = 1;
		host_mode = 0;
		break;
	}

	reg = readl(base + utmi_status_offset);

	reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
	if (!use_id_pin)
		reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;

	writel(reg, base + utmi_status_offset);

	reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND |
		USBOTGSS_UTMI_OTG_STATUS_VBUSVALID |
		USBOTGSS_UTMI_OTG_STATUS_IDDIG);

	reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID |
		USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;

	if (!host_mode)
		reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG |
			USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;

	writel(reg, base + utmi_status_offset);

	unmap_physmem(base, MAP_NOCACHE);
}

struct dwc3_glue_ops ti_ops = {
	.select_dr_mode = dwc3_ti_select_dr_mode,
};

static int dwc3_glue_bind(struct udevice *parent)
{
	ofnode node;
	int ret;

	ofnode_for_each_subnode(node, parent->node) {
		const char *name = ofnode_get_name(node);
		enum usb_dr_mode dr_mode;
		struct udevice *dev;
		const char *driver = NULL;

		debug("%s: subnode name: %s\n", __func__, name);

		dr_mode = usb_get_dr_mode(node);

		switch (dr_mode) {
		case USB_DR_MODE_PERIPHERAL:
		case USB_DR_MODE_OTG:
#if CONFIG_IS_ENABLED(DM_USB_GADGET)
			debug("%s: dr_mode: OTG or Peripheral\n", __func__);
			driver = "dwc3-generic-peripheral";
#endif
			break;
#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
		case USB_DR_MODE_HOST:
			debug("%s: dr_mode: HOST\n", __func__);
			driver = "dwc3-generic-host";
			break;
#endif
		default:
			debug("%s: unsupported dr_mode\n", __func__);
			return -ENODEV;
		};

		if (!driver)
			continue;

		ret = device_bind_driver_to_node(parent, driver, name,
						 node, &dev);
		if (ret) {
			debug("%s: not able to bind usb device mode\n",
			      __func__);
			return ret;
		}
	}

	return 0;
}

static int dwc3_glue_reset_init(struct udevice *dev,
				struct dwc3_glue_data *glue)
{
	int ret;

	ret = reset_get_bulk(dev, &glue->resets);
	if (ret == -ENOTSUPP || ret == -ENOENT)
		return 0;
	else if (ret)
		return ret;

	ret = reset_deassert_bulk(&glue->resets);
	if (ret) {
		reset_release_bulk(&glue->resets);
		return ret;
	}

	return 0;
}

static int dwc3_glue_clk_init(struct udevice *dev,
			      struct dwc3_glue_data *glue)
{
	int ret;

	ret = clk_get_bulk(dev, &glue->clks);
	if (ret == -ENOSYS || ret == -ENOENT)
		return 0;
	if (ret)
		return ret;

#if CONFIG_IS_ENABLED(CLK)
	ret = clk_enable_bulk(&glue->clks);
	if (ret) {
		clk_release_bulk(&glue->clks);
		return ret;
	}
#endif

	return 0;
}

static int dwc3_glue_probe(struct udevice *dev)
{
	struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev);
	struct dwc3_glue_data *glue = dev_get_plat(dev);
	struct udevice *child = NULL;
	int index = 0;
	int ret;

	glue->regs = dev_read_addr(dev);

	ret = dwc3_glue_clk_init(dev, glue);
	if (ret)
		return ret;

	ret = dwc3_glue_reset_init(dev, glue);
	if (ret)
		return ret;

	ret = device_find_first_child(dev, &child);
	if (ret)
		return ret;

	if (glue->resets.count == 0) {
		ret = dwc3_glue_reset_init(child, glue);
		if (ret)
			return ret;
	}

	while (child) {
		enum usb_dr_mode dr_mode;

		dr_mode = usb_get_dr_mode(child->node);
		device_find_next_child(&child);
		if (ops && ops->select_dr_mode)
			ops->select_dr_mode(dev, index, dr_mode);
		index++;
	}

	return 0;
}

static int dwc3_glue_remove(struct udevice *dev)
{
	struct dwc3_glue_data *glue = dev_get_plat(dev);

	reset_release_bulk(&glue->resets);

	clk_release_bulk(&glue->clks);

	return 0;
}

static const struct udevice_id dwc3_glue_ids[] = {
	{ .compatible = "xlnx,zynqmp-dwc3" },
	{ .compatible = "xlnx,versal-dwc3" },
	{ .compatible = "ti,keystone-dwc3"},
	{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
	{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
	{ .compatible = "ti,am654-dwc3" },
	{ .compatible = "rockchip,rk3328-dwc3" },
	{ .compatible = "rockchip,rk3399-dwc3" },
	{ .compatible = "qcom,dwc3" },
	{ }
};

U_BOOT_DRIVER(dwc3_generic_wrapper) = {
	.name	= "dwc3-generic-wrapper",
	.id	= UCLASS_NOP,
	.of_match = dwc3_glue_ids,
	.bind = dwc3_glue_bind,
	.probe = dwc3_glue_probe,
	.remove = dwc3_glue_remove,
	.plat_auto	= sizeof(struct dwc3_glue_data),

};
Commit	Line	Data
22929e12	1	// SPDX-License-Identifier: GPL-2.0
49d67454 MS	2	/*
	3	* Generic DWC3 Glue layer
	4	*
	5	* Copyright (C) 2016 - 2018 Xilinx, Inc.
	6	*
	7	* Based on dwc3-omap.c.
	8	*/
	9
	10	#include <common.h>
1eb69ae4	11	#include <cpu_func.h>
f7ae49fc	12	#include <log.h>
49d67454 MS	13	#include <dm.h>
	14	#include <dm/device-internal.h>
	15	#include <dm/lists.h>
446e3a20	16	#include <dwc3-uboot.h>
cd93d625	17	#include <linux/bitops.h>
5d422ab2	18	#include <linux/delay.h>
49d67454 MS	19	#include <linux/usb/ch9.h>
	20	#include <linux/usb/gadget.h>
	21	#include <malloc.h>
	22	#include <usb.h>
	23	#include "core.h"
	24	#include "gadget.h"
446e3a20 JJH	25	#include <reset.h>
446e3a20 JJH	26	#include <clk.h>
b575e909	27	#include <usb/xhci.h>
49d67454	28
5d422ab2 FW	29	struct dwc3_glue_data {
	30	struct clk_bulk clks;
	31	struct reset_ctl_bulk resets;
	32	fdt_addr_t regs;
	33	};
	34
3a38a0ad JJH	35	struct dwc3_generic_plat {
	36	fdt_addr_t base;
	37	u32 maximum_speed;
	38	enum usb_dr_mode dr_mode;
	39	};
	40
3a38a0ad	41	struct dwc3_generic_priv {
1af590df	42	void *base;
446e3a20	43	struct dwc3 dwc3;
6dfb8a80	44	struct phy_bulk phys;
446e3a20 JJH	45	};
446e3a20 JJH	46
b575e909 JJH	47	struct dwc3_generic_host_priv {
	48	struct xhci_ctrl xhci_ctrl;
	49	struct dwc3_generic_priv gen_priv;
	50	};
	51
1af590df JJH	52	static int dwc3_generic_probe(struct udevice *dev,
1af590df JJH	53	struct dwc3_generic_priv *priv)
49d67454	54	{
446e3a20	55	int rc;
c69cda25	56	struct dwc3_generic_plat *plat = dev_get_plat(dev);
446e3a20	57	struct dwc3 *dwc3 = &priv->dwc3;
c69cda25	58	struct dwc3_glue_data *glue = dev_get_plat(dev->parent);
446e3a20	59
ba6c5f7a	60	dwc3->dev = dev;
3a38a0ad JJH	61	dwc3->maximum_speed = plat->maximum_speed;
3a38a0ad JJH	62	dwc3->dr_mode = plat->dr_mode;
ba6c5f7a JJH	63	#if CONFIG_IS_ENABLED(OF_CONTROL)
	64	dwc3_of_parse(dwc3);
	65	#endif
3a38a0ad	66
5d422ab2 FW	67	/*
	68	* It must hold whole USB3.0 OTG controller in resetting to hold pipe
	69	* power state in P2 before initializing TypeC PHY on RK3399 platform.
	70	*/
	71	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
	72	reset_assert_bulk(&glue->resets);
	73	udelay(1);
	74	}
	75
6dfb8a80	76	rc = dwc3_setup_phy(dev, &priv->phys);
e7f9e1fc	77	if (rc && rc != -ENOTSUPP)
446e3a20 JJH	78	return rc;
446e3a20 JJH	79
5d422ab2 FW	80	if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
	81	reset_deassert_bulk(&glue->resets);
	82
1af590df JJH	83	priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
1af590df JJH	84	dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
ba6c5f7a	85
446e3a20 JJH	86
	87	rc = dwc3_init(dwc3);
	88	if (rc) {
1af590df	89	unmap_physmem(priv->base, MAP_NOCACHE);
446e3a20 JJH	90	return rc;
446e3a20 JJH	91	}
49d67454	92
446e3a20	93	return 0;
49d67454 MS	94	}
49d67454 MS	95
1af590df JJH	96	static int dwc3_generic_remove(struct udevice *dev,
1af590df JJH	97	struct dwc3_generic_priv *priv)
49d67454	98	{
446e3a20	99	struct dwc3 *dwc3 = &priv->dwc3;
49d67454	100
446e3a20	101	dwc3_remove(dwc3);
6dfb8a80	102	dwc3_shutdown_phy(dev, &priv->phys);
446e3a20	103	unmap_physmem(dwc3->regs, MAP_NOCACHE);
49d67454 MS	104
	105	return 0;
	106	}
	107
d1998a9f	108	static int dwc3_generic_of_to_plat(struct udevice *dev)
49d67454	109	{
c69cda25	110	struct dwc3_generic_plat *plat = dev_get_plat(dev);
ac28e59a	111	ofnode node = dev->node;
49d67454	112
ac28e59a	113	plat->base = dev_read_addr(dev);
49d67454	114
3a38a0ad JJH	115	plat->maximum_speed = usb_get_maximum_speed(node);
3a38a0ad JJH	116	if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
1a63e5e5 JJH	117	pr_info("No USB maximum speed specified. Using super speed\n");
1a63e5e5 JJH	118	plat->maximum_speed = USB_SPEED_SUPER;
49d67454 MS	119	}
49d67454 MS	120
3a38a0ad JJH	121	plat->dr_mode = usb_get_dr_mode(node);
3a38a0ad JJH	122	if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
49d67454 MS	123	pr_err("Invalid usb mode setup\n");
	124	return -ENODEV;
	125	}
	126
	127	return 0;
	128	}
	129
1af590df JJH	130	#if CONFIG_IS_ENABLED(DM_USB_GADGET)
	131	int dm_usb_gadget_handle_interrupts(struct udevice *dev)
	132	{
	133	struct dwc3_generic_priv *priv = dev_get_priv(dev);
	134	struct dwc3 *dwc3 = &priv->dwc3;
	135
	136	dwc3_gadget_uboot_handle_interrupt(dwc3);
	137
	138	return 0;
	139	}
	140
	141	static int dwc3_generic_peripheral_probe(struct udevice *dev)
	142	{
	143	struct dwc3_generic_priv *priv = dev_get_priv(dev);
	144
	145	return dwc3_generic_probe(dev, priv);
	146	}
	147
	148	static int dwc3_generic_peripheral_remove(struct udevice *dev)
	149	{
	150	struct dwc3_generic_priv *priv = dev_get_priv(dev);
	151
	152	return dwc3_generic_remove(dev, priv);
	153	}
	154
49d67454 MS	155	U_BOOT_DRIVER(dwc3_generic_peripheral) = {
49d67454 MS	156	.name = "dwc3-generic-peripheral",
01311624	157	.id = UCLASS_USB_GADGET_GENERIC,
d1998a9f	158	.of_to_plat = dwc3_generic_of_to_plat,
49d67454 MS	159	.probe = dwc3_generic_peripheral_probe,
49d67454 MS	160	.remove = dwc3_generic_peripheral_remove,
41575d8e	161	.priv_auto = sizeof(struct dwc3_generic_priv),
caa4daa2	162	.plat_auto = sizeof(struct dwc3_generic_plat),
49d67454	163	};
687ab545	164	#endif
49d67454	165
b575e909 JJH	166	#if defined(CONFIG_SPL_USB_HOST_SUPPORT) \|\| !defined(CONFIG_SPL_BUILD)
	167	static int dwc3_generic_host_probe(struct udevice *dev)
	168	{
	169	struct xhci_hcor *hcor;
	170	struct xhci_hccr *hccr;
	171	struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
	172	int rc;
	173
	174	rc = dwc3_generic_probe(dev, &priv->gen_priv);
	175	if (rc)
	176	return rc;
	177
	178	hccr = (struct xhci_hccr *)priv->gen_priv.base;
	179	hcor = (struct xhci_hcor *)(priv->gen_priv.base +
	180	HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
	181
	182	return xhci_register(dev, hccr, hcor);
	183	}
	184
	185	static int dwc3_generic_host_remove(struct udevice *dev)
	186	{
	187	struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
	188	int rc;
	189
	190	rc = xhci_deregister(dev);
	191	if (rc)
	192	return rc;
	193
	194	return dwc3_generic_remove(dev, &priv->gen_priv);
	195	}
	196
	197	U_BOOT_DRIVER(dwc3_generic_host) = {
	198	.name = "dwc3-generic-host",
	199	.id = UCLASS_USB,
d1998a9f	200	.of_to_plat = dwc3_generic_of_to_plat,
b575e909 JJH	201	.probe = dwc3_generic_host_probe,
b575e909 JJH	202	.remove = dwc3_generic_host_remove,
41575d8e	203	.priv_auto = sizeof(struct dwc3_generic_host_priv),
caa4daa2	204	.plat_auto = sizeof(struct dwc3_generic_plat),
b575e909 JJH	205	.ops = &xhci_usb_ops,
	206	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	207	};
	208	#endif
	209
93991cf1 JJH	210	struct dwc3_glue_ops {
	211	void (select_dr_mode)(struct udevice dev, int index,
	212	enum usb_dr_mode mode);
446e3a20 JJH	213	};
446e3a20 JJH	214
d66e54ac JJH	215	void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
	216	enum usb_dr_mode mode)
	217	{
	218	#define USBOTGSS_UTMI_OTG_STATUS 0x0084
	219	#define USBOTGSS_UTMI_OTG_OFFSET 0x0480
	220
	221	/* UTMI_OTG_STATUS REGISTER */
	222	#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE BIT(31)
	223	#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT BIT(9)
	224	#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
	225	#define USBOTGSS_UTMI_OTG_STATUS_IDDIG BIT(4)
	226	#define USBOTGSS_UTMI_OTG_STATUS_SESSEND BIT(3)
	227	#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID BIT(2)
	228	#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID BIT(1)
	229	enum dwc3_omap_utmi_mode {
	230	DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
	231	DWC3_OMAP_UTMI_MODE_HW,
	232	DWC3_OMAP_UTMI_MODE_SW,
	233	};
	234
	235	u32 use_id_pin;
	236	u32 host_mode;
	237	u32 reg;
	238	u32 utmi_mode;
	239	u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
	240
c69cda25	241	struct dwc3_glue_data *glue = dev_get_plat(dev);
d66e54ac JJH	242	void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
	243
	244	if (device_is_compatible(dev, "ti,am437x-dwc3"))
	245	utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;
	246
	247	utmi_mode = dev_read_u32_default(dev, "utmi-mode",
	248	DWC3_OMAP_UTMI_MODE_UNKNOWN);
	249	if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
	250	debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
	251	dev->name);
	252	mode = USB_DR_MODE_PERIPHERAL;
	253	}
	254
	255	switch (mode) {
	256	case USB_DR_MODE_PERIPHERAL:
	257	use_id_pin = 0;
	258	host_mode = 0;
	259	break;
	260	case USB_DR_MODE_HOST:
	261	use_id_pin = 0;
	262	host_mode = 1;
	263	break;
	264	case USB_DR_MODE_OTG:
	265	default:
	266	use_id_pin = 1;
	267	host_mode = 0;
	268	break;
	269	}
	270
	271	reg = readl(base + utmi_status_offset);
	272
	273	reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
	274	if (!use_id_pin)
	275	reg \|= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
	276
	277	writel(reg, base + utmi_status_offset);
	278
	279	reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND \|
	280	USBOTGSS_UTMI_OTG_STATUS_VBUSVALID \|
	281	USBOTGSS_UTMI_OTG_STATUS_IDDIG);
	282
	283	reg \|= USBOTGSS_UTMI_OTG_STATUS_SESSVALID \|
	284	USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
	285
	286	if (!host_mode)
	287	reg \|= USBOTGSS_UTMI_OTG_STATUS_IDDIG \|
	288	USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;
	289
	290	writel(reg, base + utmi_status_offset);
	291
	292	unmap_physmem(base, MAP_NOCACHE);
	293	}
	294
	295	struct dwc3_glue_ops ti_ops = {
	296	.select_dr_mode = dwc3_ti_select_dr_mode,
	297	};
	298
446e3a20	299	static int dwc3_glue_bind(struct udevice *parent)
49d67454	300	{
ac28e59a	301	ofnode node;
49d67454 MS	302	int ret;
49d67454 MS	303
ac28e59a KY	304	ofnode_for_each_subnode(node, parent->node) {
ac28e59a KY	305	const char *name = ofnode_get_name(node);
49d67454 MS	306	enum usb_dr_mode dr_mode;
49d67454 MS	307	struct udevice *dev;
446e3a20	308	const char *driver = NULL;
49d67454 MS	309
49d67454 MS	310	debug("%s: subnode name: %s\n", __func__, name);
49d67454 MS	311
	312	dr_mode = usb_get_dr_mode(node);
	313
	314	switch (dr_mode) {
	315	case USB_DR_MODE_PERIPHERAL:
	316	case USB_DR_MODE_OTG:
446e3a20	317	#if CONFIG_IS_ENABLED(DM_USB_GADGET)
49d67454 MS	318	debug("%s: dr_mode: OTG or Peripheral\n", __func__);
49d67454 MS	319	driver = "dwc3-generic-peripheral";
446e3a20	320	#endif
49d67454	321	break;
b575e909	322	#if defined(CONFIG_SPL_USB_HOST_SUPPORT) \|\| !defined(CONFIG_SPL_BUILD)
49d67454 MS	323	case USB_DR_MODE_HOST:
49d67454 MS	324	debug("%s: dr_mode: HOST\n", __func__);
b575e909	325	driver = "dwc3-generic-host";
49d67454	326	break;
b575e909	327	#endif
49d67454 MS	328	default:
	329	debug("%s: unsupported dr_mode\n", __func__);
	330	return -ENODEV;
	331	};
	332
446e3a20 JJH	333	if (!driver)
	334	continue;
	335
49d67454	336	ret = device_bind_driver_to_node(parent, driver, name,
ac28e59a	337	node, &dev);
49d67454 MS	338	if (ret) {
	339	debug("%s: not able to bind usb device mode\n",
	340	__func__);
	341	return ret;
	342	}
	343	}
	344
	345	return 0;
	346	}
	347
446e3a20 JJH	348	static int dwc3_glue_reset_init(struct udevice *dev,
	349	struct dwc3_glue_data *glue)
	350	{
	351	int ret;
	352
	353	ret = reset_get_bulk(dev, &glue->resets);
d624434f	354	if (ret == -ENOTSUPP \|\| ret == -ENOENT)
446e3a20 JJH	355	return 0;
	356	else if (ret)
	357	return ret;
	358
	359	ret = reset_deassert_bulk(&glue->resets);
	360	if (ret) {
	361	reset_release_bulk(&glue->resets);
	362	return ret;
	363	}
	364
	365	return 0;
	366	}
	367
	368	static int dwc3_glue_clk_init(struct udevice *dev,
	369	struct dwc3_glue_data *glue)
	370	{
	371	int ret;
	372
	373	ret = clk_get_bulk(dev, &glue->clks);
d624434f	374	if (ret == -ENOSYS \|\| ret == -ENOENT)
446e3a20 JJH	375	return 0;
	376	if (ret)
	377	return ret;
	378
	379	#if CONFIG_IS_ENABLED(CLK)
	380	ret = clk_enable_bulk(&glue->clks);
	381	if (ret) {
	382	clk_release_bulk(&glue->clks);
	383	return ret;
	384	}
	385	#endif
	386
	387	return 0;
	388	}
	389
	390	static int dwc3_glue_probe(struct udevice *dev)
	391	{
93991cf1	392	struct dwc3_glue_ops ops = (struct dwc3_glue_ops )dev_get_driver_data(dev);
c69cda25	393	struct dwc3_glue_data *glue = dev_get_plat(dev);
93991cf1 JJH	394	struct udevice *child = NULL;
93991cf1 JJH	395	int index = 0;
446e3a20 JJH	396	int ret;
446e3a20 JJH	397
93991cf1 JJH	398	glue->regs = dev_read_addr(dev);
93991cf1 JJH	399
446e3a20 JJH	400	ret = dwc3_glue_clk_init(dev, glue);
	401	if (ret)
	402	return ret;
	403
	404	ret = dwc3_glue_reset_init(dev, glue);
	405	if (ret)
	406	return ret;
	407
93991cf1 JJH	408	ret = device_find_first_child(dev, &child);
	409	if (ret)
	410	return ret;
	411
5d422ab2 FW	412	if (glue->resets.count == 0) {
	413	ret = dwc3_glue_reset_init(child, glue);
	414	if (ret)
	415	return ret;
	416	}
	417
93991cf1 JJH	418	while (child) {
	419	enum usb_dr_mode dr_mode;
	420
ac28e59a	421	dr_mode = usb_get_dr_mode(child->node);
93991cf1 JJH	422	device_find_next_child(&child);
	423	if (ops && ops->select_dr_mode)
	424	ops->select_dr_mode(dev, index, dr_mode);
	425	index++;
	426	}
	427
446e3a20 JJH	428	return 0;
	429	}
	430
	431	static int dwc3_glue_remove(struct udevice *dev)
	432	{
c69cda25	433	struct dwc3_glue_data *glue = dev_get_plat(dev);
446e3a20 JJH	434
	435	reset_release_bulk(&glue->resets);
	436
	437	clk_release_bulk(&glue->clks);
	438
e445d466	439	return 0;
446e3a20 JJH	440	}
	441
	442	static const struct udevice_id dwc3_glue_ids[] = {
49d67454	443	{ .compatible = "xlnx,zynqmp-dwc3" },
648856ac	444	{ .compatible = "xlnx,versal-dwc3" },
1c03ade3	445	{ .compatible = "ti,keystone-dwc3"},
d66e54ac	446	{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
1ce5f1f9	447	{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
cab4e275	448	{ .compatible = "ti,am654-dwc3" },
5d422ab2 FW	449	{ .compatible = "rockchip,rk3328-dwc3" },
5d422ab2 FW	450	{ .compatible = "rockchip,rk3399-dwc3" },
74a703a8	451	{ .compatible = "qcom,dwc3" },
49d67454 MS	452	{ }
	453	};
	454
	455	U_BOOT_DRIVER(dwc3_generic_wrapper) = {
	456	.name = "dwc3-generic-wrapper",
3b83829e	457	.id = UCLASS_NOP,
446e3a20 JJH	458	.of_match = dwc3_glue_ids,
	459	.bind = dwc3_glue_bind,
	460	.probe = dwc3_glue_probe,
	461	.remove = dwc3_glue_remove,
caa4daa2	462	.plat_auto = sizeof(struct dwc3_glue_data),
446e3a20	463
49d67454	464	};