[J-u-boot.git] / include / configs / microblaze-generic.h

/*
 * (C) Copyright 2007-2010 Michal Simek
 *
 * Michal SIMEK <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/microblaze-generic/xparameters.h"

/* MicroBlaze CPU */
#define	CONFIG_MICROBLAZE	1
#define	MICROBLAZE_V5		1

/* Open Firmware DTS */
#define CONFIG_OF_CONTROL	1
#define CONFIG_OF_EMBED		1
#define CONFIG_DEFAULT_DEVICE_TREE microblaze

/* linear and spi flash memory */
#ifdef XILINX_FLASH_START
#define	FLASH
#undef	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#ifdef XILINX_SPI_FLASH_BASEADDR
#undef	FLASH
#define	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#undef	FLASH
#undef	SPIFLASH
#define	RAMENV	/* hold environment in RAM */
#endif
#endif

/* uart */
#ifdef XILINX_UARTLITE_BASEADDR
# define CONFIG_XILINX_UARTLITE
# define CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
# define CONFIG_BAUDRATE	XILINX_UARTLITE_BAUDRATE
# define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
# define CONSOLE_ARG	"console=console=ttyUL0,115200\0"
#elif XILINX_UART16550_BASEADDR
# define CONFIG_SYS_NS16550		1
# define CONFIG_SYS_NS16550_SERIAL
# if defined(__MICROBLAZEEL__)
#  define CONFIG_SYS_NS16550_REG_SIZE	-4
# else
#  define CONFIG_SYS_NS16550_REG_SIZE	4
# endif
# define CONFIG_CONS_INDEX		1
# define CONFIG_SYS_NS16550_COM1 \
		((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
# define CONFIG_SYS_NS16550_CLK	XILINX_UART16550_CLOCK_HZ
# define CONFIG_BAUDRATE	115200

/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
# define CONSOLE_ARG	"console=console=ttyS0,115200\0"
#else
# error Undefined uart
#endif

/* setting reset address */
/*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/

/* ethernet */
#undef CONFIG_SYS_ENET
#if defined(XILINX_EMACLITE_BASEADDR)
# define CONFIG_XILINX_EMACLITE	1
# define CONFIG_SYS_ENET
#endif
#if defined(XILINX_LLTEMAC_BASEADDR)
# define CONFIG_XILINX_LL_TEMAC	1
# define CONFIG_SYS_ENET
#endif
#if defined(XILINX_AXIEMAC_BASEADDR)
# define CONFIG_XILINX_AXIEMAC	1
# define CONFIG_SYS_ENET
#endif

#undef ET_DEBUG

/* gpio */
#ifdef XILINX_GPIO_BASEADDR
# define CONFIG_SYS_GPIO_0		1
# define CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
#endif

/* interrupt controller */
#ifdef XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_ADDR		XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
#endif

/* timer */
#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
#  define CONFIG_SYS_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
#  define CONFIG_SYS_TIMER_0_IRQ	XILINX_TIMER_IRQ
#endif

/* FSL */
/* #define	CONFIG_SYS_FSL_2 */
/* #define	FSL_INTR_2	1 */

/*
 * memory layout - Example
 * CONFIG_SYS_TEXT_BASE = 0x1200_0000;	defined in config.mk
 * CONFIG_SYS_SRAM_BASE = 0x1000_0000;
 * CONFIG_SYS_SRAM_SIZE = 0x0400_0000;	64MB
 *
 * CONFIG_SYS_MONITOR_LEN = 0x40000
 * CONFIG_SYS_MALLOC_LEN = 3 * CONFIG_SYS_MONITOR_LEN = 0xC0000
 *
 * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
 * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - CONFIG_SYS_MONITOR_LEN = 0x13FB_F000
 * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - CONFIG_SYS_MALLOC_LEN = 0x13EF_F000
 *
 * 0x1000_0000	CONFIG_SYS_SDRAM_BASE
 *					MEMTEST_AREA	 64kB
 *					FREE
 * 0x1200_0000	CONFIG_SYS_TEXT_BASE
 *		U-BOOT code
 * 0x1202_0000
 *					FREE
 *
 *					STACK
 * 0x13EF_F000	CONFIG_SYS_MALLOC_BASE
 *					MALLOC_AREA	768kB	Alloc
 * 0x13FB_F000	CONFIG_SYS_MONITOR_BASE
 *					MONITOR_CODE	256kB	Env
 * 0x13FF_F000	CONFIG_SYS_GBL_DATA_OFFSET
 *					GLOBAL_DATA	4kB	bd, gd
 * 0x1400_0000	CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
 */

/* ddr sdram - main memory */
#define	CONFIG_SYS_SDRAM_BASE		XILINX_RAM_START
#define	CONFIG_SYS_SDRAM_SIZE		XILINX_RAM_SIZE
#define	CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)

/* global pointer */
/* start of global data */
#define	CONFIG_SYS_GBL_DATA_OFFSET \
		(CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE)

/* monitor code */
#define	SIZE				0x40000
#define	CONFIG_SYS_MONITOR_LEN		SIZE
#define	CONFIG_SYS_MONITOR_BASE	\
		(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
			- CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
#define	CONFIG_SYS_MONITOR_END \
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define	CONFIG_SYS_MALLOC_LEN		(SIZE * 3)
#define	CONFIG_SYS_MALLOC_BASE \
			(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)

/* stack */
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_MALLOC_BASE

/*
 * CFI flash memory layout - Example
 * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
 *
 * SECT_SIZE = 0x20000;			128kB is one sector
 * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
 *
 * 0x2200_0000	CONFIG_SYS_FLASH_BASE
 *					FREE		256kB
 * 0x2204_0000	CONFIG_ENV_ADDR
 *					ENV_AREA	128kB
 * 0x2206_0000
 *					FREE
 * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
 *
 */

#ifdef FLASH
# define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
# define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
# define CONFIG_SYS_FLASH_CFI		1
# define CONFIG_FLASH_CFI_DRIVER	1
/* ?empty sector */
# define CONFIG_SYS_FLASH_EMPTY_INFO	1
/* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_BANKS	1
/* max number of sectors on one chip */
# define CONFIG_SYS_MAX_FLASH_SECT	512
/* hardware flash protection */
# define CONFIG_SYS_FLASH_PROTECTION

# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* FLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_FLASH	1
/* 128K(one sector) for env */
#  define CONFIG_ENV_SECT_SIZE	0x20000
#  define CONFIG_ENV_ADDR \
			(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
#  define CONFIG_ENV_SIZE	0x20000
# endif /* FLASH && !RAMBOOT */
#else /* !FLASH */

#ifdef SPIFLASH
# define CONFIG_SYS_NO_FLASH		1
# define CONFIG_SYS_SPI_BASE		XILINX_SPI_FLASH_BASEADDR
# define CONFIG_XILINX_SPI		1
# define CONFIG_SPI			1
# define CONFIG_SPI_FLASH		1
# define CONFIG_SPI_FLASH_STMICRO	1
# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
# define CONFIG_SF_DEFAULT_SPEED	XILINX_SPI_FLASH_MAX_FREQ
# define CONFIG_SF_DEFAULT_CS		XILINX_SPI_FLASH_CS

# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* SPIFLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_SPI_FLASH	1
#  define CONFIG_ENV_SPI_MODE		SPI_MODE_3
#  define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#  define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
/* 128K(two sectors) for env */
#  define CONFIG_ENV_SECT_SIZE	0x10000
#  define CONFIG_ENV_SIZE	(2 * CONFIG_ENV_SECT_SIZE)
/* Warning: adjust the offset in respect of other flash content and size */
#  define CONFIG_ENV_OFFSET	(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
# endif /* SPIFLASH && !RAMBOOT */
#else /* !SPIFLASH */

/* ENV in RAM */
# define CONFIG_SYS_NO_FLASH	1
# define CONFIG_ENV_IS_NOWHERE	1
# define CONFIG_ENV_SIZE	0x1000
# define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
#endif /* !SPIFLASH */
#endif /* !FLASH */

/* system ace */
#ifdef XILINX_SYSACE_BASEADDR
# define CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
# define SYSTEMACE_CONFIG_FPGA
# define CONFIG_SYS_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
# define CONFIG_SYS_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
# define CONFIG_DOS_PARTITION
#endif

#if defined(XILINX_USE_ICACHE)
# define CONFIG_ICACHE
#else
# undef CONFIG_ICACHE
#endif

#if defined(XILINX_USE_DCACHE)
# define CONFIG_DCACHE
#else
# undef CONFIG_DCACHE
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL
#define CONFIG_CMD_ECHO

#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
# define CONFIG_CMD_CACHE
#else
# undef CONFIG_CMD_CACHE
#endif

#ifndef CONFIG_SYS_ENET
# undef CONFIG_CMD_NET
# undef CONFIG_CMD_NFS
#else
# define CONFIG_CMD_PING
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_TFTPPUT
#endif

#if defined(CONFIG_SYSTEMACE)
# define CONFIG_CMD_EXT2
# define CONFIG_CMD_FAT
#endif

#if defined(FLASH)
# define CONFIG_CMD_ECHO
# define CONFIG_CMD_FLASH
# define CONFIG_CMD_IMLS
# define CONFIG_CMD_JFFS2
# define CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVEENV
#  define CONFIG_CMD_SAVES
# endif

#else
#if defined(SPIFLASH)
# define CONFIG_CMD_SF

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVEENV
#  define CONFIG_CMD_SAVES
# endif
#else
# undef CONFIG_CMD_IMLS
# undef CONFIG_CMD_FLASH
# undef CONFIG_CMD_JFFS2
# undef CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS
#endif
#endif

#if defined(CONFIG_CMD_JFFS2)
# define CONFIG_MTD_PARTITIONS
#endif

#if defined(CONFIG_CMD_UBIFS)
# define CONFIG_CMD_UBI
# define CONFIG_LZO
#endif

#if defined(CONFIG_CMD_UBI)
# define CONFIG_MTD_PARTITIONS
# define CONFIG_RBTREE
#endif

#if defined(CONFIG_MTD_PARTITIONS)
/* MTD partitions */
#define CONFIG_CMD_MTDPARTS	/* mtdparts command line support */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=flash-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=flash-0:256k(u-boot),"\
				"256k(env),3m(kernel),1m(romfs),"\
				"1m(cramfs),-(jffs2)"
#endif

/* Miscellaneous configurable options */
#define	CONFIG_SYS_PROMPT	"U-Boot-mONStR> "
/* size of console buffer */
#define	CONFIG_SYS_CBSIZE	512
 /* print buffer size */
#define	CONFIG_SYS_PBSIZE \
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define	CONFIG_SYS_MAXARGS	15
#define	CONFIG_SYS_LONGHELP
/* default load address */
#define	CONFIG_SYS_LOAD_ADDR	XILINX_RAM_START

#define	CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		XILINX_BOARD_NAME
#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
#define	CONFIG_IPADDR		192.168.0.3
#define	CONFIG_SERVERIP		192.168.0.5
#define	CONFIG_GATEWAYIP	192.168.0.1
#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD

/* architecture dependent code */
#define	CONFIG_SYS_USR_EXCEP	/* user exception */
#define CONFIG_SYS_HZ	1000

#define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"

#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
					"nor0=flash-0\0"\
					"mtdparts=mtdparts=flash-0:"\
					"256k(u-boot),256k(env),3m(kernel),"\
					"1m(romfs),1m(cramfs),-(jffs2)\0"

#define CONFIG_CMDLINE_EDITING

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER

/* Enable flat device tree support */
#define CONFIG_LMB		1
#define CONFIG_FIT		1
#define CONFIG_OF_LIBFDT	1

#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
# define CONFIG_MII		1
# define CONFIG_CMD_MII		1
# define CONFIG_PHY_GIGE	1
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
# define CONFIG_PHYLIB		1
# define CONFIG_PHY_ATHEROS	1
# define CONFIG_PHY_BROADCOM	1
# define CONFIG_PHY_DAVICOM	1
# define CONFIG_PHY_LXT		1
# define CONFIG_PHY_MARVELL	1
# define CONFIG_PHY_MICREL	1
# define CONFIG_PHY_NATSEMI	1
# define CONFIG_PHY_REALTEK	1
# define CONFIG_PHY_VITESSE	1
#else
# undef CONFIG_MII
# undef CONFIG_CMD_MII
# undef CONFIG_PHYLIB
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
76316a31	1	/*
4aecfb16	2	* (C) Copyright 2007-2010 Michal Simek
76316a31	3	*
cb1bc63b	4	* Michal SIMEK <[email protected]>
76316a31 MS	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
52a822ed	28	#include "../board/xilinx/microblaze-generic/xparameters.h"
76316a31	29
4aecfb16 MS	30	/* MicroBlaze CPU */
4aecfb16 MS	31	#define CONFIG_MICROBLAZE 1
1a50f164	32	#define MICROBLAZE_V5 1
76316a31	33
920c3587 SL	34	/* Open Firmware DTS */
	35	#define CONFIG_OF_CONTROL 1
	36	#define CONFIG_OF_EMBED 1
	37	#define CONFIG_DEFAULT_DEVICE_TREE microblaze
	38
bcec8f49	39	/* linear and spi flash memory */
1fe7e8fa SL	40	#ifdef XILINX_FLASH_START
1fe7e8fa SL	41	#define FLASH
bcec8f49	42	#undef SPIFLASH
1fe7e8fa SL	43	#undef RAMENV /* hold environment in flash */
1fe7e8fa SL	44	#else
bcec8f49	45	#ifdef XILINX_SPI_FLASH_BASEADDR
1fe7e8fa	46	#undef FLASH
bcec8f49 SL	47	#define SPIFLASH
	48	#undef RAMENV /* hold environment in flash */
	49	#else
	50	#undef FLASH
	51	#undef SPIFLASH
1fe7e8fa SL	52	#define RAMENV /* hold environment in RAM */
1fe7e8fa SL	53	#endif
bcec8f49	54	#endif
1fe7e8fa	55
76316a31	56	/* uart */
af7ae1a4	57	#ifdef XILINX_UARTLITE_BASEADDR
4aecfb16 MS	58	# define CONFIG_XILINX_UARTLITE
	59	# define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
	60	# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
	61	# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
	62	# define CONSOLE_ARG "console=console=ttyUL0,115200\0"
e7d591e8	63	#elif XILINX_UART16550_BASEADDR
4aecfb16 MS	64	# define CONFIG_SYS_NS16550 1
4aecfb16 MS	65	# define CONFIG_SYS_NS16550_SERIAL
1de55ef1 SL	66	# if defined(__MICROBLAZEEL__)
	67	# define CONFIG_SYS_NS16550_REG_SIZE -4
	68	# else
	69	# define CONFIG_SYS_NS16550_REG_SIZE 4
	70	# endif
4aecfb16 MS	71	# define CONFIG_CONS_INDEX 1
4aecfb16 MS	72	# define CONFIG_SYS_NS16550_COM1 \
1de55ef1	73	((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
4aecfb16 MS	74	# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
	75	# define CONFIG_BAUDRATE 115200
	76
	77	/* The following table includes the supported baudrates */
	78	# define CONFIG_SYS_BAUDRATE_TABLE \
	79	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
	80	# define CONSOLE_ARG "console=console=ttyS0,115200\0"
e7d591e8	81	#else
4aecfb16	82	# error Undefined uart
af7ae1a4	83	#endif
76316a31 MS	84
76316a31 MS	85	/* setting reset address */
14d0a02a	86	/#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE/
76316a31	87
17980495	88	/* ethernet */
1252df06	89	#undef CONFIG_SYS_ENET
8422a35e SL	90	#if defined(XILINX_EMACLITE_BASEADDR)
8422a35e SL	91	# define CONFIG_XILINX_EMACLITE 1
4aecfb16	92	# define CONFIG_SYS_ENET
8422a35e SL	93	#endif
	94	#if defined(XILINX_LLTEMAC_BASEADDR)
	95	# define CONFIG_XILINX_LL_TEMAC 1
4aecfb16	96	# define CONFIG_SYS_ENET
e5845e21	97	#endif
e634138e MS	98	#if defined(XILINX_AXIEMAC_BASEADDR)
	99	# define CONFIG_XILINX_AXIEMAC 1
	100	# define CONFIG_SYS_ENET
	101	#endif
330e5545	102
e5845e21	103	#undef ET_DEBUG
17980495	104
76316a31	105	/* gpio */
4c6a6f02	106	#ifdef XILINX_GPIO_BASEADDR
4aecfb16 MS	107	# define CONFIG_SYS_GPIO_0 1
4aecfb16 MS	108	# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
4c6a6f02	109	#endif
76316a31 MS	110
76316a31 MS	111	/* interrupt controller */
4d49b280	112	#ifdef XILINX_INTC_BASEADDR
4aecfb16 MS	113	# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
4aecfb16 MS	114	# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
4d49b280	115	#endif
76316a31 MS	116
76316a31 MS	117	/* timer */
bcbb046b	118	#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
4aecfb16 MS	119	# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
4aecfb16 MS	120	# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
4d49b280	121	#endif
bcbb046b	122
19bf1fba	123	/* FSL */
6d0f6bcf	124	/* #define CONFIG_SYS_FSL_2 */
188dc16b	125	/* #define FSL_INTR_2 1 */
19bf1fba	126
76316a31 MS	127	/*
76316a31 MS	128	* memory layout - Example
8f371b18	129	* CONFIG_SYS_TEXT_BASE = 0x1200_0000; defined in config.mk
6d0f6bcf	130	* CONFIG_SYS_SRAM_BASE = 0x1000_0000;
8f371b18 SL	131	* CONFIG_SYS_SRAM_SIZE = 0x0400_0000; 64MB
	132	*
	133	* CONFIG_SYS_MONITOR_LEN = 0x40000
	134	* CONFIG_SYS_MALLOC_LEN = 3 * CONFIG_SYS_MONITOR_LEN = 0xC0000
76316a31	135	*
6d0f6bcf	136	* CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
8f371b18 SL	137	* CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - CONFIG_SYS_MONITOR_LEN = 0x13FB_F000
8f371b18 SL	138	* CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - CONFIG_SYS_MALLOC_LEN = 0x13EF_F000
76316a31	139	*
6d0f6bcf	140	* 0x1000_0000 CONFIG_SYS_SDRAM_BASE
8f371b18	141	* MEMTEST_AREA 64kB
76316a31	142	* FREE
14d0a02a	143	* 0x1200_0000 CONFIG_SYS_TEXT_BASE
76316a31 MS	144	* U-BOOT code
	145	* 0x1202_0000
	146	* FREE
	147	*
	148	* STACK
8f371b18 SL	149	* 0x13EF_F000 CONFIG_SYS_MALLOC_BASE
	150	* MALLOC_AREA 768kB Alloc
	151	* 0x13FB_F000 CONFIG_SYS_MONITOR_BASE
17980495	152	* MONITOR_CODE 256kB Env
6d0f6bcf	153	* 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET
853643d8	154	* GLOBAL_DATA 4kB bd, gd
6d0f6bcf	155	* 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
76316a31 MS	156	*/
	157
	158	/* ddr sdram - main memory */
6d0f6bcf JCPV	159	#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
	160	#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
	161	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	162	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
76316a31 MS	163
76316a31 MS	164	/* global pointer */
32556443	165	/* start of global data */
4aecfb16	166	#define CONFIG_SYS_GBL_DATA_OFFSET \
1020286e	167	(CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE)
76316a31 MS	168
76316a31 MS	169	/* monitor code */
4aecfb16	170	#define SIZE 0x40000
1020286e	171	#define CONFIG_SYS_MONITOR_LEN SIZE
4aecfb16	172	#define CONFIG_SYS_MONITOR_BASE \
1020286e MS	173	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
1020286e MS	174	- CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
4aecfb16 MS	175	#define CONFIG_SYS_MONITOR_END \
4aecfb16 MS	176	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
7cfb13a7	177	#define CONFIG_SYS_MALLOC_LEN (SIZE * 3)
4aecfb16 MS	178	#define CONFIG_SYS_MALLOC_BASE \
4aecfb16 MS	179	(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
76316a31 MS	180
76316a31 MS	181	/* stack */
8fe7b29f	182	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE
76316a31	183
8f371b18 SL	184	/*
	185	* CFI flash memory layout - Example
	186	* CONFIG_SYS_FLASH_BASE = 0x2200_0000;
	187	* CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
	188	*
	189	* SECT_SIZE = 0x20000; 128kB is one sector
	190	* CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
	191	*
	192	* 0x2200_0000 CONFIG_SYS_FLASH_BASE
	193	* FREE 256kB
	194	* 0x2204_0000 CONFIG_ENV_ADDR
	195	* ENV_AREA 128kB
	196	* 0x2206_0000
	197	* FREE
	198	* 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
	199	*
	200	*/
	201
76316a31	202	#ifdef FLASH
4aecfb16 MS	203	# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
	204	# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
	205	# define CONFIG_SYS_FLASH_CFI 1
	206	# define CONFIG_FLASH_CFI_DRIVER 1
	207	/* ?empty sector */
	208	# define CONFIG_SYS_FLASH_EMPTY_INFO 1
	209	/* max number of memory banks */
	210	# define CONFIG_SYS_MAX_FLASH_BANKS 1
	211	/* max number of sectors on one chip */
	212	# define CONFIG_SYS_MAX_FLASH_SECT 512
	213	/* hardware flash protection */
	214	# define CONFIG_SYS_FLASH_PROTECTION
	215
	216	# ifdef RAMENV
	217	# define CONFIG_ENV_IS_NOWHERE 1
	218	# define CONFIG_ENV_SIZE 0x1000
	219	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	220
bcec8f49	221	# else /* FLASH && !RAMENV */
4aecfb16 MS	222	# define CONFIG_ENV_IS_IN_FLASH 1
	223	/* 128K(one sector) for env */
	224	# define CONFIG_ENV_SECT_SIZE 0x20000
	225	# define CONFIG_ENV_ADDR \
	226	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
	227	# define CONFIG_ENV_SIZE 0x20000
bcec8f49	228	# endif /* FLASH && !RAMBOOT */
76316a31	229	#else /* !FLASH */
bcec8f49 SL	230
	231	#ifdef SPIFLASH
	232	# define CONFIG_SYS_NO_FLASH 1
	233	# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
	234	# define CONFIG_XILINX_SPI 1
	235	# define CONFIG_SPI 1
	236	# define CONFIG_SPI_FLASH 1
	237	# define CONFIG_SPI_FLASH_STMICRO 1
	238	# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	239	# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
	240	# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
	241
	242	# ifdef RAMENV
	243	# define CONFIG_ENV_IS_NOWHERE 1
	244	# define CONFIG_ENV_SIZE 0x1000
	245	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	246
	247	# else /* SPIFLASH && !RAMENV */
	248	# define CONFIG_ENV_IS_IN_SPI_FLASH 1
	249	# define CONFIG_ENV_SPI_MODE SPI_MODE_3
	250	# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	251	# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	252	/* 128K(two sectors) for env */
	253	# define CONFIG_ENV_SECT_SIZE 0x10000
	254	# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
	255	/* Warning: adjust the offset in respect of other flash content and size */
	256	# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
	257	# endif /* SPIFLASH && !RAMBOOT */
	258	#else /* !SPIFLASH */
	259
4aecfb16 MS	260	/* ENV in RAM */
	261	# define CONFIG_SYS_NO_FLASH 1
	262	# define CONFIG_ENV_IS_NOWHERE 1
	263	# define CONFIG_ENV_SIZE 0x1000
	264	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
bcec8f49	265	#endif /* !SPIFLASH */
76316a31 MS	266	#endif /* !FLASH */
76316a31 MS	267
853643d8 MS	268	/* system ace */
853643d8 MS	269	#ifdef XILINX_SYSACE_BASEADDR
4aecfb16 MS	270	# define CONFIG_SYSTEMACE
	271	/* #define DEBUG_SYSTEMACE */
	272	# define SYSTEMACE_CONFIG_FPGA
	273	# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
	274	# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
	275	# define CONFIG_DOS_PARTITION
853643d8 MS	276	#endif
853643d8 MS	277
e9b737de	278	#if defined(XILINX_USE_ICACHE)
4aecfb16	279	# define CONFIG_ICACHE
e9b737de	280	#else
4aecfb16	281	# undef CONFIG_ICACHE
e9b737de MS	282	#endif
	283
	284	#if defined(XILINX_USE_DCACHE)
4aecfb16	285	# define CONFIG_DCACHE
e9b737de	286	#else
4aecfb16	287	# undef CONFIG_DCACHE
e9b737de MS	288	#endif
e9b737de MS	289
079a136c JL	290	/*
	291	* BOOTP options
	292	*/
	293	#define CONFIG_BOOTP_BOOTFILESIZE
	294	#define CONFIG_BOOTP_BOOTPATH
	295	#define CONFIG_BOOTP_GATEWAY
	296	#define CONFIG_BOOTP_HOSTNAME
76316a31	297
5dc11a51 JL	298	/*
	299	* Command line configuration.
	300	*/
	301	#include <config_cmd_default.h>
	302
	303	#define CONFIG_CMD_ASKENV
5dc11a51	304	#define CONFIG_CMD_IRQ
5dc11a51	305	#define CONFIG_CMD_MFSL
330e5545	306	#define CONFIG_CMD_ECHO
4d49b280	307
e9b737de	308	#if defined(CONFIG_DCACHE) \|\| defined(CONFIG_ICACHE)
4aecfb16	309	# define CONFIG_CMD_CACHE
e9b737de	310	#else
4aecfb16	311	# undef CONFIG_CMD_CACHE
e9b737de MS	312	#endif
e9b737de MS	313
6d0f6bcf	314	#ifndef CONFIG_SYS_ENET
4aecfb16	315	# undef CONFIG_CMD_NET
1252df06	316	# undef CONFIG_CMD_NFS
4d49b280	317	#else
4aecfb16 MS	318	# define CONFIG_CMD_PING
4aecfb16 MS	319	# define CONFIG_CMD_DHCP
4eb29cf0	320	# define CONFIG_CMD_TFTPPUT
4d49b280	321	#endif
853643d8 MS	322
853643d8 MS	323	#if defined(CONFIG_SYSTEMACE)
4aecfb16 MS	324	# define CONFIG_CMD_EXT2
4aecfb16 MS	325	# define CONFIG_CMD_FAT
853643d8	326	#endif
5dc11a51 JL	327
5dc11a51 JL	328	#if defined(FLASH)
4aecfb16 MS	329	# define CONFIG_CMD_ECHO
	330	# define CONFIG_CMD_FLASH
	331	# define CONFIG_CMD_IMLS
	332	# define CONFIG_CMD_JFFS2
7cfb13a7 SL	333	# define CONFIG_CMD_UBI
7cfb13a7 SL	334	# undef CONFIG_CMD_UBIFS
4aecfb16	335
bcec8f49 SL	336	# if !defined(RAMENV)
	337	# define CONFIG_CMD_SAVEENV
	338	# define CONFIG_CMD_SAVES
	339	# endif
	340
	341	#else
	342	#if defined(SPIFLASH)
	343	# define CONFIG_CMD_SF
	344
4aecfb16 MS	345	# if !defined(RAMENV)
	346	# define CONFIG_CMD_SAVEENV
	347	# define CONFIG_CMD_SAVES
	348	# endif
853643d8	349	#else
4aecfb16 MS	350	# undef CONFIG_CMD_IMLS
	351	# undef CONFIG_CMD_FLASH
	352	# undef CONFIG_CMD_JFFS2
2cce2d32 SL	353	# undef CONFIG_CMD_UBI
2cce2d32 SL	354	# undef CONFIG_CMD_UBIFS
5dc11a51	355	#endif
bcec8f49	356	#endif
76316a31	357
5dc11a51	358	#if defined(CONFIG_CMD_JFFS2)
7cfb13a7 SL	359	# define CONFIG_MTD_PARTITIONS
	360	#endif
	361
	362	#if defined(CONFIG_CMD_UBIFS)
	363	# define CONFIG_CMD_UBI
	364	# define CONFIG_LZO
	365	#endif
	366
	367	#if defined(CONFIG_CMD_UBI)
	368	# define CONFIG_MTD_PARTITIONS
	369	# define CONFIG_RBTREE
	370	#endif
	371
	372	#if defined(CONFIG_MTD_PARTITIONS)
	373	/* MTD partitions */
68d7d651	374	#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
942556a9 SR	375	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	376	#define CONFIG_FLASH_CFI_MTD
c82a541d	377	#define MTDIDS_DEFAULT "nor0=flash-0"
144876a3 MS	378
144876a3 MS	379	/* default mtd partition table */
c82a541d	380	#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
144876a3 MS	381	"256k(env),3m(kernel),1m(romfs),"\
	382	"1m(cramfs),-(jffs2)"
	383	#endif
	384
76316a31	385	/* Miscellaneous configurable options */
6d0f6bcf	386	#define CONFIG_SYS_PROMPT "U-Boot-mONStR> "
4aecfb16 MS	387	/* size of console buffer */
	388	#define CONFIG_SYS_CBSIZE 512
	389	/* print buffer size */
	390	#define CONFIG_SYS_PBSIZE \
	391	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	392	/* max number of command args */
	393	#define CONFIG_SYS_MAXARGS 15
6d0f6bcf	394	#define CONFIG_SYS_LONGHELP
4aecfb16 MS	395	/* default load address */
4aecfb16 MS	396	#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
76316a31	397
330e5545	398	#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
76316a31	399	#define CONFIG_BOOTARGS "root=romfs"
330e5545	400	#define CONFIG_HOSTNAME XILINX_BOARD_NAME
853643d8	401	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
76316a31	402	#define CONFIG_IPADDR 192.168.0.3
853643d8 MS	403	#define CONFIG_SERVERIP 192.168.0.5
853643d8 MS	404	#define CONFIG_GATEWAYIP 192.168.0.1
76316a31 MS	405	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
	406
	407	/* architecture dependent code */
6d0f6bcf JCPV	408	#define CONFIG_SYS_USR_EXCEP /* user exception */
6d0f6bcf JCPV	409	#define CONFIG_SYS_HZ 1000
76316a31	410
0900bee9	411	#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
144876a3	412
4aecfb16	413	#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
c82a541d SL	414	"nor0=flash-0\0"\
c82a541d SL	415	"mtdparts=mtdparts=flash-0:"\
144876a3 MS	416	"256k(u-boot),256k(env),3m(kernel),"\
	417	"1m(romfs),1m(cramfs),-(jffs2)\0"
	418
188dc16b	419	#define CONFIG_CMDLINE_EDITING
188dc16b	420
0900bee9 MS	421	/* Use the HUSH parser */
0900bee9 MS	422	#define CONFIG_SYS_HUSH_PARSER
0900bee9	423
37e892d9 MS	424	/* Enable flat device tree support */
	425	#define CONFIG_LMB 1
	426	#define CONFIG_FIT 1
	427	#define CONFIG_OF_LIBFDT 1
	428
8422a35e	429	#if defined(CONFIG_XILINX_LL_TEMAC) \|\| defined(CONFIG_XILINX_AXIEMAC)
f5e5e1ff SL	430	# define CONFIG_MII 1
	431	# define CONFIG_CMD_MII 1
	432	# define CONFIG_PHY_GIGE 1
	433	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
	434	# define CONFIG_PHYLIB 1
	435	# define CONFIG_PHY_ATHEROS 1
	436	# define CONFIG_PHY_BROADCOM 1
	437	# define CONFIG_PHY_DAVICOM 1
	438	# define CONFIG_PHY_LXT 1
	439	# define CONFIG_PHY_MARVELL 1
	440	# define CONFIG_PHY_MICREL 1
	441	# define CONFIG_PHY_NATSEMI 1
	442	# define CONFIG_PHY_REALTEK 1
	443	# define CONFIG_PHY_VITESSE 1
	444	#else
	445	# undef CONFIG_MII
	446	# undef CONFIG_CMD_MII
	447	# undef CONFIG_PHYLIB
	448	#endif
	449
76316a31	450	#endif /* __CONFIG_H */