[J-u-boot.git] / include / configs / ml401.h

/*
 * (C) Copyright 2007-2008 Michal Simek
 *
 * Michal SIMEK <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/ml401/xparameters.h"

#define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
#define	MICROBLAZE_V5		1
#define	CONFIG_ML401		1	/* ML401 Board */

/* uart */
#ifdef XILINX_UARTLITE_BASEADDR
#define	CONFIG_XILINX_UARTLITE
#define	CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
#define	CONFIG_BAUDRATE		XILINX_UARTLITE_BAUDRATE
#define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
#else
#ifdef XILINX_UART16550_BASEADDR
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	4
#define CONFIG_CONS_INDEX	1
#define CFG_NS16550_COM1	XILINX_UART16550_BASEADDR
#define CFG_NS16550_CLK		XILINX_UART16550_CLOCK_HZ
#define	CONFIG_BAUDRATE		115200
#define	CFG_BAUDRATE_TABLE	{ 9600, 115200 }
#endif
#endif

/* setting reset address */
/*#define	CFG_RESET_ADDRESS	TEXT_BASE*/

/* ethernet */
#ifdef XILINX_EMAC_BASEADDR
#define CONFIG_XILINX_EMAC	1
#else
#ifdef XILINX_EMACLITE_BASEADDR
#define CONFIG_XILINX_EMACLITE	1
#endif
#endif
#undef ET_DEBUG

/* gpio */
#ifdef XILINX_GPIO_BASEADDR
#define	CFG_GPIO_0		1
#define	CFG_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
#endif

/* interrupt controller */
#define	CFG_INTC_0		1
#define	CFG_INTC_0_ADDR		XILINX_INTC_BASEADDR
#define	CFG_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS

/* timer */
#define	CFG_TIMER_0		1
#define	CFG_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
#define	CFG_TIMER_0_IRQ		XILINX_TIMER_IRQ
#define	FREQUENCE		XILINX_CLOCK_FREQ
#define	CFG_TIMER_0_PRELOAD	( FREQUENCE/1000 )
#define	CONFIG_XILINX_CLOCK_FREQ	XILINX_CLOCK_FREQ

/* FSL */
/* #define	CFG_FSL_2 */
/* #define	FSL_INTR_2	1 */

/*
 * memory layout - Example
 * TEXT_BASE = 0x1200_0000;
 * CFG_SRAM_BASE = 0x1000_0000;
 * CFG_SRAM_SIZE = 0x0400_0000;
 *
 * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
 * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
 * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
 *
 * 0x1000_0000	CFG_SDRAM_BASE
 *					FREE
 * 0x1200_0000	TEXT_BASE
 *		U-BOOT code
 * 0x1202_0000
 *					FREE
 *
 *					STACK
 * 0x13F7_F000	CFG_MALLOC_BASE
 *					MALLOC_AREA	256kB	Alloc
 * 0x11FB_F000	CFG_MONITOR_BASE
 *					MONITOR_CODE	256kB	Env
 * 0x13FF_F000	CFG_GBL_DATA_OFFSET
 *					GLOBAL_DATA	4kB	bd, gd
 * 0x1400_0000	CFG_SDRAM_BASE + CFG_SDRAM_SIZE
 */

/* ddr sdram - main memory */
#define	CFG_SDRAM_BASE		XILINX_RAM_START
#define	CFG_SDRAM_SIZE		XILINX_RAM_SIZE
#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
#define	CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0x1000)

/* global pointer */
#define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
/* start of global data */
#define	CFG_GBL_DATA_OFFSET	(CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)

/* monitor code */
#define	SIZE			0x40000
#define	CFG_MONITOR_LEN		SIZE
#define	CFG_MONITOR_BASE	(CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
#define	CFG_MONITOR_END		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define	CFG_MALLOC_LEN		SIZE
#define	CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)

/* stack */
#define	CFG_INIT_SP_OFFSET	CFG_MONITOR_BASE

/*#define	RAMENV */
#define	FLASH

#ifdef FLASH
	#define	CFG_FLASH_BASE		XILINX_FLASH_START
	#define	CFG_FLASH_SIZE		XILINX_FLASH_SIZE
	#define	CFG_FLASH_CFI		1
	#define	CFG_FLASH_CFI_DRIVER	1
	#define	CFG_FLASH_EMPTY_INFO	1	/* ?empty sector */
	#define	CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
	#define	CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
	#define	CFG_FLASH_PROTECTION		/* hardware flash protection */

	#ifdef	RAMENV
		#define	CFG_ENV_IS_NOWHERE	1
		#define	CFG_ENV_SIZE		0x1000
		#define	CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SIZE)

	#else	/* !RAMENV */
		#define	CFG_ENV_IS_IN_FLASH	1
		#define	CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
		#define	CFG_ENV_ADDR		(CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE))
		#define	CFG_ENV_SIZE		0x40000
	#endif /* !RAMBOOT */
#else /* !FLASH */
	/* ENV in RAM */
	#define	CFG_NO_FLASH		1
	#define	CFG_ENV_IS_NOWHERE	1
	#define	CFG_ENV_SIZE		0x1000
	#define	CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SIZE)
	#define	CFG_FLASH_PROTECTION		/* hardware flash protection */
#endif /* !FLASH */

/* system ace */
#ifdef XILINX_SYSACE_BASEADDR
	#define	CONFIG_SYSTEMACE
	/* #define DEBUG_SYSTEMACE */
	#define	SYSTEMACE_CONFIG_FPGA
	#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
	#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
	#define	CONFIG_DOS_PARTITION
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL
#define CONFIG_CMD_PING

#if defined(CONFIG_SYSTEMACE)
	#define CONFIG_CMD_EXT2
	#define CONFIG_CMD_FAT
#endif

#if defined(FLASH)
	#define CONFIG_CMD_ECHO
	#define CONFIG_CMD_FLASH
	#define CONFIG_CMD_IMLS
	#define CONFIG_CMD_JFFS2

	#if !defined(RAMENV)
		#define CONFIG_CMD_ENV
		#define CONFIG_CMD_SAVES
	#endif
#else
	#undef CONFIG_CMD_FLASH
#endif

#if defined(CONFIG_CMD_JFFS2)
/* JFFS2 partitions */
#define CONFIG_JFFS2_CMDLINE	/* mtdparts command line support */
#define MTDIDS_DEFAULT		"nor0=ml401-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=ml401-0:256k(u-boot),"\
				"256k(env),3m(kernel),1m(romfs),"\
				"1m(cramfs),-(jffs2)"
#endif

/* Miscellaneous configurable options */
#define	CFG_PROMPT	"U-Boot-mONStR> "
#define	CFG_CBSIZE	512	/* size of console buffer */
#define	CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
#define	CFG_MAXARGS	15	/* max number of command args */
#define	CFG_LONGHELP
#define	CFG_LOAD_ADDR	0x12000000 /* default load address */

#define	CONFIG_BOOTDELAY	30
#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		"ml401"
#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
#define	CONFIG_IPADDR		192.168.0.3
#define	CONFIG_SERVERIP		192.168.0.5
#define	CONFIG_GATEWAYIP	192.168.0.1
#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD

/* architecture dependent code */
#define	CFG_USR_EXCEP	/* user exception */
#define CFG_HZ	1000

#define	CONFIG_PREBOOT		"echo U-BOOT for ML401;setenv preboot;echo"

#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" /* hardware flash protection */\
					"nor0=ml401-0\0"\
					"mtdparts=mtdparts=ml401-0:"\
					"256k(u-boot),256k(env),3m(kernel),"\
					"1m(romfs),1m(cramfs),-(jffs2)\0"

#define CONFIG_CMDLINE_EDITING
#define CONFIG_OF_LIBFDT	1

#endif	/* __CONFIG_H */
Commit	Line	Data
76316a31	1	/*
188dc16b	2	* (C) Copyright 2007-2008 Michal Simek
76316a31	3	*
cb1bc63b	4	* Michal SIMEK <[email protected]>
76316a31 MS	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	#include "../board/xilinx/ml401/xparameters.h"
	29
	30	#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
1a50f164	31	#define MICROBLAZE_V5 1
76316a31 MS	32	#define CONFIG_ML401 1 /* ML401 Board */
	33
	34	/* uart */
af7ae1a4	35	#ifdef XILINX_UARTLITE_BASEADDR
853643d8	36	#define CONFIG_XILINX_UARTLITE
af7ae1a4 MS	37	#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
af7ae1a4 MS	38	#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
76316a31	39	#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
af7ae1a4 MS	40	#else
	41	#ifdef XILINX_UART16550_BASEADDR
	42	#define CFG_NS16550
	43	#define CFG_NS16550_SERIAL
	44	#define CFG_NS16550_REG_SIZE 4
	45	#define CONFIG_CONS_INDEX 1
	46	#define CFG_NS16550_COM1 XILINX_UART16550_BASEADDR
	47	#define CFG_NS16550_CLK XILINX_UART16550_CLOCK_HZ
	48	#define CONFIG_BAUDRATE 115200
	49	#define CFG_BAUDRATE_TABLE { 9600, 115200 }
	50	#endif
	51	#endif
76316a31 MS	52
76316a31 MS	53	/* setting reset address */
d62f64cc	54	/#define CFG_RESET_ADDRESS TEXT_BASE/
76316a31	55
17980495	56	/* ethernet */
e5845e21 MS	57	#ifdef XILINX_EMAC_BASEADDR
	58	#define CONFIG_XILINX_EMAC 1
	59	#else
	60	#ifdef XILINX_EMACLITE_BASEADDR
	61	#define CONFIG_XILINX_EMACLITE 1
	62	#endif
	63	#endif
	64	#undef ET_DEBUG
17980495	65
76316a31	66	/* gpio */
4c6a6f02	67	#ifdef XILINX_GPIO_BASEADDR
76316a31	68	#define CFG_GPIO_0 1
17980495	69	#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
4c6a6f02	70	#endif
76316a31 MS	71
	72	/* interrupt controller */
	73	#define CFG_INTC_0 1
17980495 MS	74	#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
17980495 MS	75	#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
76316a31 MS	76
	77	/* timer */
	78	#define CFG_TIMER_0 1
17980495 MS	79	#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
	80	#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
	81	#define FREQUENCE XILINX_CLOCK_FREQ
76316a31	82	#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
853643d8	83	#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
76316a31	84
19bf1fba	85	/* FSL */
188dc16b MS	86	/* #define CFG_FSL_2 */
188dc16b MS	87	/* #define FSL_INTR_2 1 */
19bf1fba	88
76316a31 MS	89	/*
	90	* memory layout - Example
	91	* TEXT_BASE = 0x1200_0000;
	92	* CFG_SRAM_BASE = 0x1000_0000;
	93	* CFG_SRAM_SIZE = 0x0400_0000;
	94	*
	95	* CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
	96	* CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
32556443	97	* CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
76316a31 MS	98	*
	99	* 0x1000_0000 CFG_SDRAM_BASE
	100	* FREE
	101	* 0x1200_0000 TEXT_BASE
	102	* U-BOOT code
	103	* 0x1202_0000
	104	* FREE
	105	*
	106	* STACK
17980495 MS	107	* 0x13F7_F000 CFG_MALLOC_BASE
17980495 MS	108	* MALLOC_AREA 256kB Alloc
76316a31	109	* 0x11FB_F000 CFG_MONITOR_BASE
17980495	110	* MONITOR_CODE 256kB Env
76316a31	111	* 0x13FF_F000 CFG_GBL_DATA_OFFSET
853643d8	112	* GLOBAL_DATA 4kB bd, gd
76316a31 MS	113	* 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
	114	*/
	115
	116	/* ddr sdram - main memory */
17980495 MS	117	#define CFG_SDRAM_BASE XILINX_RAM_START
17980495 MS	118	#define CFG_SDRAM_SIZE XILINX_RAM_SIZE
76316a31 MS	119	#define CFG_MEMTEST_START CFG_SDRAM_BASE
	120	#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000)
	121
	122	/* global pointer */
	123	#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
32556443	124	/* start of global data */
853643d8	125	#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
76316a31 MS	126
	127	/* monitor code */
	128	#define SIZE 0x40000
	129	#define CFG_MONITOR_LEN SIZE
	130	#define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
17980495	131	#define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
76316a31	132	#define CFG_MALLOC_LEN SIZE
17980495	133	#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
76316a31 MS	134
	135	/* stack */
	136	#define CFG_INIT_SP_OFFSET CFG_MONITOR_BASE
	137
	138	/#define RAMENV /
	139	#define FLASH
	140
	141	#ifdef FLASH
17980495 MS	142	#define CFG_FLASH_BASE XILINX_FLASH_START
17980495 MS	143	#define CFG_FLASH_SIZE XILINX_FLASH_SIZE
76316a31 MS	144	#define CFG_FLASH_CFI 1
	145	#define CFG_FLASH_CFI_DRIVER 1
	146	#define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */
	147	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	148	#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
144876a3	149	#define CFG_FLASH_PROTECTION /* hardware flash protection */
76316a31 MS	150
	151	#ifdef RAMENV
	152	#define CFG_ENV_IS_NOWHERE 1
	153	#define CFG_ENV_SIZE 0x1000
	154	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
	155
	156	#else /* !RAMENV */
	157	#define CFG_ENV_IS_IN_FLASH 1
76316a31	158	#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
188dc16b MS	159	#define CFG_ENV_ADDR (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE))
188dc16b MS	160	#define CFG_ENV_SIZE 0x40000
76316a31 MS	161	#endif /* !RAMBOOT */
	162	#else /* !FLASH */
	163	/* ENV in RAM */
	164	#define CFG_NO_FLASH 1
	165	#define CFG_ENV_IS_NOWHERE 1
	166	#define CFG_ENV_SIZE 0x1000
	167	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
144876a3	168	#define CFG_FLASH_PROTECTION /* hardware flash protection */
76316a31 MS	169	#endif /* !FLASH */
76316a31 MS	170
853643d8 MS	171	/* system ace */
	172	#ifdef XILINX_SYSACE_BASEADDR
	173	#define CONFIG_SYSTEMACE
	174	/* #define DEBUG_SYSTEMACE */
	175	#define SYSTEMACE_CONFIG_FPGA
	176	#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
	177	#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
	178	#define CONFIG_DOS_PARTITION
	179	#endif
	180
079a136c JL	181	/*
	182	* BOOTP options
	183	*/
	184	#define CONFIG_BOOTP_BOOTFILESIZE
	185	#define CONFIG_BOOTP_BOOTPATH
	186	#define CONFIG_BOOTP_GATEWAY
	187	#define CONFIG_BOOTP_HOSTNAME
76316a31	188
5dc11a51 JL	189	/*
	190	* Command line configuration.
	191	*/
	192	#include <config_cmd_default.h>
	193
	194	#define CONFIG_CMD_ASKENV
5dc11a51	195	#define CONFIG_CMD_CACHE
5dc11a51	196	#define CONFIG_CMD_IRQ
5dc11a51	197	#define CONFIG_CMD_MFSL
5dc11a51	198	#define CONFIG_CMD_PING
853643d8 MS	199
	200	#if defined(CONFIG_SYSTEMACE)
	201	#define CONFIG_CMD_EXT2
	202	#define CONFIG_CMD_FAT
	203	#endif
5dc11a51 JL	204
	205	#if defined(FLASH)
	206	#define CONFIG_CMD_ECHO
	207	#define CONFIG_CMD_FLASH
	208	#define CONFIG_CMD_IMLS
	209	#define CONFIG_CMD_JFFS2
	210
	211	#if !defined(RAMENV)
	212	#define CONFIG_CMD_ENV
	213	#define CONFIG_CMD_SAVES
76316a31	214	#endif
853643d8 MS	215	#else
853643d8 MS	216	#undef CONFIG_CMD_FLASH
5dc11a51	217	#endif
76316a31	218
5dc11a51	219	#if defined(CONFIG_CMD_JFFS2)
144876a3 MS	220	/* JFFS2 partitions */
	221	#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */
	222	#define MTDIDS_DEFAULT "nor0=ml401-0"
	223
	224	/* default mtd partition table */
	225	#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\
	226	"256k(env),3m(kernel),1m(romfs),"\
	227	"1m(cramfs),-(jffs2)"
	228	#endif
	229
76316a31 MS	230	/* Miscellaneous configurable options */
	231	#define CFG_PROMPT "U-Boot-mONStR> "
	232	#define CFG_CBSIZE 512 /* size of console buffer */
	233	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
	234	#define CFG_MAXARGS 15 /* max number of command args */
	235	#define CFG_LONGHELP
	236	#define CFG_LOAD_ADDR 0x12000000 /* default load address */
	237
144876a3	238	#define CONFIG_BOOTDELAY 30
76316a31 MS	239	#define CONFIG_BOOTARGS "root=romfs"
76316a31 MS	240	#define CONFIG_HOSTNAME "ml401"
853643d8	241	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
76316a31	242	#define CONFIG_IPADDR 192.168.0.3
853643d8 MS	243	#define CONFIG_SERVERIP 192.168.0.5
853643d8 MS	244	#define CONFIG_GATEWAYIP 192.168.0.1
76316a31 MS	245	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
	246
	247	/* architecture dependent code */
	248	#define CFG_USR_EXCEP /* user exception */
	249	#define CFG_HZ 1000
	250
144876a3 MS	251	#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo"
	252
	253	#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\
	254	"nor0=ml401-0\0"\
	255	"mtdparts=mtdparts=ml401-0:"\
	256	"256k(u-boot),256k(env),3m(kernel),"\
	257	"1m(romfs),1m(cramfs),-(jffs2)\0"
	258
188dc16b MS	259	#define CONFIG_CMDLINE_EDITING
	260	#define CONFIG_OF_LIBFDT 1
	261
76316a31	262	#endif /* __CONFIG_H */