[J-u-boot.git] / include / tpm-v2.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Defines APIs and structures that allow software to interact with a
 * TPM2 device
 *
 * Copyright (c) 2020 Linaro
 * Copyright (c) 2018 Bootlin
 *
 * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
 *
 * Author: Miquel Raynal <[email protected]>
 */

#ifndef __TPM_V2_H
#define __TPM_V2_H

#include <tpm-common.h>

struct udevice;

#define TPM2_DIGEST_LEN		32

#define TPM2_SHA1_DIGEST_SIZE 20
#define TPM2_SHA256_DIGEST_SIZE	32
#define TPM2_SHA384_DIGEST_SIZE	48
#define TPM2_SHA512_DIGEST_SIZE	64
#define TPM2_SM3_256_DIGEST_SIZE 32

#define TPM2_MAX_PCRS 32
#define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
#define TPM2_MAX_CAP_BUFFER 1024
#define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
				 sizeof(u32)) / sizeof(struct tpms_tagged_property))

#define TPM2_HDR_LEN		10

/*
 *  We deviate from this draft of the specification by increasing the value of
 *  TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
 *  implementations that have enabled a larger than typical number of PCR
 *  banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
 *  in a future revision of the specification.
 */
#define TPM2_NUM_PCR_BANKS 16

/* Definition of (UINT32) TPM2_CAP Constants */
#define TPM2_CAP_PCRS 0x00000005U
#define TPM2_CAP_TPM_PROPERTIES 0x00000006U

/* Definition of (UINT32) TPM2_PT Constants */
#define TPM2_PT_GROUP			(u32)(0x00000100)
#define TPM2_PT_FIXED			(u32)(TPM2_PT_GROUP * 1)
#define TPM2_PT_MANUFACTURER		(u32)(TPM2_PT_FIXED + 5)
#define TPM2_PT_PCR_COUNT		(u32)(TPM2_PT_FIXED + 18)
#define TPM2_PT_MAX_COMMAND_SIZE	(u32)(TPM2_PT_FIXED + 30)
#define TPM2_PT_MAX_RESPONSE_SIZE	(u32)(TPM2_PT_FIXED + 31)

/*
 * event types, cf.
 * "TCG Server Management Domain Firmware Profile Specification",
 * rev 1.00, 2020-05-01
 */
#define EV_POST_CODE			((u32)0x00000001)
#define EV_NO_ACTION			((u32)0x00000003)
#define EV_SEPARATOR			((u32)0x00000004)
#define EV_ACTION			((u32)0x00000005)
#define EV_TAG				((u32)0x00000006)
#define EV_S_CRTM_CONTENTS		((u32)0x00000007)
#define EV_S_CRTM_VERSION		((u32)0x00000008)
#define EV_CPU_MICROCODE		((u32)0x00000009)
#define EV_PLATFORM_CONFIG_FLAGS	((u32)0x0000000A)
#define EV_TABLE_OF_DEVICES		((u32)0x0000000B)
#define EV_COMPACT_HASH			((u32)0x0000000C)

/*
 * event types, cf.
 * "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
 * Level 00 Version 1.05 Revision 23, May 7, 2021
 */
#define EV_EFI_EVENT_BASE			((u32)0x80000000)
#define EV_EFI_VARIABLE_DRIVER_CONFIG		((u32)0x80000001)
#define EV_EFI_VARIABLE_BOOT			((u32)0x80000002)
#define EV_EFI_BOOT_SERVICES_APPLICATION	((u32)0x80000003)
#define EV_EFI_BOOT_SERVICES_DRIVER		((u32)0x80000004)
#define EV_EFI_RUNTIME_SERVICES_DRIVER		((u32)0x80000005)
#define EV_EFI_GPT_EVENT			((u32)0x80000006)
#define EV_EFI_ACTION				((u32)0x80000007)
#define EV_EFI_PLATFORM_FIRMWARE_BLOB		((u32)0x80000008)
#define EV_EFI_HANDOFF_TABLES			((u32)0x80000009)
#define EV_EFI_PLATFORM_FIRMWARE_BLOB2		((u32)0x8000000A)
#define EV_EFI_HANDOFF_TABLES2			((u32)0x8000000B)
#define EV_EFI_VARIABLE_BOOT2			((u32)0x8000000C)
#define EV_EFI_HCRTM_EVENT			((u32)0x80000010)
#define EV_EFI_VARIABLE_AUTHORITY		((u32)0x800000E0)
#define EV_EFI_SPDM_FIRMWARE_BLOB		((u32)0x800000E1)
#define EV_EFI_SPDM_FIRMWARE_CONFIG		((u32)0x800000E2)

#define EFI_CALLING_EFI_APPLICATION         \
	"Calling EFI Application from Boot Option"
#define EFI_RETURNING_FROM_EFI_APPLICATION  \
	"Returning from EFI Application from Boot Option"
#define EFI_EXIT_BOOT_SERVICES_INVOCATION   \
	"Exit Boot Services Invocation"
#define EFI_EXIT_BOOT_SERVICES_FAILED       \
	"Exit Boot Services Returned with Failure"
#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED    \
	"Exit Boot Services Returned with Success"

/* TPMS_TAGGED_PROPERTY Structure */
struct tpms_tagged_property {
	u32 property;
	u32 value;
} __packed;

/* TPMS_PCR_SELECTION Structure */
struct tpms_pcr_selection {
	u16 hash;
	u8 size_of_select;
	u8 pcr_select[TPM2_PCR_SELECT_MAX];
} __packed;

/* TPML_PCR_SELECTION Structure */
struct tpml_pcr_selection {
	u32 count;
	struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
} __packed;

/* TPML_TAGGED_TPM_PROPERTY Structure */
struct tpml_tagged_tpm_property {
	u32 count;
	struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
} __packed;

/* TPMU_CAPABILITIES Union */
union tpmu_capabilities {
	/*
	 * Non exhaustive. Only added the structs needed for our
	 * current code
	 */
	struct tpml_pcr_selection assigned_pcr;
	struct tpml_tagged_tpm_property tpm_properties;
} __packed;

/* TPMS_CAPABILITY_DATA Structure */
struct tpms_capability_data {
	u32 capability;
	union tpmu_capabilities data;
} __packed;

/**
 * SHA1 Event Log Entry Format
 *
 * @pcr_index:	PCRIndex event extended to
 * @event_type:	Type of event (see EFI specs)
 * @digest:	Value extended into PCR index
 * @event_size:	Size of event
 * @event:	Event data
 */
struct tcg_pcr_event {
	u32 pcr_index;
	u32 event_type;
	u8 digest[TPM2_SHA1_DIGEST_SIZE];
	u32 event_size;
	u8 event[];
} __packed;

/**
 * Definition of TPMU_HA Union
 */
union tmpu_ha {
	u8 sha1[TPM2_SHA1_DIGEST_SIZE];
	u8 sha256[TPM2_SHA256_DIGEST_SIZE];
	u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
	u8 sha384[TPM2_SHA384_DIGEST_SIZE];
	u8 sha512[TPM2_SHA512_DIGEST_SIZE];
} __packed;

/**
 * Definition of TPMT_HA Structure
 *
 * @hash_alg:	Hash algorithm defined in enum tpm2_algorithms
 * @digest:	Digest value for a given algorithm
 */
struct tpmt_ha {
	u16 hash_alg;
	union tmpu_ha digest;
} __packed;

/**
 * Definition of TPML_DIGEST_VALUES Structure
 *
 * @count:	Number of algorithms supported by hardware
 * @digests:	struct for algorithm id and hash value
 */
struct tpml_digest_values {
	u32 count;
	struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
} __packed;

/**
 * Crypto Agile Log Entry Format
 *
 * @pcr_index:	PCRIndex event extended to
 * @event_type:	Type of event
 * @digests:	List of digestsextended to PCR index
 * @event_size: Size of the event data
 * @event:	Event data
 */
struct tcg_pcr_event2 {
	u32 pcr_index;
	u32 event_type;
	struct tpml_digest_values digests;
	u32 event_size;
	u8 event[];
} __packed;

/**
 * TPM2 Structure Tags for command/response buffers.
 *
 * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
 * @TPM2_ST_SESSIONS: the command needs an authentication.
 */
enum tpm2_structures {
	TPM2_ST_NO_SESSIONS	= 0x8001,
	TPM2_ST_SESSIONS	= 0x8002,
};

/**
 * TPM2 type of boolean.
 */
enum tpm2_yes_no {
	TPMI_YES		= 1,
	TPMI_NO			= 0,
};

/**
 * TPM2 startup values.
 *
 * @TPM2_SU_CLEAR: reset the internal state.
 * @TPM2_SU_STATE: restore saved state (if any).
 */
enum tpm2_startup_types {
	TPM2_SU_CLEAR		= 0x0000,
	TPM2_SU_STATE		= 0x0001,
};

/**
 * TPM2 permanent handles.
 *
 * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
 * @TPM2_RS_PW: indicates a password.
 * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
 * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
 * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
 */
enum tpm2_handles {
	TPM2_RH_OWNER		= 0x40000001,
	TPM2_RS_PW		= 0x40000009,
	TPM2_RH_LOCKOUT		= 0x4000000A,
	TPM2_RH_ENDORSEMENT	= 0x4000000B,
	TPM2_RH_PLATFORM	= 0x4000000C,
};

/**
 * TPM2 command codes used at the beginning of a buffer, gives the command.
 *
 * @TPM2_CC_STARTUP: TPM2_Startup().
 * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
 * @TPM2_CC_CLEAR: TPM2_Clear().
 * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
 * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
 * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
 * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
 * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
 * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
 * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
 * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
 * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
 * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
 */
enum tpm2_command_codes {
	TPM2_CC_STARTUP		= 0x0144,
	TPM2_CC_SELF_TEST	= 0x0143,
	TPM2_CC_HIER_CONTROL	= 0x0121,
	TPM2_CC_CLEAR		= 0x0126,
	TPM2_CC_CLEARCONTROL	= 0x0127,
	TPM2_CC_HIERCHANGEAUTH	= 0x0129,
	TPM2_CC_NV_DEFINE_SPACE	= 0x012a,
	TPM2_CC_PCR_SETAUTHPOL	= 0x012C,
	TPM2_CC_NV_WRITE	= 0x0137,
	TPM2_CC_NV_WRITELOCK	= 0x0138,
	TPM2_CC_DAM_RESET	= 0x0139,
	TPM2_CC_DAM_PARAMETERS	= 0x013A,
	TPM2_CC_NV_READ         = 0x014E,
	TPM2_CC_GET_CAPABILITY	= 0x017A,
	TPM2_CC_GET_RANDOM      = 0x017B,
	TPM2_CC_PCR_READ	= 0x017E,
	TPM2_CC_PCR_EXTEND	= 0x0182,
	TPM2_CC_PCR_SETAUTHVAL	= 0x0183,
};

/**
 * TPM2 return codes.
 */
enum tpm2_return_codes {
	TPM2_RC_SUCCESS		= 0x0000,
	TPM2_RC_BAD_TAG		= 0x001E,
	TPM2_RC_FMT1		= 0x0080,
	TPM2_RC_HASH		= TPM2_RC_FMT1 + 0x0003,
	TPM2_RC_VALUE		= TPM2_RC_FMT1 + 0x0004,
	TPM2_RC_SIZE		= TPM2_RC_FMT1 + 0x0015,
	TPM2_RC_BAD_AUTH	= TPM2_RC_FMT1 + 0x0022,
	TPM2_RC_HANDLE		= TPM2_RC_FMT1 + 0x000B,
	TPM2_RC_VER1		= 0x0100,
	TPM2_RC_INITIALIZE	= TPM2_RC_VER1 + 0x0000,
	TPM2_RC_FAILURE		= TPM2_RC_VER1 + 0x0001,
	TPM2_RC_DISABLED	= TPM2_RC_VER1 + 0x0020,
	TPM2_RC_AUTH_MISSING	= TPM2_RC_VER1 + 0x0025,
	TPM2_RC_COMMAND_CODE	= TPM2_RC_VER1 + 0x0043,
	TPM2_RC_AUTHSIZE	= TPM2_RC_VER1 + 0x0044,
	TPM2_RC_AUTH_CONTEXT	= TPM2_RC_VER1 + 0x0045,
	TPM2_RC_NV_DEFINED	= TPM2_RC_VER1 + 0x004c,
	TPM2_RC_NEEDS_TEST	= TPM2_RC_VER1 + 0x0053,
	TPM2_RC_WARN		= 0x0900,
	TPM2_RC_TESTING		= TPM2_RC_WARN + 0x000A,
	TPM2_RC_REFERENCE_H0	= TPM2_RC_WARN + 0x0010,
	TPM2_RC_LOCKOUT		= TPM2_RC_WARN + 0x0021,
};

/**
 * TPM2 algorithms.
 */
enum tpm2_algorithms {
	TPM2_ALG_SHA1		= 0x04,
	TPM2_ALG_XOR		= 0x0A,
	TPM2_ALG_SHA256		= 0x0B,
	TPM2_ALG_SHA384		= 0x0C,
	TPM2_ALG_SHA512		= 0x0D,
	TPM2_ALG_NULL		= 0x10,
	TPM2_ALG_SM3_256	= 0x12,
};

/* NV index attributes */
enum tpm_index_attrs {
	TPMA_NV_PPWRITE		= 1UL << 0,
	TPMA_NV_OWNERWRITE	= 1UL << 1,
	TPMA_NV_AUTHWRITE	= 1UL << 2,
	TPMA_NV_POLICYWRITE	= 1UL << 3,
	TPMA_NV_COUNTER		= 1UL << 4,
	TPMA_NV_BITS		= 1UL << 5,
	TPMA_NV_EXTEND		= 1UL << 6,
	TPMA_NV_POLICY_DELETE	= 1UL << 10,
	TPMA_NV_WRITELOCKED	= 1UL << 11,
	TPMA_NV_WRITEALL	= 1UL << 12,
	TPMA_NV_WRITEDEFINE	= 1UL << 13,
	TPMA_NV_WRITE_STCLEAR	= 1UL << 14,
	TPMA_NV_GLOBALLOCK	= 1UL << 15,
	TPMA_NV_PPREAD		= 1UL << 16,
	TPMA_NV_OWNERREAD	= 1UL << 17,
	TPMA_NV_AUTHREAD	= 1UL << 18,
	TPMA_NV_POLICYREAD	= 1UL << 19,
	TPMA_NV_NO_DA		= 1UL << 25,
	TPMA_NV_ORDERLY		= 1UL << 26,
	TPMA_NV_CLEAR_STCLEAR	= 1UL << 27,
	TPMA_NV_READLOCKED	= 1UL << 28,
	TPMA_NV_WRITTEN		= 1UL << 29,
	TPMA_NV_PLATFORMCREATE	= 1UL << 30,
	TPMA_NV_READ_STCLEAR	= 1UL << 31,

	TPMA_NV_MASK_READ	= TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
				TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
	TPMA_NV_MASK_WRITE	= TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
					TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
};

enum {
	TPM_ACCESS_VALID		= 1 << 7,
	TPM_ACCESS_ACTIVE_LOCALITY	= 1 << 5,
	TPM_ACCESS_REQUEST_PENDING	= 1 << 2,
	TPM_ACCESS_REQUEST_USE		= 1 << 1,
	TPM_ACCESS_ESTABLISHMENT	= 1 << 0,
};

enum {
	TPM_STS_FAMILY_SHIFT		= 26,
	TPM_STS_FAMILY_MASK		= 0x3 << TPM_STS_FAMILY_SHIFT,
	TPM_STS_FAMILY_TPM2		= 1 << TPM_STS_FAMILY_SHIFT,
	TPM_STS_RESE_TESTABLISMENT_BIT	= 1 << 25,
	TPM_STS_COMMAND_CANCEL		= 1 << 24,
	TPM_STS_BURST_COUNT_SHIFT	= 8,
	TPM_STS_BURST_COUNT_MASK	= 0xffff << TPM_STS_BURST_COUNT_SHIFT,
	TPM_STS_VALID			= 1 << 7,
	TPM_STS_COMMAND_READY		= 1 << 6,
	TPM_STS_GO			= 1 << 5,
	TPM_STS_DATA_AVAIL		= 1 << 4,
	TPM_STS_DATA_EXPECT		= 1 << 3,
	TPM_STS_SELF_TEST_DONE		= 1 << 2,
	TPM_STS_RESPONSE_RETRY		= 1 << 1,
};

enum {
	TPM_CMD_COUNT_OFFSET	= 2,
	TPM_CMD_ORDINAL_OFFSET	= 6,
	TPM_MAX_BUF_SIZE	= 1260,
};

enum {
	/* Secure storage for firmware settings */
	TPM_HT_PCR = 0,
	TPM_HT_NV_INDEX,
	TPM_HT_HMAC_SESSION,
	TPM_HT_POLICY_SESSION,

	HR_SHIFT		= 24,
	HR_PCR			= TPM_HT_PCR << HR_SHIFT,
	HR_HMAC_SESSION		= TPM_HT_HMAC_SESSION << HR_SHIFT,
	HR_POLICY_SESSION	= TPM_HT_POLICY_SESSION << HR_SHIFT,
	HR_NV_INDEX		= TPM_HT_NV_INDEX << HR_SHIFT,
};

/**
 * Issue a TPM2_Startup command.
 *
 * @dev		TPM device
 * @mode	TPM startup mode
 *
 * @return code of the operation
 */
u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);

/**
 * Issue a TPM2_SelfTest command.
 *
 * @dev		TPM device
 * @full_test	Asking to perform all tests or only the untested ones
 *
 * @return code of the operation
 */
u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);

/**
 * Issue a TPM2_Clear command.
 *
 * @dev		TPM device
 * @handle	Handle
 * @pw		Password
 * @pw_sz	Length of the password
 *
 * @return code of the operation
 */
u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
	       const ssize_t pw_sz);

/**
 * Issue a TPM_NV_DefineSpace command
 *
 * This allows a space to be defined with given attributes and policy
 *
 * @dev			TPM device
 * @space_index		index of the area
 * @space_size		size of area in bytes
 * @nv_attributes	TPM_NV_ATTRIBUTES of the area
 * @nv_policy		policy to use
 * @nv_policy_size	size of the policy
 * @return return code of the operation
 */
u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index,
			 size_t space_size, u32 nv_attributes,
			 const u8 *nv_policy, size_t nv_policy_size);

/**
 * Issue a TPM2_PCR_Extend command.
 *
 * @dev		TPM device
 * @index	Index of the PCR
 * @algorithm	Algorithm used, defined in 'enum tpm2_algorithms'
 * @digest	Value representing the event to be recorded
 * @digest_len  len of the hash
 *
 * @return code of the operation
 */
u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
		    const u8 *digest, u32 digest_len);

/**
 * Read data from the secure storage
 *
 * @dev		TPM device
 * @index	Index of data to read
 * @data	Place to put data
 * @count	Number of bytes of data
 * @return code of the operation
 */
u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count);

/**
 * Write data to the secure storage
 *
 * @dev		TPM device
 * @index	Index of data to write
 * @data	Data to write
 * @count	Number of bytes of data
 * @return code of the operation
 */
u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data,
			u32 count);

/**
 * Issue a TPM2_PCR_Read command.
 *
 * @dev		TPM device
 * @idx		Index of the PCR
 * @idx_min_sz	Minimum size in bytes of the pcrSelect array
 * @data	Output buffer for contents of the named PCR
 * @updates	Optional out parameter: number of updates for this PCR
 *
 * @return code of the operation
 */
u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
		  void *data, unsigned int *updates);

/**
 * Issue a TPM2_GetCapability command.  This implementation is limited
 * to query property index that is 4-byte wide.
 *
 * @dev		TPM device
 * @capability	Partition of capabilities
 * @property	Further definition of capability, limited to be 4 bytes wide
 * @buf		Output buffer for capability information
 * @prop_count	Size of output buffer
 *
 * @return code of the operation
 */
u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
			void *buf, size_t prop_count);

/**
 * Issue a TPM2_DictionaryAttackLockReset command.
 *
 * @dev		TPM device
 * @pw		Password
 * @pw_sz	Length of the password
 *
 * @return code of the operation
 */
u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);

/**
 * Issue a TPM2_DictionaryAttackParameters command.
 *
 * @dev		TPM device
 * @pw		Password
 * @pw_sz	Length of the password
 * @max_tries	Count of authorizations before lockout
 * @recovery_time Time before decrementation of the failure count
 * @lockout_recovery Time to wait after a lockout
 *
 * @return code of the operation
 */
u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
			const ssize_t pw_sz, unsigned int max_tries,
			unsigned int recovery_time,
			unsigned int lockout_recovery);

/**
 * Issue a TPM2_HierarchyChangeAuth command.
 *
 * @dev		TPM device
 * @handle	Handle
 * @newpw	New password
 * @newpw_sz	Length of the new password
 * @oldpw	Old password
 * @oldpw_sz	Length of the old password
 *
 * @return code of the operation
 */
int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
		     const ssize_t newpw_sz, const char *oldpw,
		     const ssize_t oldpw_sz);

/**
 * Issue a TPM_PCR_SetAuthPolicy command.
 *
 * @dev		TPM device
 * @pw		Platform password
 * @pw_sz	Length of the password
 * @index	Index of the PCR
 * @digest	New key to access the PCR
 *
 * @return code of the operation
 */
u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
			   const ssize_t pw_sz, u32 index, const char *key);

/**
 * Issue a TPM_PCR_SetAuthValue command.
 *
 * @dev		TPM device
 * @pw		Platform password
 * @pw_sz	Length of the password
 * @index	Index of the PCR
 * @digest	New key to access the PCR
 * @key_sz	Length of the new key
 *
 * @return code of the operation
 */
u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
			  const ssize_t pw_sz, u32 index, const char *key,
			  const ssize_t key_sz);

/**
 * Issue a TPM2_GetRandom command.
 *
 * @dev		TPM device
 * @param data		output buffer for the random bytes
 * @param count		size of output buffer
 *
 * @return return code of the operation
 */
u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);

/**
 * Lock data in the TPM
 *
 * Once locked the data cannot be written until after a reboot
 *
 * @dev		TPM device
 * @index	Index of data to lock
 * @return code of the operation
 */
u32 tpm2_write_lock(struct udevice *dev, u32 index);

/**
 * Disable access to any platform data
 *
 * This can be called to close off access to the firmware data in the data,
 * before calling the kernel.
 *
 * @dev		TPM device
 * @return code of the operation
 */
u32 tpm2_disable_platform_hierarchy(struct udevice *dev);

/**
 * submit user specified data to the TPM and get response
 *
 * @dev		TPM device
 * @sendbuf:	Buffer of the data to send
 * @recvbuf:	Buffer to save the response to
 * @recv_size:	Pointer to the size of the response buffer
 *
 * @return code of the operation
 */
u32 tpm2_submit_command(struct udevice *dev, const u8 *sendbuf,
			u8 *recvbuf, size_t *recv_size);

#endif /* __TPM_V2_H */
Commit	Line	Data
ff32245b MR	1	/* SPDX-License-Identifier: GPL-2.0+ */
ff32245b MR	2	/*
915e3ae5 IA	3	* Defines APIs and structures that allow software to interact with a
	4	* TPM2 device
	5	*
	6	* Copyright (c) 2020 Linaro
ff32245b	7	* Copyright (c) 2018 Bootlin
915e3ae5 IA	8	*
	9	* https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
	10	*
ff32245b MR	11	* Author: Miquel Raynal <[email protected]>
	12	*/
	13
	14	#ifndef __TPM_V2_H
	15	#define __TPM_V2_H
	16
	17	#include <tpm-common.h>
	18
401d1c4f SG	19	struct udevice;
401d1c4f SG	20
ff32245b MR	21	#define TPM2_DIGEST_LEN 32
ff32245b MR	22
8e0b0871 IA	23	#define TPM2_SHA1_DIGEST_SIZE 20
	24	#define TPM2_SHA256_DIGEST_SIZE 32
	25	#define TPM2_SHA384_DIGEST_SIZE 48
	26	#define TPM2_SHA512_DIGEST_SIZE 64
	27	#define TPM2_SM3_256_DIGEST_SIZE 32
	28
915e3ae5 IA	29	#define TPM2_MAX_PCRS 32
	30	#define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
	31	#define TPM2_MAX_CAP_BUFFER 1024
	32	#define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
	33	sizeof(u32)) / sizeof(struct tpms_tagged_property))
	34
d8f105dd SG	35	#define TPM2_HDR_LEN 10
d8f105dd SG	36
915e3ae5 IA	37	/*
	38	* We deviate from this draft of the specification by increasing the value of
	39	* TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
	40	* implementations that have enabled a larger than typical number of PCR
	41	* banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
	42	* in a future revision of the specification.
	43	*/
	44	#define TPM2_NUM_PCR_BANKS 16
	45
	46	/* Definition of (UINT32) TPM2_CAP Constants */
	47	#define TPM2_CAP_PCRS 0x00000005U
	48	#define TPM2_CAP_TPM_PROPERTIES 0x00000006U
	49
	50	/* Definition of (UINT32) TPM2_PT Constants */
	51	#define TPM2_PT_GROUP (u32)(0x00000100)
	52	#define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
	53	#define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
	54	#define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
	55	#define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
	56	#define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
	57
5b700cdc HS	58	/*
	59	* event types, cf.
	60	* "TCG Server Management Domain Firmware Profile Specification",
	61	* rev 1.00, 2020-05-01
	62	*/
	63	#define EV_POST_CODE ((u32)0x00000001)
	64	#define EV_NO_ACTION ((u32)0x00000003)
	65	#define EV_SEPARATOR ((u32)0x00000004)
	66	#define EV_ACTION ((u32)0x00000005)
	67	#define EV_TAG ((u32)0x00000006)
	68	#define EV_S_CRTM_CONTENTS ((u32)0x00000007)
	69	#define EV_S_CRTM_VERSION ((u32)0x00000008)
	70	#define EV_CPU_MICROCODE ((u32)0x00000009)
	71	#define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A)
	72	#define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
	73	#define EV_COMPACT_HASH ((u32)0x0000000C)
8e0b0871	74
163a0d7e MK	75	/*
	76	* event types, cf.
	77	* "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
8fc4e0b4	78	* Level 00 Version 1.05 Revision 23, May 7, 2021
163a0d7e MK	79	*/
	80	#define EV_EFI_EVENT_BASE ((u32)0x80000000)
	81	#define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001)
	82	#define EV_EFI_VARIABLE_BOOT ((u32)0x80000002)
	83	#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003)
	84	#define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004)
	85	#define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005)
	86	#define EV_EFI_GPT_EVENT ((u32)0x80000006)
	87	#define EV_EFI_ACTION ((u32)0x80000007)
	88	#define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008)
	89	#define EV_EFI_HANDOFF_TABLES ((u32)0x80000009)
8fc4e0b4 MK	90	#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 ((u32)0x8000000A)
	91	#define EV_EFI_HANDOFF_TABLES2 ((u32)0x8000000B)
	92	#define EV_EFI_VARIABLE_BOOT2 ((u32)0x8000000C)
163a0d7e MK	93	#define EV_EFI_HCRTM_EVENT ((u32)0x80000010)
163a0d7e MK	94	#define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0)
8fc4e0b4 MK	95	#define EV_EFI_SPDM_FIRMWARE_BLOB ((u32)0x800000E1)
	96	#define EV_EFI_SPDM_FIRMWARE_CONFIG ((u32)0x800000E2)
	97
	98	#define EFI_CALLING_EFI_APPLICATION \
	99	"Calling EFI Application from Boot Option"
	100	#define EFI_RETURNING_FROM_EFI_APPLICATION \
	101	"Returning from EFI Application from Boot Option"
	102	#define EFI_EXIT_BOOT_SERVICES_INVOCATION \
	103	"Exit Boot Services Invocation"
	104	#define EFI_EXIT_BOOT_SERVICES_FAILED \
	105	"Exit Boot Services Returned with Failure"
	106	#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED \
	107	"Exit Boot Services Returned with Success"
163a0d7e	108
915e3ae5 IA	109	/* TPMS_TAGGED_PROPERTY Structure */
	110	struct tpms_tagged_property {
	111	u32 property;
	112	u32 value;
	113	} __packed;
	114
	115	/* TPMS_PCR_SELECTION Structure */
	116	struct tpms_pcr_selection {
	117	u16 hash;
	118	u8 size_of_select;
	119	u8 pcr_select[TPM2_PCR_SELECT_MAX];
	120	} __packed;
	121
	122	/* TPML_PCR_SELECTION Structure */
	123	struct tpml_pcr_selection {
	124	u32 count;
	125	struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
	126	} __packed;
	127
	128	/* TPML_TAGGED_TPM_PROPERTY Structure */
	129	struct tpml_tagged_tpm_property {
	130	u32 count;
	131	struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
	132	} __packed;
	133
	134	/* TPMU_CAPABILITIES Union */
	135	union tpmu_capabilities {
	136	/*
	137	* Non exhaustive. Only added the structs needed for our
	138	* current code
	139	*/
	140	struct tpml_pcr_selection assigned_pcr;
	141	struct tpml_tagged_tpm_property tpm_properties;
	142	} __packed;
	143
	144	/* TPMS_CAPABILITY_DATA Structure */
	145	struct tpms_capability_data {
	146	u32 capability;
	147	union tpmu_capabilities data;
	148	} __packed;
	149
8e0b0871 IA	150	/**
	151	* SHA1 Event Log Entry Format
	152	*
	153	* @pcr_index: PCRIndex event extended to
	154	* @event_type: Type of event (see EFI specs)
	155	* @digest: Value extended into PCR index
	156	* @event_size: Size of event
	157	* @event: Event data
	158	*/
	159	struct tcg_pcr_event {
	160	u32 pcr_index;
	161	u32 event_type;
	162	u8 digest[TPM2_SHA1_DIGEST_SIZE];
	163	u32 event_size;
	164	u8 event[];
	165	} __packed;
	166
	167	/**
	168	* Definition of TPMU_HA Union
	169	*/
	170	union tmpu_ha {
	171	u8 sha1[TPM2_SHA1_DIGEST_SIZE];
	172	u8 sha256[TPM2_SHA256_DIGEST_SIZE];
	173	u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
	174	u8 sha384[TPM2_SHA384_DIGEST_SIZE];
	175	u8 sha512[TPM2_SHA512_DIGEST_SIZE];
	176	} __packed;
	177
	178	/**
	179	* Definition of TPMT_HA Structure
	180	*
	181	* @hash_alg: Hash algorithm defined in enum tpm2_algorithms
	182	* @digest: Digest value for a given algorithm
	183	*/
	184	struct tpmt_ha {
	185	u16 hash_alg;
	186	union tmpu_ha digest;
	187	} __packed;
	188
	189	/**
	190	* Definition of TPML_DIGEST_VALUES Structure
	191	*
	192	* @count: Number of algorithms supported by hardware
	193	* @digests: struct for algorithm id and hash value
	194	*/
	195	struct tpml_digest_values {
	196	u32 count;
	197	struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
	198	} __packed;
	199
	200	/**
	201	* Crypto Agile Log Entry Format
	202	*
	203	* @pcr_index: PCRIndex event extended to
	204	* @event_type: Type of event
	205	* @digests: List of digestsextended to PCR index
	206	* @event_size: Size of the event data
	207	* @event: Event data
	208	*/
	209	struct tcg_pcr_event2 {
	210	u32 pcr_index;
	211	u32 event_type;
	212	struct tpml_digest_values digests;
	213	u32 event_size;
214	u8 event[];
215	} __packed;
216
ff32245b MR	217	/**
	218	* TPM2 Structure Tags for command/response buffers.
	219	*
	220	* @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
	221	* @TPM2_ST_SESSIONS: the command needs an authentication.
	222	*/
	223	enum tpm2_structures {
	224	TPM2_ST_NO_SESSIONS = 0x8001,
	225	TPM2_ST_SESSIONS = 0x8002,
	226	};
	227
	228	/**
	229	* TPM2 type of boolean.
	230	*/
	231	enum tpm2_yes_no {
	232	TPMI_YES = 1,
	233	TPMI_NO = 0,
	234	};
	235
	236	/**
	237	* TPM2 startup values.
	238	*
	239	* @TPM2_SU_CLEAR: reset the internal state.
	240	* @TPM2_SU_STATE: restore saved state (if any).
	241	*/
	242	enum tpm2_startup_types {
	243	TPM2_SU_CLEAR = 0x0000,
	244	TPM2_SU_STATE = 0x0001,
	245	};
	246
	247	/**
	248	* TPM2 permanent handles.
	249	*
	250	* @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
	251	* @TPM2_RS_PW: indicates a password.
	252	* @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
	253	* @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
	254	* @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
	255	*/
	256	enum tpm2_handles {
	257	TPM2_RH_OWNER = 0x40000001,
	258	TPM2_RS_PW = 0x40000009,
	259	TPM2_RH_LOCKOUT = 0x4000000A,
	260	TPM2_RH_ENDORSEMENT = 0x4000000B,
	261	TPM2_RH_PLATFORM = 0x4000000C,
	262	};
	263
	264	/**
	265	* TPM2 command codes used at the beginning of a buffer, gives the command.
	266	*
	267	* @TPM2_CC_STARTUP: TPM2_Startup().
	268	* @TPM2_CC_SELF_TEST: TPM2_SelfTest().
	269	* @TPM2_CC_CLEAR: TPM2_Clear().
	270	* @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
	271	* @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
	272	* @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
	273	* @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
	274	* @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
	275	* @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
06bea498	276	* @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
ff32245b MR	277	* @TPM2_CC_PCR_READ: TPM2_PCR_Read().
	278	* @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
	279	* @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
	280	*/
	281	enum tpm2_command_codes {
	282	TPM2_CC_STARTUP = 0x0144,
	283	TPM2_CC_SELF_TEST = 0x0143,
63af92e8	284	TPM2_CC_HIER_CONTROL = 0x0121,
ff32245b MR	285	TPM2_CC_CLEAR = 0x0126,
	286	TPM2_CC_CLEARCONTROL = 0x0127,
	287	TPM2_CC_HIERCHANGEAUTH = 0x0129,
eadcbc78	288	TPM2_CC_NV_DEFINE_SPACE = 0x012a,
b9dd4fab	289	TPM2_CC_PCR_SETAUTHPOL = 0x012C,
6719cbe3	290	TPM2_CC_NV_WRITE = 0x0137,
7785bc1d	291	TPM2_CC_NV_WRITELOCK = 0x0138,
ff32245b MR	292	TPM2_CC_DAM_RESET = 0x0139,
ff32245b MR	293	TPM2_CC_DAM_PARAMETERS = 0x013A,
998af319	294	TPM2_CC_NV_READ = 0x014E,
ff32245b	295	TPM2_CC_GET_CAPABILITY = 0x017A,
06bea498	296	TPM2_CC_GET_RANDOM = 0x017B,
ff32245b MR	297	TPM2_CC_PCR_READ = 0x017E,
ff32245b MR	298	TPM2_CC_PCR_EXTEND = 0x0182,
b9dd4fab	299	TPM2_CC_PCR_SETAUTHVAL = 0x0183,
ff32245b MR	300	};
	301
	302	/**
	303	* TPM2 return codes.
	304	*/
	305	enum tpm2_return_codes {
	306	TPM2_RC_SUCCESS = 0x0000,
	307	TPM2_RC_BAD_TAG = 0x001E,
	308	TPM2_RC_FMT1 = 0x0080,
	309	TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
	310	TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
	311	TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
	312	TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
	313	TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
	314	TPM2_RC_VER1 = 0x0100,
	315	TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
	316	TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
	317	TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
	318	TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
	319	TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
	320	TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
	321	TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
63af92e8	322	TPM2_RC_NV_DEFINED = TPM2_RC_VER1 + 0x004c,
ff32245b MR	323	TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
	324	TPM2_RC_WARN = 0x0900,
	325	TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
	326	TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
	327	TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
	328	};
	329
	330	/**
	331	* TPM2 algorithms.
	332	*/
	333	enum tpm2_algorithms {
915e3ae5	334	TPM2_ALG_SHA1 = 0x04,
ff32245b MR	335	TPM2_ALG_XOR = 0x0A,
	336	TPM2_ALG_SHA256 = 0x0B,
	337	TPM2_ALG_SHA384 = 0x0C,
	338	TPM2_ALG_SHA512 = 0x0D,
	339	TPM2_ALG_NULL = 0x10,
915e3ae5	340	TPM2_ALG_SM3_256 = 0x12,
ff32245b MR	341	};
ff32245b MR	342
be8a025e SG	343	/* NV index attributes */
	344	enum tpm_index_attrs {
	345	TPMA_NV_PPWRITE = 1UL << 0,
	346	TPMA_NV_OWNERWRITE = 1UL << 1,
	347	TPMA_NV_AUTHWRITE = 1UL << 2,
	348	TPMA_NV_POLICYWRITE = 1UL << 3,
	349	TPMA_NV_COUNTER = 1UL << 4,
	350	TPMA_NV_BITS = 1UL << 5,
	351	TPMA_NV_EXTEND = 1UL << 6,
	352	TPMA_NV_POLICY_DELETE = 1UL << 10,
	353	TPMA_NV_WRITELOCKED = 1UL << 11,
	354	TPMA_NV_WRITEALL = 1UL << 12,
	355	TPMA_NV_WRITEDEFINE = 1UL << 13,
	356	TPMA_NV_WRITE_STCLEAR = 1UL << 14,
	357	TPMA_NV_GLOBALLOCK = 1UL << 15,
	358	TPMA_NV_PPREAD = 1UL << 16,
	359	TPMA_NV_OWNERREAD = 1UL << 17,
	360	TPMA_NV_AUTHREAD = 1UL << 18,
	361	TPMA_NV_POLICYREAD = 1UL << 19,
	362	TPMA_NV_NO_DA = 1UL << 25,
	363	TPMA_NV_ORDERLY = 1UL << 26,
	364	TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
	365	TPMA_NV_READLOCKED = 1UL << 28,
	366	TPMA_NV_WRITTEN = 1UL << 29,
	367	TPMA_NV_PLATFORMCREATE = 1UL << 30,
	368	TPMA_NV_READ_STCLEAR = 1UL << 31,
	369
	370	TPMA_NV_MASK_READ = TPMA_NV_PPREAD \| TPMA_NV_OWNERREAD \|
	371	TPMA_NV_AUTHREAD \| TPMA_NV_POLICYREAD,
	372	TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE \| TPMA_NV_OWNERWRITE \|
	373	TPMA_NV_AUTHWRITE \| TPMA_NV_POLICYWRITE,
	374	};
	375
1400a7f3 SG	376	enum {
	377	TPM_ACCESS_VALID = 1 << 7,
	378	TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
	379	TPM_ACCESS_REQUEST_PENDING = 1 << 2,
	380	TPM_ACCESS_REQUEST_USE = 1 << 1,
	381	TPM_ACCESS_ESTABLISHMENT = 1 << 0,
	382	};
	383
	384	enum {
	385	TPM_STS_FAMILY_SHIFT = 26,
	386	TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
	387	TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
	388	TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
	389	TPM_STS_COMMAND_CANCEL = 1 << 24,
	390	TPM_STS_BURST_COUNT_SHIFT = 8,
	391	TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
	392	TPM_STS_VALID = 1 << 7,
	393	TPM_STS_COMMAND_READY = 1 << 6,
	394	TPM_STS_GO = 1 << 5,
	395	TPM_STS_DATA_AVAIL = 1 << 4,
	396	TPM_STS_DATA_EXPECT = 1 << 3,
	397	TPM_STS_SELF_TEST_DONE = 1 << 2,
	398	TPM_STS_RESPONSE_RETRY = 1 << 1,
	399	};
	400
	401	enum {
	402	TPM_CMD_COUNT_OFFSET = 2,
	403	TPM_CMD_ORDINAL_OFFSET = 6,
	404	TPM_MAX_BUF_SIZE = 1260,
	405	};
	406
6719cbe3 SG	407	enum {
	408	/* Secure storage for firmware settings */
	409	TPM_HT_PCR = 0,
	410	TPM_HT_NV_INDEX,
	411	TPM_HT_HMAC_SESSION,
	412	TPM_HT_POLICY_SESSION,
	413
	414	HR_SHIFT = 24,
	415	HR_PCR = TPM_HT_PCR << HR_SHIFT,
	416	HR_HMAC_SESSION = TPM_HT_HMAC_SESSION << HR_SHIFT,
	417	HR_POLICY_SESSION = TPM_HT_POLICY_SESSION << HR_SHIFT,
	418	HR_NV_INDEX = TPM_HT_NV_INDEX << HR_SHIFT,
	419	};
	420
1922df20 MR	421	/**
	422	* Issue a TPM2_Startup command.
	423	*
abdc7b8a	424	* @dev TPM device
1922df20 MR	425	* @mode TPM startup mode
	426	*
	427	* @return code of the operation
	428	*/
abdc7b8a	429	u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
1922df20	430
2dc6d97e MR	431	/**
	432	* Issue a TPM2_SelfTest command.
	433	*
abdc7b8a	434	* @dev TPM device
2dc6d97e MR	435	* @full_test Asking to perform all tests or only the untested ones
	436	*
	437	* @return code of the operation
	438	*/
abdc7b8a	439	u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
2dc6d97e	440
bad8ff56 MR	441	/**
	442	* Issue a TPM2_Clear command.
	443	*
abdc7b8a	444	* @dev TPM device
bad8ff56 MR	445	* @handle Handle
	446	* @pw Password
	447	* @pw_sz Length of the password
	448	*
	449	* @return code of the operation
	450	*/
abdc7b8a SG	451	u32 tpm2_clear(struct udevice dev, u32 handle, const char pw,
abdc7b8a SG	452	const ssize_t pw_sz);
bad8ff56	453
eadcbc78 SG	454	/**
	455	* Issue a TPM_NV_DefineSpace command
	456	*
	457	* This allows a space to be defined with given attributes and policy
	458	*
	459	* @dev TPM device
	460	* @space_index index of the area
	461	* @space_size size of area in bytes
	462	* @nv_attributes TPM_NV_ATTRIBUTES of the area
	463	* @nv_policy policy to use
	464	* @nv_policy_size size of the policy
	465	* @return return code of the operation
	466	*/
	467	u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index,
	468	size_t space_size, u32 nv_attributes,
	469	const u8 *nv_policy, size_t nv_policy_size);
	470
6284be5a MR	471	/**
	472	* Issue a TPM2_PCR_Extend command.
	473	*
abdc7b8a	474	* @dev TPM device
6284be5a	475	* @index Index of the PCR
e926136b	476	* @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
6284be5a	477	* @digest Value representing the event to be recorded
e926136b	478	* @digest_len len of the hash
6284be5a MR	479	*
	480	* @return code of the operation
	481	*/
e926136b IA	482	u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
e926136b IA	483	const u8 *digest, u32 digest_len);
6284be5a	484
6719cbe3 SG	485	/**
	486	* Read data from the secure storage
	487	*
	488	* @dev TPM device
	489	* @index Index of data to read
	490	* @data Place to put data
	491	* @count Number of bytes of data
	492	* @return code of the operation
	493	*/
	494	u32 tpm2_nv_read_value(struct udevice dev, u32 index, void data, u32 count);
	495
	496	/**
	497	* Write data to the secure storage
	498	*
	499	* @dev TPM device
	500	* @index Index of data to write
	501	* @data Data to write
	502	* @count Number of bytes of data
	503	* @return code of the operation
	504	*/
	505	u32 tpm2_nv_write_value(struct udevice dev, u32 index, const void data,
	506	u32 count);
	507
1c4ea8f4 MR	508	/**
	509	* Issue a TPM2_PCR_Read command.
	510	*
abdc7b8a	511	* @dev TPM device
1c4ea8f4 MR	512	* @idx Index of the PCR
	513	* @idx_min_sz Minimum size in bytes of the pcrSelect array
	514	* @data Output buffer for contents of the named PCR
	515	* @updates Optional out parameter: number of updates for this PCR
	516	*
	517	* @return code of the operation
	518	*/
abdc7b8a SG	519	u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
abdc7b8a SG	520	void data, unsigned int updates);
1c4ea8f4	521
69cd8f06 MR	522	/**
	523	* Issue a TPM2_GetCapability command. This implementation is limited
	524	* to query property index that is 4-byte wide.
	525	*
abdc7b8a	526	* @dev TPM device
69cd8f06 MR	527	* @capability Partition of capabilities
	528	* @property Further definition of capability, limited to be 4 bytes wide
	529	* @buf Output buffer for capability information
	530	* @prop_count Size of output buffer
	531	*
	532	* @return code of the operation
	533	*/
abdc7b8a SG	534	u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
abdc7b8a SG	535	void *buf, size_t prop_count);
69cd8f06	536
da9c3392 MR	537	/**
	538	* Issue a TPM2_DictionaryAttackLockReset command.
	539	*
abdc7b8a	540	* @dev TPM device
da9c3392 MR	541	* @pw Password
	542	* @pw_sz Length of the password
	543	*
	544	* @return code of the operation
	545	*/
abdc7b8a	546	u32 tpm2_dam_reset(struct udevice dev, const char pw, const ssize_t pw_sz);
da9c3392 MR	547
	548	/**
	549	* Issue a TPM2_DictionaryAttackParameters command.
	550	*
abdc7b8a	551	* @dev TPM device
da9c3392 MR	552	* @pw Password
	553	* @pw_sz Length of the password
	554	* @max_tries Count of authorizations before lockout
	555	* @recovery_time Time before decrementation of the failure count
	556	* @lockout_recovery Time to wait after a lockout
	557	*
	558	* @return code of the operation
	559	*/
abdc7b8a SG	560	u32 tpm2_dam_parameters(struct udevice dev, const char pw,
	561	const ssize_t pw_sz, unsigned int max_tries,
	562	unsigned int recovery_time,
da9c3392 MR	563	unsigned int lockout_recovery);
da9c3392 MR	564
dc26e913 MR	565	/**
	566	* Issue a TPM2_HierarchyChangeAuth command.
	567	*
abdc7b8a	568	* @dev TPM device
dc26e913 MR	569	* @handle Handle
	570	* @newpw New password
	571	* @newpw_sz Length of the new password
	572	* @oldpw Old password
	573	* @oldpw_sz Length of the old password
	574	*
	575	* @return code of the operation
	576	*/
abdc7b8a SG	577	int tpm2_change_auth(struct udevice dev, u32 handle, const char newpw,
	578	const ssize_t newpw_sz, const char *oldpw,
	579	const ssize_t oldpw_sz);
dc26e913	580
b9dd4fab MR	581	/**
	582	* Issue a TPM_PCR_SetAuthPolicy command.
	583	*
abdc7b8a	584	* @dev TPM device
b9dd4fab MR	585	* @pw Platform password
	586	* @pw_sz Length of the password
	587	* @index Index of the PCR
	588	* @digest New key to access the PCR
	589	*
	590	* @return code of the operation
	591	*/
abdc7b8a SG	592	u32 tpm2_pcr_setauthpolicy(struct udevice dev, const char pw,
abdc7b8a SG	593	const ssize_t pw_sz, u32 index, const char *key);
b9dd4fab MR	594
	595	/**
	596	* Issue a TPM_PCR_SetAuthValue command.
	597	*
abdc7b8a	598	* @dev TPM device
b9dd4fab MR	599	* @pw Platform password
	600	* @pw_sz Length of the password
	601	* @index Index of the PCR
	602	* @digest New key to access the PCR
	603	* @key_sz Length of the new key
	604	*
	605	* @return code of the operation
	606	*/
abdc7b8a SG	607	u32 tpm2_pcr_setauthvalue(struct udevice dev, const char pw,
	608	const ssize_t pw_sz, u32 index, const char *key,
	609	const ssize_t key_sz);
b9dd4fab	610
06bea498 DP	611	/**
	612	* Issue a TPM2_GetRandom command.
	613	*
	614	* @dev TPM device
	615	* @param data output buffer for the random bytes
	616	* @param count size of output buffer
	617	*
	618	* @return return code of the operation
	619	*/
	620	u32 tpm2_get_random(struct udevice dev, void data, u32 count);
	621
7785bc1d SG	622	/**
	623	* Lock data in the TPM
	624	*
	625	* Once locked the data cannot be written until after a reboot
	626	*
	627	* @dev TPM device
	628	* @index Index of data to lock
	629	* @return code of the operation
	630	*/
	631	u32 tpm2_write_lock(struct udevice *dev, u32 index);
	632
63af92e8 SG	633	/**
	634	* Disable access to any platform data
	635	*
	636	* This can be called to close off access to the firmware data in the data,
	637	* before calling the kernel.
	638	*
	639	* @dev TPM device
	640	* @return code of the operation
	641	*/
	642	u32 tpm2_disable_platform_hierarchy(struct udevice *dev);
	643
7fc93cae MK	644	/**
	645	* submit user specified data to the TPM and get response
	646	*
	647	* @dev TPM device
	648	* @sendbuf: Buffer of the data to send
	649	* @recvbuf: Buffer to save the response to
	650	* @recv_size: Pointer to the size of the response buffer
	651	*
	652	* @return code of the operation
	653	*/
	654	u32 tpm2_submit_command(struct udevice dev, const u8 sendbuf,
	655	u8 recvbuf, size_t recv_size);
	656
ff32245b	657	#endif /* __TPM_V2_H */