[J-u-boot.git] / include / tpm-v2.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Defines APIs and structures that allow software to interact with a
 * TPM2 device
 *
 * Copyright (c) 2020 Linaro
 * Copyright (c) 2018 Bootlin
 *
 * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
 *
 * Author: Miquel Raynal <[email protected]>
 */

#ifndef __TPM_V2_H
#define __TPM_V2_H

#include <tpm-common.h>

#define TPM2_DIGEST_LEN		32

#define TPM2_SHA1_DIGEST_SIZE 20
#define TPM2_SHA256_DIGEST_SIZE	32
#define TPM2_SHA384_DIGEST_SIZE	48
#define TPM2_SHA512_DIGEST_SIZE	64
#define TPM2_SM3_256_DIGEST_SIZE 32

#define TPM2_MAX_PCRS 32
#define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
#define TPM2_MAX_CAP_BUFFER 1024
#define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
				 sizeof(u32)) / sizeof(struct tpms_tagged_property))

/*
 *  We deviate from this draft of the specification by increasing the value of
 *  TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
 *  implementations that have enabled a larger than typical number of PCR
 *  banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
 *  in a future revision of the specification.
 */
#define TPM2_NUM_PCR_BANKS 16

/* Definition of (UINT32) TPM2_CAP Constants */
#define TPM2_CAP_PCRS 0x00000005U
#define TPM2_CAP_TPM_PROPERTIES 0x00000006U

/* Definition of (UINT32) TPM2_PT Constants */
#define TPM2_PT_GROUP			(u32)(0x00000100)
#define TPM2_PT_FIXED			(u32)(TPM2_PT_GROUP * 1)
#define TPM2_PT_MANUFACTURER		(u32)(TPM2_PT_FIXED + 5)
#define TPM2_PT_PCR_COUNT		(u32)(TPM2_PT_FIXED + 18)
#define TPM2_PT_MAX_COMMAND_SIZE	(u32)(TPM2_PT_FIXED + 30)
#define TPM2_PT_MAX_RESPONSE_SIZE	(u32)(TPM2_PT_FIXED + 31)

/* event types */
#define EV_POST_CODE		((u32)0x00000001)
#define EV_NO_ACTION		((u32)0x00000003)
#define EV_SEPARATOR		((u32)0x00000004)
#define EV_S_CRTM_CONTENTS	((u32)0x00000007)
#define EV_S_CRTM_VERSION	((u32)0x00000008)
#define EV_CPU_MICROCODE	((u32)0x00000009)
#define EV_TABLE_OF_DEVICES	((u32)0x0000000B)

/* TPMS_TAGGED_PROPERTY Structure */
struct tpms_tagged_property {
	u32 property;
	u32 value;
} __packed;

/* TPMS_PCR_SELECTION Structure */
struct tpms_pcr_selection {
	u16 hash;
	u8 size_of_select;
	u8 pcr_select[TPM2_PCR_SELECT_MAX];
} __packed;

/* TPML_PCR_SELECTION Structure */
struct tpml_pcr_selection {
	u32 count;
	struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
} __packed;

/* TPML_TAGGED_TPM_PROPERTY Structure */
struct tpml_tagged_tpm_property {
	u32 count;
	struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
} __packed;

/* TPMU_CAPABILITIES Union */
union tpmu_capabilities {
	/*
	 * Non exhaustive. Only added the structs needed for our
	 * current code
	 */
	struct tpml_pcr_selection assigned_pcr;
	struct tpml_tagged_tpm_property tpm_properties;
} __packed;

/* TPMS_CAPABILITY_DATA Structure */
struct tpms_capability_data {
	u32 capability;
	union tpmu_capabilities data;
} __packed;

/**
 * SHA1 Event Log Entry Format
 *
 * @pcr_index:	PCRIndex event extended to
 * @event_type:	Type of event (see EFI specs)
 * @digest:	Value extended into PCR index
 * @event_size:	Size of event
 * @event:	Event data
 */
struct tcg_pcr_event {
	u32 pcr_index;
	u32 event_type;
	u8 digest[TPM2_SHA1_DIGEST_SIZE];
	u32 event_size;
	u8 event[];
} __packed;

/**
 * Definition of TPMU_HA Union
 */
union tmpu_ha {
	u8 sha1[TPM2_SHA1_DIGEST_SIZE];
	u8 sha256[TPM2_SHA256_DIGEST_SIZE];
	u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
	u8 sha384[TPM2_SHA384_DIGEST_SIZE];
	u8 sha512[TPM2_SHA512_DIGEST_SIZE];
} __packed;

/**
 * Definition of TPMT_HA Structure
 *
 * @hash_alg:	Hash algorithm defined in enum tpm2_algorithms
 * @digest:	Digest value for a given algorithm
 */
struct tpmt_ha {
	u16 hash_alg;
	union tmpu_ha digest;
} __packed;

/**
 * Definition of TPML_DIGEST_VALUES Structure
 *
 * @count:	Number of algorithms supported by hardware
 * @digests:	struct for algorithm id and hash value
 */
struct tpml_digest_values {
	u32 count;
	struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
} __packed;

/**
 * Crypto Agile Log Entry Format
 *
 * @pcr_index:	PCRIndex event extended to
 * @event_type:	Type of event
 * @digests:	List of digestsextended to PCR index
 * @event_size: Size of the event data
 * @event:	Event data
 */
struct tcg_pcr_event2 {
	u32 pcr_index;
	u32 event_type;
	struct tpml_digest_values digests;
	u32 event_size;
	u8 event[];
} __packed;

/**
 * TPM2 Structure Tags for command/response buffers.
 *
 * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
 * @TPM2_ST_SESSIONS: the command needs an authentication.
 */
enum tpm2_structures {
	TPM2_ST_NO_SESSIONS	= 0x8001,
	TPM2_ST_SESSIONS	= 0x8002,
};

/**
 * TPM2 type of boolean.
 */
enum tpm2_yes_no {
	TPMI_YES		= 1,
	TPMI_NO			= 0,
};

/**
 * TPM2 startup values.
 *
 * @TPM2_SU_CLEAR: reset the internal state.
 * @TPM2_SU_STATE: restore saved state (if any).
 */
enum tpm2_startup_types {
	TPM2_SU_CLEAR		= 0x0000,
	TPM2_SU_STATE		= 0x0001,
};

/**
 * TPM2 permanent handles.
 *
 * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
 * @TPM2_RS_PW: indicates a password.
 * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
 * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
 * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
 */
enum tpm2_handles {
	TPM2_RH_OWNER		= 0x40000001,
	TPM2_RS_PW		= 0x40000009,
	TPM2_RH_LOCKOUT		= 0x4000000A,
	TPM2_RH_ENDORSEMENT	= 0x4000000B,
	TPM2_RH_PLATFORM	= 0x4000000C,
};

/**
 * TPM2 command codes used at the beginning of a buffer, gives the command.
 *
 * @TPM2_CC_STARTUP: TPM2_Startup().
 * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
 * @TPM2_CC_CLEAR: TPM2_Clear().
 * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
 * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
 * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
 * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
 * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
 * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
 * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
 * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
 * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
 * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
 */
enum tpm2_command_codes {
	TPM2_CC_STARTUP		= 0x0144,
	TPM2_CC_SELF_TEST	= 0x0143,
	TPM2_CC_CLEAR		= 0x0126,
	TPM2_CC_CLEARCONTROL	= 0x0127,
	TPM2_CC_HIERCHANGEAUTH	= 0x0129,
	TPM2_CC_PCR_SETAUTHPOL	= 0x012C,
	TPM2_CC_DAM_RESET	= 0x0139,
	TPM2_CC_DAM_PARAMETERS	= 0x013A,
	TPM2_CC_NV_READ         = 0x014E,
	TPM2_CC_GET_CAPABILITY	= 0x017A,
	TPM2_CC_GET_RANDOM      = 0x017B,
	TPM2_CC_PCR_READ	= 0x017E,
	TPM2_CC_PCR_EXTEND	= 0x0182,
	TPM2_CC_PCR_SETAUTHVAL	= 0x0183,
};

/**
 * TPM2 return codes.
 */
enum tpm2_return_codes {
	TPM2_RC_SUCCESS		= 0x0000,
	TPM2_RC_BAD_TAG		= 0x001E,
	TPM2_RC_FMT1		= 0x0080,
	TPM2_RC_HASH		= TPM2_RC_FMT1 + 0x0003,
	TPM2_RC_VALUE		= TPM2_RC_FMT1 + 0x0004,
	TPM2_RC_SIZE		= TPM2_RC_FMT1 + 0x0015,
	TPM2_RC_BAD_AUTH	= TPM2_RC_FMT1 + 0x0022,
	TPM2_RC_HANDLE		= TPM2_RC_FMT1 + 0x000B,
	TPM2_RC_VER1		= 0x0100,
	TPM2_RC_INITIALIZE	= TPM2_RC_VER1 + 0x0000,
	TPM2_RC_FAILURE		= TPM2_RC_VER1 + 0x0001,
	TPM2_RC_DISABLED	= TPM2_RC_VER1 + 0x0020,
	TPM2_RC_AUTH_MISSING	= TPM2_RC_VER1 + 0x0025,
	TPM2_RC_COMMAND_CODE	= TPM2_RC_VER1 + 0x0043,
	TPM2_RC_AUTHSIZE	= TPM2_RC_VER1 + 0x0044,
	TPM2_RC_AUTH_CONTEXT	= TPM2_RC_VER1 + 0x0045,
	TPM2_RC_NEEDS_TEST	= TPM2_RC_VER1 + 0x0053,
	TPM2_RC_WARN		= 0x0900,
	TPM2_RC_TESTING		= TPM2_RC_WARN + 0x000A,
	TPM2_RC_REFERENCE_H0	= TPM2_RC_WARN + 0x0010,
	TPM2_RC_LOCKOUT		= TPM2_RC_WARN + 0x0021,
};

/**
 * TPM2 algorithms.
 */
enum tpm2_algorithms {
	TPM2_ALG_SHA1		= 0x04,
	TPM2_ALG_XOR		= 0x0A,
	TPM2_ALG_SHA256		= 0x0B,
	TPM2_ALG_SHA384		= 0x0C,
	TPM2_ALG_SHA512		= 0x0D,
	TPM2_ALG_NULL		= 0x10,
	TPM2_ALG_SM3_256	= 0x12,
};

/* NV index attributes */
enum tpm_index_attrs {
	TPMA_NV_PPWRITE		= 1UL << 0,
	TPMA_NV_OWNERWRITE	= 1UL << 1,
	TPMA_NV_AUTHWRITE	= 1UL << 2,
	TPMA_NV_POLICYWRITE	= 1UL << 3,
	TPMA_NV_COUNTER		= 1UL << 4,
	TPMA_NV_BITS		= 1UL << 5,
	TPMA_NV_EXTEND		= 1UL << 6,
	TPMA_NV_POLICY_DELETE	= 1UL << 10,
	TPMA_NV_WRITELOCKED	= 1UL << 11,
	TPMA_NV_WRITEALL	= 1UL << 12,
	TPMA_NV_WRITEDEFINE	= 1UL << 13,
	TPMA_NV_WRITE_STCLEAR	= 1UL << 14,
	TPMA_NV_GLOBALLOCK	= 1UL << 15,
	TPMA_NV_PPREAD		= 1UL << 16,
	TPMA_NV_OWNERREAD	= 1UL << 17,
	TPMA_NV_AUTHREAD	= 1UL << 18,
	TPMA_NV_POLICYREAD	= 1UL << 19,
	TPMA_NV_NO_DA		= 1UL << 25,
	TPMA_NV_ORDERLY		= 1UL << 26,
	TPMA_NV_CLEAR_STCLEAR	= 1UL << 27,
	TPMA_NV_READLOCKED	= 1UL << 28,
	TPMA_NV_WRITTEN		= 1UL << 29,
	TPMA_NV_PLATFORMCREATE	= 1UL << 30,
	TPMA_NV_READ_STCLEAR	= 1UL << 31,

	TPMA_NV_MASK_READ	= TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
				TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
	TPMA_NV_MASK_WRITE	= TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
					TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
};

enum {
	TPM_ACCESS_VALID		= 1 << 7,
	TPM_ACCESS_ACTIVE_LOCALITY	= 1 << 5,
	TPM_ACCESS_REQUEST_PENDING	= 1 << 2,
	TPM_ACCESS_REQUEST_USE		= 1 << 1,
	TPM_ACCESS_ESTABLISHMENT	= 1 << 0,
};

enum {
	TPM_STS_FAMILY_SHIFT		= 26,
	TPM_STS_FAMILY_MASK		= 0x3 << TPM_STS_FAMILY_SHIFT,
	TPM_STS_FAMILY_TPM2		= 1 << TPM_STS_FAMILY_SHIFT,
	TPM_STS_RESE_TESTABLISMENT_BIT	= 1 << 25,
	TPM_STS_COMMAND_CANCEL		= 1 << 24,
	TPM_STS_BURST_COUNT_SHIFT	= 8,
	TPM_STS_BURST_COUNT_MASK	= 0xffff << TPM_STS_BURST_COUNT_SHIFT,
	TPM_STS_VALID			= 1 << 7,
	TPM_STS_COMMAND_READY		= 1 << 6,
	TPM_STS_GO			= 1 << 5,
	TPM_STS_DATA_AVAIL		= 1 << 4,
	TPM_STS_DATA_EXPECT		= 1 << 3,
	TPM_STS_SELF_TEST_DONE		= 1 << 2,
	TPM_STS_RESPONSE_RETRY		= 1 << 1,
};

enum {
	TPM_CMD_COUNT_OFFSET	= 2,
	TPM_CMD_ORDINAL_OFFSET	= 6,
	TPM_MAX_BUF_SIZE	= 1260,
};

/**
 * Issue a TPM2_Startup command.
 *
 * @dev		TPM device
 * @mode	TPM startup mode
 *
 * @return code of the operation
 */
u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);

/**
 * Issue a TPM2_SelfTest command.
 *
 * @dev		TPM device
 * @full_test	Asking to perform all tests or only the untested ones
 *
 * @return code of the operation
 */
u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);

/**
 * Issue a TPM2_Clear command.
 *
 * @dev		TPM device
 * @handle	Handle
 * @pw		Password
 * @pw_sz	Length of the password
 *
 * @return code of the operation
 */
u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
	       const ssize_t pw_sz);

/**
 * Issue a TPM2_PCR_Extend command.
 *
 * @dev		TPM device
 * @index	Index of the PCR
 * @algorithm	Algorithm used, defined in 'enum tpm2_algorithms'
 * @digest	Value representing the event to be recorded
 * @digest_len  len of the hash
 *
 * @return code of the operation
 */
u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
		    const u8 *digest, u32 digest_len);

/**
 * Issue a TPM2_PCR_Read command.
 *
 * @dev		TPM device
 * @idx		Index of the PCR
 * @idx_min_sz	Minimum size in bytes of the pcrSelect array
 * @data	Output buffer for contents of the named PCR
 * @updates	Optional out parameter: number of updates for this PCR
 *
 * @return code of the operation
 */
u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
		  void *data, unsigned int *updates);

/**
 * Issue a TPM2_GetCapability command.  This implementation is limited
 * to query property index that is 4-byte wide.
 *
 * @dev		TPM device
 * @capability	Partition of capabilities
 * @property	Further definition of capability, limited to be 4 bytes wide
 * @buf		Output buffer for capability information
 * @prop_count	Size of output buffer
 *
 * @return code of the operation
 */
u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
			void *buf, size_t prop_count);

/**
 * Issue a TPM2_DictionaryAttackLockReset command.
 *
 * @dev		TPM device
 * @pw		Password
 * @pw_sz	Length of the password
 *
 * @return code of the operation
 */
u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);

/**
 * Issue a TPM2_DictionaryAttackParameters command.
 *
 * @dev		TPM device
 * @pw		Password
 * @pw_sz	Length of the password
 * @max_tries	Count of authorizations before lockout
 * @recovery_time Time before decrementation of the failure count
 * @lockout_recovery Time to wait after a lockout
 *
 * @return code of the operation
 */
u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
			const ssize_t pw_sz, unsigned int max_tries,
			unsigned int recovery_time,
			unsigned int lockout_recovery);

/**
 * Issue a TPM2_HierarchyChangeAuth command.
 *
 * @dev		TPM device
 * @handle	Handle
 * @newpw	New password
 * @newpw_sz	Length of the new password
 * @oldpw	Old password
 * @oldpw_sz	Length of the old password
 *
 * @return code of the operation
 */
int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
		     const ssize_t newpw_sz, const char *oldpw,
		     const ssize_t oldpw_sz);

/**
 * Issue a TPM_PCR_SetAuthPolicy command.
 *
 * @dev		TPM device
 * @pw		Platform password
 * @pw_sz	Length of the password
 * @index	Index of the PCR
 * @digest	New key to access the PCR
 *
 * @return code of the operation
 */
u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
			   const ssize_t pw_sz, u32 index, const char *key);

/**
 * Issue a TPM_PCR_SetAuthValue command.
 *
 * @dev		TPM device
 * @pw		Platform password
 * @pw_sz	Length of the password
 * @index	Index of the PCR
 * @digest	New key to access the PCR
 * @key_sz	Length of the new key
 *
 * @return code of the operation
 */
u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
			  const ssize_t pw_sz, u32 index, const char *key,
			  const ssize_t key_sz);

/**
 * Issue a TPM2_GetRandom command.
 *
 * @dev		TPM device
 * @param data		output buffer for the random bytes
 * @param count		size of output buffer
 *
 * @return return code of the operation
 */
u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);

#endif /* __TPM_V2_H */
Commit	Line	Data
ff32245b MR	1	/* SPDX-License-Identifier: GPL-2.0+ */
ff32245b MR	2	/*
915e3ae5 IA	3	* Defines APIs and structures that allow software to interact with a
	4	* TPM2 device
	5	*
	6	* Copyright (c) 2020 Linaro
ff32245b	7	* Copyright (c) 2018 Bootlin
915e3ae5 IA	8	*
	9	* https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
	10	*
ff32245b MR	11	* Author: Miquel Raynal <[email protected]>
	12	*/
	13
	14	#ifndef __TPM_V2_H
	15	#define __TPM_V2_H
	16
	17	#include <tpm-common.h>
	18
	19	#define TPM2_DIGEST_LEN 32
	20
8e0b0871 IA	21	#define TPM2_SHA1_DIGEST_SIZE 20
	22	#define TPM2_SHA256_DIGEST_SIZE 32
	23	#define TPM2_SHA384_DIGEST_SIZE 48
	24	#define TPM2_SHA512_DIGEST_SIZE 64
	25	#define TPM2_SM3_256_DIGEST_SIZE 32
	26
915e3ae5 IA	27	#define TPM2_MAX_PCRS 32
	28	#define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
	29	#define TPM2_MAX_CAP_BUFFER 1024
	30	#define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
	31	sizeof(u32)) / sizeof(struct tpms_tagged_property))
	32
	33	/*
	34	* We deviate from this draft of the specification by increasing the value of
	35	* TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
	36	* implementations that have enabled a larger than typical number of PCR
	37	* banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
	38	* in a future revision of the specification.
	39	*/
	40	#define TPM2_NUM_PCR_BANKS 16
	41
	42	/* Definition of (UINT32) TPM2_CAP Constants */
	43	#define TPM2_CAP_PCRS 0x00000005U
	44	#define TPM2_CAP_TPM_PROPERTIES 0x00000006U
	45
	46	/* Definition of (UINT32) TPM2_PT Constants */
	47	#define TPM2_PT_GROUP (u32)(0x00000100)
	48	#define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
	49	#define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
	50	#define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
	51	#define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
	52	#define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
	53
8e0b0871 IA	54	/* event types */
	55	#define EV_POST_CODE ((u32)0x00000001)
	56	#define EV_NO_ACTION ((u32)0x00000003)
	57	#define EV_SEPARATOR ((u32)0x00000004)
	58	#define EV_S_CRTM_CONTENTS ((u32)0x00000007)
	59	#define EV_S_CRTM_VERSION ((u32)0x00000008)
	60	#define EV_CPU_MICROCODE ((u32)0x00000009)
	61	#define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
	62
915e3ae5 IA	63	/* TPMS_TAGGED_PROPERTY Structure */
	64	struct tpms_tagged_property {
	65	u32 property;
	66	u32 value;
	67	} __packed;
	68
	69	/* TPMS_PCR_SELECTION Structure */
	70	struct tpms_pcr_selection {
	71	u16 hash;
	72	u8 size_of_select;
	73	u8 pcr_select[TPM2_PCR_SELECT_MAX];
	74	} __packed;
	75
	76	/* TPML_PCR_SELECTION Structure */
	77	struct tpml_pcr_selection {
	78	u32 count;
	79	struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
	80	} __packed;
	81
	82	/* TPML_TAGGED_TPM_PROPERTY Structure */
	83	struct tpml_tagged_tpm_property {
	84	u32 count;
	85	struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
	86	} __packed;
	87
	88	/* TPMU_CAPABILITIES Union */
	89	union tpmu_capabilities {
	90	/*
	91	* Non exhaustive. Only added the structs needed for our
	92	* current code
	93	*/
	94	struct tpml_pcr_selection assigned_pcr;
	95	struct tpml_tagged_tpm_property tpm_properties;
	96	} __packed;
	97
	98	/* TPMS_CAPABILITY_DATA Structure */
	99	struct tpms_capability_data {
	100	u32 capability;
	101	union tpmu_capabilities data;
	102	} __packed;
	103
8e0b0871 IA	104	/**
	105	* SHA1 Event Log Entry Format
	106	*
	107	* @pcr_index: PCRIndex event extended to
	108	* @event_type: Type of event (see EFI specs)
	109	* @digest: Value extended into PCR index
	110	* @event_size: Size of event
	111	* @event: Event data
	112	*/
	113	struct tcg_pcr_event {
	114	u32 pcr_index;
	115	u32 event_type;
	116	u8 digest[TPM2_SHA1_DIGEST_SIZE];
	117	u32 event_size;
	118	u8 event[];
	119	} __packed;
	120
	121	/**
	122	* Definition of TPMU_HA Union
	123	*/
	124	union tmpu_ha {
	125	u8 sha1[TPM2_SHA1_DIGEST_SIZE];
	126	u8 sha256[TPM2_SHA256_DIGEST_SIZE];
	127	u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
	128	u8 sha384[TPM2_SHA384_DIGEST_SIZE];
	129	u8 sha512[TPM2_SHA512_DIGEST_SIZE];
	130	} __packed;
	131
	132	/**
	133	* Definition of TPMT_HA Structure
	134	*
	135	* @hash_alg: Hash algorithm defined in enum tpm2_algorithms
	136	* @digest: Digest value for a given algorithm
	137	*/
	138	struct tpmt_ha {
	139	u16 hash_alg;
	140	union tmpu_ha digest;
	141	} __packed;
	142
	143	/**
	144	* Definition of TPML_DIGEST_VALUES Structure
	145	*
	146	* @count: Number of algorithms supported by hardware
	147	* @digests: struct for algorithm id and hash value
	148	*/
	149	struct tpml_digest_values {
	150	u32 count;
	151	struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
	152	} __packed;
	153
	154	/**
	155	* Crypto Agile Log Entry Format
	156	*
	157	* @pcr_index: PCRIndex event extended to
	158	* @event_type: Type of event
	159	* @digests: List of digestsextended to PCR index
	160	* @event_size: Size of the event data
	161	* @event: Event data
	162	*/
	163	struct tcg_pcr_event2 {
	164	u32 pcr_index;
	165	u32 event_type;
	166	struct tpml_digest_values digests;
	167	u32 event_size;
168	u8 event[];
169	} __packed;
170
ff32245b MR	171	/**
	172	* TPM2 Structure Tags for command/response buffers.
	173	*
	174	* @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
	175	* @TPM2_ST_SESSIONS: the command needs an authentication.
	176	*/
	177	enum tpm2_structures {
	178	TPM2_ST_NO_SESSIONS = 0x8001,
	179	TPM2_ST_SESSIONS = 0x8002,
	180	};
	181
	182	/**
	183	* TPM2 type of boolean.
	184	*/
	185	enum tpm2_yes_no {
	186	TPMI_YES = 1,
	187	TPMI_NO = 0,
	188	};
	189
	190	/**
	191	* TPM2 startup values.
	192	*
	193	* @TPM2_SU_CLEAR: reset the internal state.
	194	* @TPM2_SU_STATE: restore saved state (if any).
	195	*/
	196	enum tpm2_startup_types {
	197	TPM2_SU_CLEAR = 0x0000,
	198	TPM2_SU_STATE = 0x0001,
	199	};
	200
	201	/**
	202	* TPM2 permanent handles.
	203	*
	204	* @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
	205	* @TPM2_RS_PW: indicates a password.
	206	* @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
	207	* @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
	208	* @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
	209	*/
	210	enum tpm2_handles {
	211	TPM2_RH_OWNER = 0x40000001,
	212	TPM2_RS_PW = 0x40000009,
	213	TPM2_RH_LOCKOUT = 0x4000000A,
	214	TPM2_RH_ENDORSEMENT = 0x4000000B,
	215	TPM2_RH_PLATFORM = 0x4000000C,
	216	};
	217
	218	/**
	219	* TPM2 command codes used at the beginning of a buffer, gives the command.
	220	*
	221	* @TPM2_CC_STARTUP: TPM2_Startup().
	222	* @TPM2_CC_SELF_TEST: TPM2_SelfTest().
	223	* @TPM2_CC_CLEAR: TPM2_Clear().
	224	* @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
	225	* @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
	226	* @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
	227	* @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
	228	* @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
	229	* @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
06bea498	230	* @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
ff32245b MR	231	* @TPM2_CC_PCR_READ: TPM2_PCR_Read().
	232	* @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
	233	* @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
	234	*/
	235	enum tpm2_command_codes {
	236	TPM2_CC_STARTUP = 0x0144,
	237	TPM2_CC_SELF_TEST = 0x0143,
	238	TPM2_CC_CLEAR = 0x0126,
	239	TPM2_CC_CLEARCONTROL = 0x0127,
	240	TPM2_CC_HIERCHANGEAUTH = 0x0129,
b9dd4fab	241	TPM2_CC_PCR_SETAUTHPOL = 0x012C,
ff32245b MR	242	TPM2_CC_DAM_RESET = 0x0139,
ff32245b MR	243	TPM2_CC_DAM_PARAMETERS = 0x013A,
998af319	244	TPM2_CC_NV_READ = 0x014E,
ff32245b	245	TPM2_CC_GET_CAPABILITY = 0x017A,
06bea498	246	TPM2_CC_GET_RANDOM = 0x017B,
ff32245b MR	247	TPM2_CC_PCR_READ = 0x017E,
ff32245b MR	248	TPM2_CC_PCR_EXTEND = 0x0182,
b9dd4fab	249	TPM2_CC_PCR_SETAUTHVAL = 0x0183,
ff32245b MR	250	};
	251
	252	/**
	253	* TPM2 return codes.
	254	*/
	255	enum tpm2_return_codes {
	256	TPM2_RC_SUCCESS = 0x0000,
	257	TPM2_RC_BAD_TAG = 0x001E,
	258	TPM2_RC_FMT1 = 0x0080,
	259	TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
	260	TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
	261	TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
	262	TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
	263	TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
	264	TPM2_RC_VER1 = 0x0100,
	265	TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
	266	TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
	267	TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
	268	TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
	269	TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
	270	TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
	271	TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
	272	TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
	273	TPM2_RC_WARN = 0x0900,
	274	TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
	275	TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
	276	TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
	277	};
	278
	279	/**
	280	* TPM2 algorithms.
	281	*/
	282	enum tpm2_algorithms {
915e3ae5	283	TPM2_ALG_SHA1 = 0x04,
ff32245b MR	284	TPM2_ALG_XOR = 0x0A,
	285	TPM2_ALG_SHA256 = 0x0B,
	286	TPM2_ALG_SHA384 = 0x0C,
	287	TPM2_ALG_SHA512 = 0x0D,
	288	TPM2_ALG_NULL = 0x10,
915e3ae5	289	TPM2_ALG_SM3_256 = 0x12,
ff32245b MR	290	};
ff32245b MR	291
be8a025e SG	292	/* NV index attributes */
	293	enum tpm_index_attrs {
	294	TPMA_NV_PPWRITE = 1UL << 0,
	295	TPMA_NV_OWNERWRITE = 1UL << 1,
	296	TPMA_NV_AUTHWRITE = 1UL << 2,
	297	TPMA_NV_POLICYWRITE = 1UL << 3,
	298	TPMA_NV_COUNTER = 1UL << 4,
	299	TPMA_NV_BITS = 1UL << 5,
	300	TPMA_NV_EXTEND = 1UL << 6,
	301	TPMA_NV_POLICY_DELETE = 1UL << 10,
	302	TPMA_NV_WRITELOCKED = 1UL << 11,
	303	TPMA_NV_WRITEALL = 1UL << 12,
	304	TPMA_NV_WRITEDEFINE = 1UL << 13,
	305	TPMA_NV_WRITE_STCLEAR = 1UL << 14,
	306	TPMA_NV_GLOBALLOCK = 1UL << 15,
	307	TPMA_NV_PPREAD = 1UL << 16,
	308	TPMA_NV_OWNERREAD = 1UL << 17,
	309	TPMA_NV_AUTHREAD = 1UL << 18,
	310	TPMA_NV_POLICYREAD = 1UL << 19,
	311	TPMA_NV_NO_DA = 1UL << 25,
	312	TPMA_NV_ORDERLY = 1UL << 26,
	313	TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
	314	TPMA_NV_READLOCKED = 1UL << 28,
	315	TPMA_NV_WRITTEN = 1UL << 29,
	316	TPMA_NV_PLATFORMCREATE = 1UL << 30,
	317	TPMA_NV_READ_STCLEAR = 1UL << 31,
	318
	319	TPMA_NV_MASK_READ = TPMA_NV_PPREAD \| TPMA_NV_OWNERREAD \|
	320	TPMA_NV_AUTHREAD \| TPMA_NV_POLICYREAD,
	321	TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE \| TPMA_NV_OWNERWRITE \|
	322	TPMA_NV_AUTHWRITE \| TPMA_NV_POLICYWRITE,
	323	};
	324
1400a7f3 SG	325	enum {
	326	TPM_ACCESS_VALID = 1 << 7,
	327	TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
	328	TPM_ACCESS_REQUEST_PENDING = 1 << 2,
	329	TPM_ACCESS_REQUEST_USE = 1 << 1,
	330	TPM_ACCESS_ESTABLISHMENT = 1 << 0,
	331	};
	332
	333	enum {
	334	TPM_STS_FAMILY_SHIFT = 26,
	335	TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
	336	TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
	337	TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
	338	TPM_STS_COMMAND_CANCEL = 1 << 24,
	339	TPM_STS_BURST_COUNT_SHIFT = 8,
	340	TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
	341	TPM_STS_VALID = 1 << 7,
	342	TPM_STS_COMMAND_READY = 1 << 6,
	343	TPM_STS_GO = 1 << 5,
	344	TPM_STS_DATA_AVAIL = 1 << 4,
	345	TPM_STS_DATA_EXPECT = 1 << 3,
	346	TPM_STS_SELF_TEST_DONE = 1 << 2,
	347	TPM_STS_RESPONSE_RETRY = 1 << 1,
	348	};
	349
	350	enum {
	351	TPM_CMD_COUNT_OFFSET = 2,
	352	TPM_CMD_ORDINAL_OFFSET = 6,
	353	TPM_MAX_BUF_SIZE = 1260,
	354	};
	355
1922df20 MR	356	/**
	357	* Issue a TPM2_Startup command.
	358	*
abdc7b8a	359	* @dev TPM device
1922df20 MR	360	* @mode TPM startup mode
	361	*
	362	* @return code of the operation
	363	*/
abdc7b8a	364	u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
1922df20	365
2dc6d97e MR	366	/**
	367	* Issue a TPM2_SelfTest command.
	368	*
abdc7b8a	369	* @dev TPM device
2dc6d97e MR	370	* @full_test Asking to perform all tests or only the untested ones
	371	*
	372	* @return code of the operation
	373	*/
abdc7b8a	374	u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
2dc6d97e	375
bad8ff56 MR	376	/**
	377	* Issue a TPM2_Clear command.
	378	*
abdc7b8a	379	* @dev TPM device
bad8ff56 MR	380	* @handle Handle
	381	* @pw Password
	382	* @pw_sz Length of the password
	383	*
	384	* @return code of the operation
	385	*/
abdc7b8a SG	386	u32 tpm2_clear(struct udevice dev, u32 handle, const char pw,
abdc7b8a SG	387	const ssize_t pw_sz);
bad8ff56	388
6284be5a MR	389	/**
	390	* Issue a TPM2_PCR_Extend command.
	391	*
abdc7b8a	392	* @dev TPM device
6284be5a	393	* @index Index of the PCR
e926136b	394	* @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
6284be5a	395	* @digest Value representing the event to be recorded
e926136b	396	* @digest_len len of the hash
6284be5a MR	397	*
	398	* @return code of the operation
	399	*/
e926136b IA	400	u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
e926136b IA	401	const u8 *digest, u32 digest_len);
6284be5a	402
1c4ea8f4 MR	403	/**
	404	* Issue a TPM2_PCR_Read command.
	405	*
abdc7b8a	406	* @dev TPM device
1c4ea8f4 MR	407	* @idx Index of the PCR
	408	* @idx_min_sz Minimum size in bytes of the pcrSelect array
	409	* @data Output buffer for contents of the named PCR
	410	* @updates Optional out parameter: number of updates for this PCR
	411	*
	412	* @return code of the operation
	413	*/
abdc7b8a SG	414	u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
abdc7b8a SG	415	void data, unsigned int updates);
1c4ea8f4	416
69cd8f06 MR	417	/**
	418	* Issue a TPM2_GetCapability command. This implementation is limited
	419	* to query property index that is 4-byte wide.
	420	*
abdc7b8a	421	* @dev TPM device
69cd8f06 MR	422	* @capability Partition of capabilities
	423	* @property Further definition of capability, limited to be 4 bytes wide
	424	* @buf Output buffer for capability information
	425	* @prop_count Size of output buffer
	426	*
	427	* @return code of the operation
	428	*/
abdc7b8a SG	429	u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
abdc7b8a SG	430	void *buf, size_t prop_count);
69cd8f06	431
da9c3392 MR	432	/**
	433	* Issue a TPM2_DictionaryAttackLockReset command.
	434	*
abdc7b8a	435	* @dev TPM device
da9c3392 MR	436	* @pw Password
	437	* @pw_sz Length of the password
	438	*
	439	* @return code of the operation
	440	*/
abdc7b8a	441	u32 tpm2_dam_reset(struct udevice dev, const char pw, const ssize_t pw_sz);
da9c3392 MR	442
	443	/**
	444	* Issue a TPM2_DictionaryAttackParameters command.
	445	*
abdc7b8a	446	* @dev TPM device
da9c3392 MR	447	* @pw Password
	448	* @pw_sz Length of the password
	449	* @max_tries Count of authorizations before lockout
	450	* @recovery_time Time before decrementation of the failure count
	451	* @lockout_recovery Time to wait after a lockout
	452	*
	453	* @return code of the operation
	454	*/
abdc7b8a SG	455	u32 tpm2_dam_parameters(struct udevice dev, const char pw,
	456	const ssize_t pw_sz, unsigned int max_tries,
	457	unsigned int recovery_time,
da9c3392 MR	458	unsigned int lockout_recovery);
da9c3392 MR	459
dc26e913 MR	460	/**
	461	* Issue a TPM2_HierarchyChangeAuth command.
	462	*
abdc7b8a	463	* @dev TPM device
dc26e913 MR	464	* @handle Handle
	465	* @newpw New password
	466	* @newpw_sz Length of the new password
	467	* @oldpw Old password
	468	* @oldpw_sz Length of the old password
	469	*
	470	* @return code of the operation
	471	*/
abdc7b8a SG	472	int tpm2_change_auth(struct udevice dev, u32 handle, const char newpw,
	473	const ssize_t newpw_sz, const char *oldpw,
	474	const ssize_t oldpw_sz);
dc26e913	475
b9dd4fab MR	476	/**
	477	* Issue a TPM_PCR_SetAuthPolicy command.
	478	*
abdc7b8a	479	* @dev TPM device
b9dd4fab MR	480	* @pw Platform password
	481	* @pw_sz Length of the password
	482	* @index Index of the PCR
	483	* @digest New key to access the PCR
	484	*
	485	* @return code of the operation
	486	*/
abdc7b8a SG	487	u32 tpm2_pcr_setauthpolicy(struct udevice dev, const char pw,
abdc7b8a SG	488	const ssize_t pw_sz, u32 index, const char *key);
b9dd4fab MR	489
	490	/**
	491	* Issue a TPM_PCR_SetAuthValue command.
	492	*
abdc7b8a	493	* @dev TPM device
b9dd4fab MR	494	* @pw Platform password
	495	* @pw_sz Length of the password
	496	* @index Index of the PCR
	497	* @digest New key to access the PCR
	498	* @key_sz Length of the new key
	499	*
	500	* @return code of the operation
	501	*/
abdc7b8a SG	502	u32 tpm2_pcr_setauthvalue(struct udevice dev, const char pw,
	503	const ssize_t pw_sz, u32 index, const char *key,
	504	const ssize_t key_sz);
b9dd4fab	505
06bea498 DP	506	/**
	507	* Issue a TPM2_GetRandom command.
	508	*
	509	* @dev TPM device
	510	* @param data output buffer for the random bytes
	511	* @param count size of output buffer
	512	*
	513	* @return return code of the operation
	514	*/
	515	u32 tpm2_get_random(struct udevice dev, void data, u32 count);
	516
ff32245b	517	#endif /* __TPM_V2_H */