[J-u-boot.git] / drivers / fpga / Makefile

# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2008
# Wolfgang Denk, DENX Software Engineering, [email protected].

obj-y += fpga.o
obj-$(CONFIG_DM_FPGA) += fpga-uclass.o
obj-$(CONFIG_SANDBOX_FPGA) += sandbox.o

obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
obj-$(CONFIG_FPGA_VERSALPL) += versalpl.o
obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
obj-$(CONFIG_FPGA_XILINX) += xilinx.o
obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
ifdef CONFIG_FPGA_ALTERA
obj-y += altera.o
obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
endif
Commit	Line	Data
83d290c5	1	# SPDX-License-Identifier: GPL-2.0+
c8aa7dfc JCPV	2	#
	3	# (C) Copyright 2008
	4	# Wolfgang Denk, DENX Software Engineering, [email protected].
c8aa7dfc	5
710f1d3d	6	obj-y += fpga.o
1323d08b AD	7	obj-$(CONFIG_DM_FPGA) += fpga-uclass.o
	8	obj-$(CONFIG_SANDBOX_FPGA) += sandbox.o
	9
710f1d3d MY	10	obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
710f1d3d MY	11	obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
26e054c9	12	obj-$(CONFIG_FPGA_VERSALPL) += versalpl.o
710f1d3d MY	13	obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
710f1d3d MY	14	obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
6b245014	15	obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
710f1d3d MY	16	obj-$(CONFIG_FPGA_XILINX) += xilinx.o
710f1d3d MY	17	obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
c8aa7dfc	18	ifdef CONFIG_FPGA_ALTERA
710f1d3d MY	19	obj-y += altera.o
	20	obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
	21	obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
d2170168	22	obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o
710f1d3d	23	obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
ff9c4c53	24	obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
230fe9b2	25	obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
6867e19a	26	obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
2baa9972	27	obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
c8aa7dfc	28	endif