[J-u-boot.git] / drivers / pci / pcie_fsl.c

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * Copyright 2019 NXP
 *
 * PCIe DM U-Boot driver for Freescale PowerPC SoCs
 * Author: Hou Zhiqiang <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <mapmem.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <linux/delay.h>
#include "pcie_fsl.h"
#include <dm/device_compat.h>

LIST_HEAD(fsl_pcie_list);

static int fsl_pcie_link_up(struct fsl_pcie *pcie);

static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
{
	struct udevice *bus = pcie->bus;

	if (!pcie->enabled)
		return -ENXIO;

	if (PCI_BUS(bdf) < bus->seq)
		return -EINVAL;

	if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))
		return -EINVAL;

	if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
		return -EINVAL;

	if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
		return -EINVAL;

	return 0;
}

static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
				uint offset, ulong *valuep,
				enum pci_size_t size)
{
	struct fsl_pcie *pcie = dev_get_priv(bus);
	ccsr_fsl_pci_t *regs = pcie->regs;
	u32 val;

	if (fsl_pcie_addr_valid(pcie, bdf)) {
		*valuep = pci_get_ff(size);
		return 0;
	}

	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
	val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
	out_be32(&regs->cfg_addr, val);

	sync();

	switch (size) {
	case PCI_SIZE_8:
		*valuep = in_8((u8 *)&regs->cfg_data + (offset & 3));
		break;
	case PCI_SIZE_16:
		*valuep = in_le16((u16 *)((u8 *)&regs->cfg_data +
			  (offset & 2)));
		break;
	case PCI_SIZE_32:
		*valuep = in_le32(&regs->cfg_data);
		break;
	}

	return 0;
}

static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
				 uint offset, ulong value,
				 enum pci_size_t size)
{
	struct fsl_pcie *pcie = dev_get_priv(bus);
	ccsr_fsl_pci_t *regs = pcie->regs;
	u32 val;
	u8 val_8;
	u16 val_16;
	u32 val_32;

	if (fsl_pcie_addr_valid(pcie, bdf))
		return 0;

	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
	val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
	out_be32(&regs->cfg_addr, val);

	sync();

	switch (size) {
	case PCI_SIZE_8:
		val_8 = value;
		out_8((u8 *)&regs->cfg_data + (offset & 3), val_8);
		break;
	case PCI_SIZE_16:
		val_16 = value;
		out_le16((u16 *)((u8 *)&regs->cfg_data + (offset & 2)), val_16);
		break;
	case PCI_SIZE_32:
		val_32 = value;
		out_le32(&regs->cfg_data, val_32);
		break;
	}

	return 0;
}

static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
				     ulong *valuep, enum pci_size_t size)
{
	int ret;
	struct udevice *bus = pcie->bus;

	ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
				   offset, valuep, size);

	return ret;
}

static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
				      ulong value, enum pci_size_t size)
{
	struct udevice *bus = pcie->bus;

	return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
				     offset, value, size);
}

static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
					  u8 *valuep)
{
	ulong val;
	int ret;

	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
	*valuep = val;

	return ret;
}

static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
					  u16 *valuep)
{
	ulong val;
	int ret;

	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
	*valuep = val;

	return ret;
}

static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
					   u32 *valuep)
{
	ulong val;
	int ret;

	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
	*valuep = val;

	return ret;
}

static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
					   u8 value)
{
	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
}

static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
					   u16 value)
{
	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
}

static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
					    u32 value)
{
	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
}

static int fsl_pcie_link_up(struct fsl_pcie *pcie)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	u16 ltssm;

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
		ltssm = (in_be32(&regs->pex_csr0)
			& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
		return ltssm == LTSSM_L0_REV3;
	}

	fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);

	return ltssm == LTSSM_L0;
}

static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
{
	u8 header_type;

	fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);

	return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
}

static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
{
	struct pci_region *io, *mem, *pref;

	pci_get_regions(pcie->bus, &io, &mem, &pref);

	if (mem)
		set_next_law(mem->phys_start,
			     law_size_bits(mem->size),
			     pcie->law_trgt_if);

	if (io)
		set_next_law(io->phys_start,
			     law_size_bits(io->size),
			     pcie->law_trgt_if);

	return 0;
}

static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
{
	ccsr_fsl_pci_t *regs = pcie->regs;

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
		setbits_be32(&regs->config, FSL_PCIE_V3_CFG_RDY);
		return;
	}

	fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
}

static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
				       int type, u64 phys, u64 bus_addr,
				       pci_size_t size)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	pot_t *po = &regs->pot[idx];
	u32 war, sz;

	if (idx < 0)
		return -EINVAL;

	out_be32(&po->powbar, phys >> 12);
	out_be32(&po->potar, bus_addr >> 12);
#ifdef CONFIG_SYS_PCI_64BIT
	out_be32(&po->potear, bus_addr >> 44);
#else
	out_be32(&po->potear, 0);
#endif

	sz = (__ilog2_u64((u64)size) - 1);
	war = POWAR_EN | sz;

	if (type == PCI_REGION_IO)
		war |= POWAR_IO_READ | POWAR_IO_WRITE;
	else
		war |= POWAR_MEM_READ | POWAR_MEM_WRITE;

	out_be32(&po->powar, war);

	return 0;
}

static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
				      bool pf, u64 phys, u64 bus_addr,
				      pci_size_t size)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	pit_t *pi = &regs->pit[idx];
	u32 sz = (__ilog2_u64(size) - 1);
	u32 flag = PIWAR_LOCAL;

	if (idx < 0)
		return -EINVAL;

	out_be32(&pi->pitar, phys >> 12);
	out_be32(&pi->piwbar, bus_addr >> 12);

#ifdef CONFIG_SYS_PCI_64BIT
	out_be32(&pi->piwbear, bus_addr >> 44);
#else
	out_be32(&pi->piwbear, 0);
#endif

#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
	flag = 0;
#endif

	flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
	if (pf)
		flag |= PIWAR_PF;
	out_be32(&pi->piwar, flag | sz);

	return 0;
}

static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
{
	struct pci_region *io, *mem, *pref;
	int idx = 1; /* skip 0 */

	pci_get_regions(pcie->bus, &io, &mem, &pref);

	if (io)
		/* ATU : OUTBOUND : IO */
		fsl_pcie_setup_outbound_win(pcie, idx++,
					    PCI_REGION_IO,
					    io->phys_start,
					    io->bus_start,
					    io->size);

	if (mem)
		/* ATU : OUTBOUND : MEM */
		fsl_pcie_setup_outbound_win(pcie, idx++,
					    PCI_REGION_MEM,
					    mem->phys_start,
					    mem->bus_start,
					    mem->size);
	return 0;
}

static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
{
	phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
	pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
	u64 sz = min((u64)gd->ram_size, (1ull << 32));
	pci_size_t pci_sz;
	int idx;

	if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
		idx = 2;
	else
		idx = 3;

	pci_sz = 1ull << __ilog2_u64(sz);

	dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
		(u64)bus_start, (u64)phys_start, (u64)sz);

	/* if we aren't an exact power of two match, pci_sz is smaller
	 * round it up to the next power of two.  We report the actual
	 * size to pci region tracking.
	 */
	if (pci_sz != sz)
		sz = 2ull << __ilog2_u64(sz);

	fsl_pcie_setup_inbound_win(pcie, idx--, true,
				   CONFIG_SYS_PCI_MEMORY_PHYS,
				   CONFIG_SYS_PCI_MEMORY_BUS, sz);
#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
	/*
	 * On 64-bit capable systems, set up a mapping for all of DRAM
	 * in high pci address space.
	 */
	pci_sz = 1ull << __ilog2_u64(gd->ram_size);
	/* round up to the next largest power of two */
	if (gd->ram_size > pci_sz)
		pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);

	dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
		(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
		(u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);

	fsl_pcie_setup_inbound_win(pcie, idx--, true,
				   CONFIG_SYS_PCI_MEMORY_PHYS,
				   CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
#endif

	return 0;
}

static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
{
	fsl_pcie_setup_outbound_wins(pcie);
	fsl_pcie_setup_inbound_wins(pcie);

	return 0;
}

static int fsl_pcie_init_port(struct fsl_pcie *pcie)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	u32 val_32;
	u16 val_16;

	fsl_pcie_init_atmu(pcie);

#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
	val_32 = 0;
	fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
	val_32 &= ~0x03;
	fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
	udelay(1);
#endif

#ifdef CONFIG_FSL_PCIE_RESET
	u16 ltssm;
	int i;

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
		/* assert PCIe reset */
		setbits_be32(&regs->pdb_stat, 0x08000000);
		(void)in_be32(&regs->pdb_stat);
		udelay(1000);
		/* clear PCIe reset */
		clrbits_be32(&regs->pdb_stat, 0x08000000);
		asm("sync;isync");
		for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
			udelay(1000);
	} else {
		fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
		if (ltssm == 1) {
			/* assert PCIe reset */
			setbits_be32(&regs->pdb_stat, 0x08000000);
			(void)in_be32(&regs->pdb_stat);
			udelay(100);
			/* clear PCIe reset */
			clrbits_be32(&regs->pdb_stat, 0x08000000);
			asm("sync;isync");
			for (i = 0; i < 100 &&
			     !fsl_pcie_link_up(pcie); i++)
				udelay(1000);
		}
	}
#endif

#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
	if (!fsl_pcie_link_up(pcie)) {
		serdes_corenet_t *srds_regs;

		srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
		val_32 = in_be32(&srds_regs->srdspccr0);

		if ((val_32 >> 28) == 3) {
			int i;

			out_be32(&srds_regs->srdspccr0, 2 << 28);
			setbits_be32(&regs->pdb_stat, 0x08000000);
			in_be32(&regs->pdb_stat);
			udelay(100);
			clrbits_be32(&regs->pdb_stat, 0x08000000);
			asm("sync;isync");
			for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
				udelay(1000);
		}
	}
#endif

	/*
	 * The Read-Only Write Enable bit defaults to 1 instead of 0.
	 * Set to 0 to protect the read-only registers.
	 */
#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
	clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
#endif

	/*
	 * Enable All Error Interrupts except
	 * - Master abort (pci)
	 * - Master PERR (pci)
	 * - ICCA (PCIe)
	 */
	out_be32(&regs->peer, ~0x20140);

	/* set URR, FER, NFER (but not CER) */
	fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
	val_32 |= 0xf000e;
	fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);

	/* Clear all error indications */
	out_be32(&regs->pme_msg_det, 0xffffffff);
	out_be32(&regs->pme_msg_int_en, 0xffffffff);
	out_be32(&regs->pedr, 0xffffffff);

	fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
	if (val_16)
		fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);

	fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
	if (val_16)
		fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);

	return 0;
}

static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	u32 classcode_reg;
	u32 val;

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
		classcode_reg = PCI_CLASS_REVISION;
		setbits_be32(&regs->dbi_ro_wr_en, 0x01);
	} else {
		classcode_reg = CSR_CLASSCODE;
	}

	fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
	val &= 0xff;
	val |= PCI_CLASS_BRIDGE_PCI << 16;
	fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
		clrbits_be32(&regs->dbi_ro_wr_en, 0x01);

	return 0;
}

static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
{
	return fsl_pcie_fixup_classcode(pcie);
}

static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
{
	fsl_pcie_config_ready(pcie);

	return 0;
}

static int fsl_pcie_probe(struct udevice *dev)
{
	struct fsl_pcie *pcie = dev_get_priv(dev);
	ccsr_fsl_pci_t *regs = pcie->regs;
	u16 val_16;

	pcie->bus = dev;
	pcie->block_rev = in_be32(&regs->block_rev1);

	list_add(&pcie->list, &fsl_pcie_list);
	pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
	if (!pcie->enabled) {
		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
		return 0;
	}

	fsl_pcie_setup_law(pcie);

	pcie->mode = fsl_pcie_is_agent(pcie);

	fsl_pcie_init_port(pcie);

	printf("PCIe%d: %s ", pcie->idx, dev->name);

	if (pcie->mode) {
		printf("Endpoint");
		fsl_pcie_init_ep(pcie);
	} else {
		printf("Root Complex");
		fsl_pcie_init_rc(pcie);
	}

	if (!fsl_pcie_link_up(pcie)) {
		printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
		return 0;
	}

	fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
	printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));

	return 0;
}

static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
{
	struct fsl_pcie *pcie = dev_get_priv(dev);
	struct fsl_pcie_data *info;
	int ret;

	pcie->regs = dev_remap_addr(dev);
	if (!pcie->regs) {
		pr_err("\"reg\" resource not found\n");
		return -EINVAL;
	}

	ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
	if (ret < 0) {
		pr_err("\"law_trgt_if\" not found\n");
		return ret;
	}

	info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
	pcie->info = info;
	pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
		    info->block_offset) / info->stride;

	return 0;
}

static const struct dm_pci_ops fsl_pcie_ops = {
	.read_config	= fsl_pcie_read_config,
	.write_config	= fsl_pcie_write_config,
};

static struct fsl_pcie_data p1_p2_data = {
	.block_offset = 0xa000,
	.block_offset_mask = 0xffff,
	.stride = 0x1000,
};

static struct fsl_pcie_data p2041_data = {
	.block_offset = 0x200000,
	.block_offset_mask = 0x3fffff,
	.stride = 0x1000,
};

static struct fsl_pcie_data t2080_data = {
	.block_offset = 0x240000,
	.block_offset_mask = 0x3fffff,
	.stride = 0x10000,
};

static const struct udevice_id fsl_pcie_ids[] = {
	{ .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
	{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
	{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
	{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
	{ .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
	{ .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
	{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
	{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
	{ .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
	{ }
};

U_BOOT_DRIVER(fsl_pcie) = {
	.name = "fsl_pcie",
	.id = UCLASS_PCI,
	.of_match = fsl_pcie_ids,
	.ops = &fsl_pcie_ops,
	.ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
	.probe = fsl_pcie_probe,
	.priv_auto_alloc_size = sizeof(struct fsl_pcie),
};
Commit	Line	Data
b89e3d92 HZ	1	// SPDX-License-Identifier: GPL-2.0+ OR X11
	2	/*
	3	* Copyright 2019 NXP
	4	*
	5	* PCIe DM U-Boot driver for Freescale PowerPC SoCs
	6	* Author: Hou Zhiqiang <[email protected]>
	7	*/
	8
	9	#include <common.h>
	10	#include <dm.h>
	11	#include <malloc.h>
	12	#include <mapmem.h>
	13	#include <pci.h>
	14	#include <asm/fsl_pci.h>
	15	#include <asm/fsl_serdes.h>
	16	#include <asm/io.h>
c05ed00a	17	#include <linux/delay.h>
b89e3d92	18	#include "pcie_fsl.h"
336d4615	19	#include <dm/device_compat.h>
b89e3d92 HZ	20
	21	LIST_HEAD(fsl_pcie_list);
	22
	23	static int fsl_pcie_link_up(struct fsl_pcie *pcie);
	24
	25	static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
	26	{
	27	struct udevice *bus = pcie->bus;
	28
	29	if (!pcie->enabled)
	30	return -ENXIO;
	31
	32	if (PCI_BUS(bdf) < bus->seq)
	33	return -EINVAL;
	34
	35	if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) \|\| pcie->mode))
	36	return -EINVAL;
	37
	38	if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 \|\| PCI_FUNC(bdf) > 0))
	39	return -EINVAL;
	40
	41	if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
	42	return -EINVAL;
	43
	44	return 0;
	45	}
	46
c4e72c4a	47	static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
b89e3d92 HZ	48	uint offset, ulong *valuep,
	49	enum pci_size_t size)
	50	{
	51	struct fsl_pcie *pcie = dev_get_priv(bus);
	52	ccsr_fsl_pci_t *regs = pcie->regs;
	53	u32 val;
	54
	55	if (fsl_pcie_addr_valid(pcie, bdf)) {
	56	*valuep = pci_get_ff(size);
	57	return 0;
	58	}
	59
	60	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
	61	val = bdf \| (offset & 0xfc) \| ((offset & 0xf00) << 16) \| 0x80000000;
	62	out_be32(&regs->cfg_addr, val);
	63
	64	sync();
	65
	66	switch (size) {
	67	case PCI_SIZE_8:
	68	valuep = in_8((u8 )&regs->cfg_data + (offset & 3));
	69	break;
	70	case PCI_SIZE_16:
	71	valuep = in_le16((u16 )((u8 *)&regs->cfg_data +
	72	(offset & 2)));
	73	break;
	74	case PCI_SIZE_32:
	75	*valuep = in_le32(&regs->cfg_data);
	76	break;
	77	}
	78
	79	return 0;
	80	}
	81
	82	static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
	83	uint offset, ulong value,
	84	enum pci_size_t size)
	85	{
	86	struct fsl_pcie *pcie = dev_get_priv(bus);
	87	ccsr_fsl_pci_t *regs = pcie->regs;
	88	u32 val;
	89	u8 val_8;
	90	u16 val_16;
	91	u32 val_32;
	92
	93	if (fsl_pcie_addr_valid(pcie, bdf))
	94	return 0;
	95
	96	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
	97	val = bdf \| (offset & 0xfc) \| ((offset & 0xf00) << 16) \| 0x80000000;
	98	out_be32(&regs->cfg_addr, val);
	99
	100	sync();
	101
	102	switch (size) {
	103	case PCI_SIZE_8:
	104	val_8 = value;
	105	out_8((u8 *)&regs->cfg_data + (offset & 3), val_8);
	106	break;
	107	case PCI_SIZE_16:
	108	val_16 = value;
	109	out_le16((u16 )((u8 )&regs->cfg_data + (offset & 2)), val_16);
	110	break;
	111	case PCI_SIZE_32:
112	val_32 = value;
113	out_le32(&regs->cfg_data, val_32);
114	break;
115	}
116
117	return 0;
118	}
119
120	static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
121	ulong *valuep, enum pci_size_t size)
122	{
123	int ret;
124	struct udevice *bus = pcie->bus;
125
126	ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
127	offset, valuep, size);
128
129	return ret;
130	}
131
132	static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
133	ulong value, enum pci_size_t size)
134	{
135	struct udevice *bus = pcie->bus;
136
137	return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
138	offset, value, size);
139	}
140
141	static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
142	u8 *valuep)
143	{
144	ulong val;
145	int ret;
146
147	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
148	*valuep = val;
149
150	return ret;
151	}
152
153	static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
154	u16 *valuep)
155	{
156	ulong val;
157	int ret;
158
159	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
160	*valuep = val;
161
162	return ret;
163	}
164
165	static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
166	u32 *valuep)
167	{
168	ulong val;
169	int ret;
170
171	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
172	*valuep = val;
173
174	return ret;
175	}
176
177	static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
178	u8 value)
179	{
180	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
181	}
182
183	static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
184	u16 value)
185	{
186	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
187	}
188
189	static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
190	u32 value)
191	{
192	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
193	}
194
195	static int fsl_pcie_link_up(struct fsl_pcie *pcie)
196	{
197	ccsr_fsl_pci_t *regs = pcie->regs;
198	u16 ltssm;
199
200	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
201	ltssm = (in_be32(&regs->pex_csr0)
202	& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
203	return ltssm == LTSSM_L0_REV3;
204	}
205
206	fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
207
208	return ltssm == LTSSM_L0;
209	}
210
211	static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
212	{
213	u8 header_type;
214
215	fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
216
217	return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
218	}
219
220	static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
221	{
222	struct pci_region io, mem, *pref;
223
224	pci_get_regions(pcie->bus, &io, &mem, &pref);
225
226	if (mem)
227	set_next_law(mem->phys_start,
228	law_size_bits(mem->size),
229	pcie->law_trgt_if);
230
231	if (io)
232	set_next_law(io->phys_start,
233	law_size_bits(io->size),
234	pcie->law_trgt_if);
235
236	return 0;
237	}
238
239	static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
240	{
241	ccsr_fsl_pci_t *regs = pcie->regs;
242
243	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
244	setbits_be32(&regs->config, FSL_PCIE_V3_CFG_RDY);
245	return;
246	}
247
248	fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
249	}
250
251	static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
252	int type, u64 phys, u64 bus_addr,
253	pci_size_t size)
254	{
255	ccsr_fsl_pci_t *regs = pcie->regs;
256	pot_t *po = &regs->pot[idx];
257	u32 war, sz;
258
259	if (idx < 0)
260	return -EINVAL;
261
262	out_be32(&po->powbar, phys >> 12);
263	out_be32(&po->potar, bus_addr >> 12);
264	#ifdef CONFIG_SYS_PCI_64BIT
265	out_be32(&po->potear, bus_addr >> 44);
266	#else
267	out_be32(&po->potear, 0);
268	#endif
269
270	sz = (__ilog2_u64((u64)size) - 1);
271	war = POWAR_EN \| sz;
272
273	if (type == PCI_REGION_IO)
274	war \|= POWAR_IO_READ \| POWAR_IO_WRITE;
275	else
276	war \|= POWAR_MEM_READ \| POWAR_MEM_WRITE;
277
278	out_be32(&po->powar, war);
279
280	return 0;
281	}
282
283	static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
284	bool pf, u64 phys, u64 bus_addr,
285	pci_size_t size)
286	{
287	ccsr_fsl_pci_t *regs = pcie->regs;
288	pit_t *pi = &regs->pit[idx];
289	u32 sz = (__ilog2_u64(size) - 1);
290	u32 flag = PIWAR_LOCAL;
291
292	if (idx < 0)
293	return -EINVAL;
294
295	out_be32(&pi->pitar, phys >> 12);
296	out_be32(&pi->piwbar, bus_addr >> 12);
297
298	#ifdef CONFIG_SYS_PCI_64BIT
299	out_be32(&pi->piwbear, bus_addr >> 44);
300	#else
301	out_be32(&pi->piwbear, 0);
302	#endif
303
adc983b4 HZ	304	#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
	305	flag = 0;
	306	#endif
b89e3d92 HZ	307
	308	flag \|= PIWAR_EN \| PIWAR_READ_SNOOP \| PIWAR_WRITE_SNOOP;
	309	if (pf)
	310	flag \|= PIWAR_PF;
	311	out_be32(&pi->piwar, flag \| sz);
	312
	313	return 0;
	314	}
	315
	316	static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
	317	{
	318	struct pci_region io, mem, *pref;
	319	int idx = 1; /* skip 0 */
	320
	321	pci_get_regions(pcie->bus, &io, &mem, &pref);
	322
	323	if (io)
	324	/* ATU : OUTBOUND : IO */
	325	fsl_pcie_setup_outbound_win(pcie, idx++,
	326	PCI_REGION_IO,
	327	io->phys_start,
	328	io->bus_start,
	329	io->size);
	330
	331	if (mem)
	332	/* ATU : OUTBOUND : MEM */
	333	fsl_pcie_setup_outbound_win(pcie, idx++,
	334	PCI_REGION_MEM,
	335	mem->phys_start,
	336	mem->bus_start,
	337	mem->size);
	338	return 0;
	339	}
	340
	341	static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
	342	{
	343	phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
	344	pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
	345	u64 sz = min((u64)gd->ram_size, (1ull << 32));
	346	pci_size_t pci_sz;
	347	int idx;
	348
	349	if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
	350	idx = 2;
	351	else
	352	idx = 3;
	353
	354	pci_sz = 1ull << __ilog2_u64(sz);
	355
	356	dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
	357	(u64)bus_start, (u64)phys_start, (u64)sz);
	358
	359	/* if we aren't an exact power of two match, pci_sz is smaller
	360	* round it up to the next power of two. We report the actual
	361	* size to pci region tracking.
	362	*/
	363	if (pci_sz != sz)
	364	sz = 2ull << __ilog2_u64(sz);
	365
	366	fsl_pcie_setup_inbound_win(pcie, idx--, true,
	367	CONFIG_SYS_PCI_MEMORY_PHYS,
	368	CONFIG_SYS_PCI_MEMORY_BUS, sz);
	369	#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
	370	/*
371	* On 64-bit capable systems, set up a mapping for all of DRAM
372	* in high pci address space.
373	*/
374	pci_sz = 1ull << __ilog2_u64(gd->ram_size);
375	/* round up to the next largest power of two */
376	if (gd->ram_size > pci_sz)
377	pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
378
379	dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
380	(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
381	(u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
382
383	fsl_pcie_setup_inbound_win(pcie, idx--, true,
384	CONFIG_SYS_PCI_MEMORY_PHYS,
385	CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
386	#endif
387
388	return 0;
389	}
390
391	static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
392	{
393	fsl_pcie_setup_outbound_wins(pcie);
394	fsl_pcie_setup_inbound_wins(pcie);
395
396	return 0;
397	}
398
399	static int fsl_pcie_init_port(struct fsl_pcie *pcie)
400	{
401	ccsr_fsl_pci_t *regs = pcie->regs;
402	u32 val_32;
403	u16 val_16;
404
405	fsl_pcie_init_atmu(pcie);
406
adc983b4 HZ	407	#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
	408	val_32 = 0;
	409	fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
	410	val_32 &= ~0x03;
	411	fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
	412	udelay(1);
	413	#endif
b89e3d92	414
adc983b4 HZ	415	#ifdef CONFIG_FSL_PCIE_RESET
	416	u16 ltssm;
	417	int i;
b89e3d92	418
adc983b4 HZ	419	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
	420	/* assert PCIe reset */
	421	setbits_be32(&regs->pdb_stat, 0x08000000);
	422	(void)in_be32(&regs->pdb_stat);
	423	udelay(1000);
	424	/* clear PCIe reset */
	425	clrbits_be32(&regs->pdb_stat, 0x08000000);
	426	asm("sync;isync");
	427	for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
	428	udelay(1000);
	429	} else {
	430	fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
	431	if (ltssm == 1) {
b89e3d92 HZ	432	/* assert PCIe reset */
	433	setbits_be32(&regs->pdb_stat, 0x08000000);
	434	(void)in_be32(&regs->pdb_stat);
adc983b4	435	udelay(100);
b89e3d92 HZ	436	/* clear PCIe reset */
	437	clrbits_be32(&regs->pdb_stat, 0x08000000);
	438	asm("sync;isync");
adc983b4 HZ	439	for (i = 0; i < 100 &&
adc983b4 HZ	440	!fsl_pcie_link_up(pcie); i++)
b89e3d92	441	udelay(1000);
b89e3d92 HZ	442	}
b89e3d92 HZ	443	}
adc983b4	444	#endif
b89e3d92	445
adc983b4 HZ	446	#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
adc983b4 HZ	447	if (!fsl_pcie_link_up(pcie)) {
b89e3d92 HZ	448	serdes_corenet_t *srds_regs;
	449
	450	srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
	451	val_32 = in_be32(&srds_regs->srdspccr0);
	452
	453	if ((val_32 >> 28) == 3) {
	454	int i;
	455
	456	out_be32(&srds_regs->srdspccr0, 2 << 28);
	457	setbits_be32(&regs->pdb_stat, 0x08000000);
	458	in_be32(&regs->pdb_stat);
	459	udelay(100);
	460	clrbits_be32(&regs->pdb_stat, 0x08000000);
	461	asm("sync;isync");
	462	for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
	463	udelay(1000);
	464	}
	465	}
adc983b4	466	#endif
b89e3d92 HZ	467
	468	/*
	469	* The Read-Only Write Enable bit defaults to 1 instead of 0.
	470	* Set to 0 to protect the read-only registers.
	471	*/
adc983b4 HZ	472	#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
	473	clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
	474	#endif
b89e3d92 HZ	475
	476	/*
	477	* Enable All Error Interrupts except
	478	* - Master abort (pci)
	479	* - Master PERR (pci)
	480	* - ICCA (PCIe)
	481	*/
	482	out_be32(&regs->peer, ~0x20140);
	483
	484	/* set URR, FER, NFER (but not CER) */
	485	fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
	486	val_32 \|= 0xf000e;
	487	fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
	488
	489	/* Clear all error indications */
	490	out_be32(&regs->pme_msg_det, 0xffffffff);
	491	out_be32(&regs->pme_msg_int_en, 0xffffffff);
	492	out_be32(&regs->pedr, 0xffffffff);
	493
	494	fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
	495	if (val_16)
	496	fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
	497
	498	fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
	499	if (val_16)
	500	fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
	501
	502	return 0;
	503	}
	504
	505	static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
	506	{
	507	ccsr_fsl_pci_t *regs = pcie->regs;
d18d06ac	508	u32 classcode_reg;
b89e3d92 HZ	509	u32 val;
b89e3d92 HZ	510
d18d06ac HZ	511	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
	512	classcode_reg = PCI_CLASS_REVISION;
	513	setbits_be32(&regs->dbi_ro_wr_en, 0x01);
	514	} else {
	515	classcode_reg = CSR_CLASSCODE;
	516	}
	517
	518	fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
b89e3d92 HZ	519	val &= 0xff;
b89e3d92 HZ	520	val \|= PCI_CLASS_BRIDGE_PCI << 16;
d18d06ac HZ	521	fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
	522
	523	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
	524	clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
b89e3d92 HZ	525
	526	return 0;
	527	}
	528
	529	static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
	530	{
	531	return fsl_pcie_fixup_classcode(pcie);
	532	}
	533
	534	static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
	535	{
	536	fsl_pcie_config_ready(pcie);
	537
	538	return 0;
	539	}
	540
	541	static int fsl_pcie_probe(struct udevice *dev)
	542	{
	543	struct fsl_pcie *pcie = dev_get_priv(dev);
	544	ccsr_fsl_pci_t *regs = pcie->regs;
	545	u16 val_16;
	546
	547	pcie->bus = dev;
	548	pcie->block_rev = in_be32(&regs->block_rev1);
	549
	550	list_add(&pcie->list, &fsl_pcie_list);
	551	pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
	552	if (!pcie->enabled) {
	553	printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
	554	return 0;
	555	}
	556
	557	fsl_pcie_setup_law(pcie);
	558
	559	pcie->mode = fsl_pcie_is_agent(pcie);
	560
	561	fsl_pcie_init_port(pcie);
	562
	563	printf("PCIe%d: %s ", pcie->idx, dev->name);
	564
	565	if (pcie->mode) {
	566	printf("Endpoint");
	567	fsl_pcie_init_ep(pcie);
	568	} else {
	569	printf("Root Complex");
	570	fsl_pcie_init_rc(pcie);
	571	}
	572
	573	if (!fsl_pcie_link_up(pcie)) {
	574	printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
	575	return 0;
	576	}
	577
	578	fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
	579	printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
	580
	581	return 0;
	582	}
	583
	584	static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
	585	{
	586	struct fsl_pcie *pcie = dev_get_priv(dev);
fbcb2ff5	587	struct fsl_pcie_data *info;
b89e3d92 HZ	588	int ret;
	589
	590	pcie->regs = dev_remap_addr(dev);
	591	if (!pcie->regs) {
	592	pr_err("\"reg\" resource not found\n");
	593	return -EINVAL;
	594	}
	595
	596	ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
	597	if (ret < 0) {
	598	pr_err("\"law_trgt_if\" not found\n");
	599	return ret;
	600	}
	601
fbcb2ff5 HZ	602	info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
	603	pcie->info = info;
	604	pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
	605	info->block_offset) / info->stride;
b89e3d92 HZ	606
	607	return 0;
	608	}
	609
	610	static const struct dm_pci_ops fsl_pcie_ops = {
	611	.read_config = fsl_pcie_read_config,
	612	.write_config = fsl_pcie_write_config,
	613	};
	614
ba827365 HZ	615	static struct fsl_pcie_data p1_p2_data = {
	616	.block_offset = 0xa000,
	617	.block_offset_mask = 0xffff,
	618	.stride = 0x1000,
	619	};
	620
1a92802e HZ	621	static struct fsl_pcie_data p2041_data = {
	622	.block_offset = 0x200000,
	623	.block_offset_mask = 0x3fffff,
	624	.stride = 0x1000,
	625	};
	626
fbcb2ff5 HZ	627	static struct fsl_pcie_data t2080_data = {
	628	.block_offset = 0x240000,
	629	.block_offset_mask = 0x3fffff,
	630	.stride = 0x10000,
	631	};
	632
b89e3d92	633	static const struct udevice_id fsl_pcie_ids[] = {
92e025c6	634	{ .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
ba827365	635	{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
1a92802e	636	{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
096d5f80	637	{ .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
7b7e4e1b	638	{ .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
52744596	639	{ .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
a8c79f61	640	{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
4392ddbb	641	{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
fbcb2ff5	642	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
9acc038b	643	{ .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
b89e3d92 HZ	644	{ }
	645	};
	646
	647	U_BOOT_DRIVER(fsl_pcie) = {
	648	.name = "fsl_pcie",
	649	.id = UCLASS_PCI,
	650	.of_match = fsl_pcie_ids,
	651	.ops = &fsl_pcie_ops,
	652	.ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
	653	.probe = fsl_pcie_probe,
	654	.priv_auto_alloc_size = sizeof(struct fsl_pcie),
	655	};