[J-u-boot.git] / drivers / pci / pcie_fsl.c

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * Copyright 2019 NXP
 *
 * PCIe DM U-Boot driver for Freescale PowerPC SoCs
 * Author: Hou Zhiqiang <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <mapmem.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include "pcie_fsl.h"

LIST_HEAD(fsl_pcie_list);

static int fsl_pcie_link_up(struct fsl_pcie *pcie);

static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
{
	struct udevice *bus = pcie->bus;

	if (!pcie->enabled)
		return -ENXIO;

	if (PCI_BUS(bdf) < bus->seq)
		return -EINVAL;

	if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))
		return -EINVAL;

	if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
		return -EINVAL;

	if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
		return -EINVAL;

	return 0;
}

static int fsl_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
				uint offset, ulong *valuep,
				enum pci_size_t size)
{
	struct fsl_pcie *pcie = dev_get_priv(bus);
	ccsr_fsl_pci_t *regs = pcie->regs;
	u32 val;

	if (fsl_pcie_addr_valid(pcie, bdf)) {
		*valuep = pci_get_ff(size);
		return 0;
	}

	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
	val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
	out_be32(&regs->cfg_addr, val);

	sync();

	switch (size) {
	case PCI_SIZE_8:
		*valuep = in_8((u8 *)&regs->cfg_data + (offset & 3));
		break;
	case PCI_SIZE_16:
		*valuep = in_le16((u16 *)((u8 *)&regs->cfg_data +
			  (offset & 2)));
		break;
	case PCI_SIZE_32:
		*valuep = in_le32(&regs->cfg_data);
		break;
	}

	return 0;
}

static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
				 uint offset, ulong value,
				 enum pci_size_t size)
{
	struct fsl_pcie *pcie = dev_get_priv(bus);
	ccsr_fsl_pci_t *regs = pcie->regs;
	u32 val;
	u8 val_8;
	u16 val_16;
	u32 val_32;

	if (fsl_pcie_addr_valid(pcie, bdf))
		return 0;

	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
	val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
	out_be32(&regs->cfg_addr, val);

	sync();

	switch (size) {
	case PCI_SIZE_8:
		val_8 = value;
		out_8((u8 *)&regs->cfg_data + (offset & 3), val_8);
		break;
	case PCI_SIZE_16:
		val_16 = value;
		out_le16((u16 *)((u8 *)&regs->cfg_data + (offset & 2)), val_16);
		break;
	case PCI_SIZE_32:
		val_32 = value;
		out_le32(&regs->cfg_data, val_32);
		break;
	}

	return 0;
}

static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
				     ulong *valuep, enum pci_size_t size)
{
	int ret;
	struct udevice *bus = pcie->bus;

	ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
				   offset, valuep, size);

	return ret;
}

static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
				      ulong value, enum pci_size_t size)
{
	struct udevice *bus = pcie->bus;

	return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
				     offset, value, size);
}

static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
					  u8 *valuep)
{
	ulong val;
	int ret;

	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
	*valuep = val;

	return ret;
}

static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
					  u16 *valuep)
{
	ulong val;
	int ret;

	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
	*valuep = val;

	return ret;
}

static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
					   u32 *valuep)
{
	ulong val;
	int ret;

	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
	*valuep = val;

	return ret;
}

static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
					   u8 value)
{
	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
}

static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
					   u16 value)
{
	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
}

static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
					    u32 value)
{
	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
}

static int fsl_pcie_link_up(struct fsl_pcie *pcie)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	u16 ltssm;

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
		ltssm = (in_be32(&regs->pex_csr0)
			& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
		return ltssm == LTSSM_L0_REV3;
	}

	fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);

	return ltssm == LTSSM_L0;
}

static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
{
	u8 header_type;

	fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);

	return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
}

static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
{
	struct pci_region *io, *mem, *pref;

	pci_get_regions(pcie->bus, &io, &mem, &pref);

	if (mem)
		set_next_law(mem->phys_start,
			     law_size_bits(mem->size),
			     pcie->law_trgt_if);

	if (io)
		set_next_law(io->phys_start,
			     law_size_bits(io->size),
			     pcie->law_trgt_if);

	return 0;
}

static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
{
	ccsr_fsl_pci_t *regs = pcie->regs;

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
		setbits_be32(&regs->config, FSL_PCIE_V3_CFG_RDY);
		return;
	}

	fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
}

static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
				       int type, u64 phys, u64 bus_addr,
				       pci_size_t size)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	pot_t *po = &regs->pot[idx];
	u32 war, sz;

	if (idx < 0)
		return -EINVAL;

	out_be32(&po->powbar, phys >> 12);
	out_be32(&po->potar, bus_addr >> 12);
#ifdef CONFIG_SYS_PCI_64BIT
	out_be32(&po->potear, bus_addr >> 44);
#else
	out_be32(&po->potear, 0);
#endif

	sz = (__ilog2_u64((u64)size) - 1);
	war = POWAR_EN | sz;

	if (type == PCI_REGION_IO)
		war |= POWAR_IO_READ | POWAR_IO_WRITE;
	else
		war |= POWAR_MEM_READ | POWAR_MEM_WRITE;

	out_be32(&po->powar, war);

	return 0;
}

static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
				      bool pf, u64 phys, u64 bus_addr,
				      pci_size_t size)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	pit_t *pi = &regs->pit[idx];
	u32 sz = (__ilog2_u64(size) - 1);
	u32 flag = PIWAR_LOCAL;

	if (idx < 0)
		return -EINVAL;

	out_be32(&pi->pitar, phys >> 12);
	out_be32(&pi->piwbar, bus_addr >> 12);

#ifdef CONFIG_SYS_PCI_64BIT
	out_be32(&pi->piwbear, bus_addr >> 44);
#else
	out_be32(&pi->piwbear, 0);
#endif

#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
	flag = 0;
#endif

	flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
	if (pf)
		flag |= PIWAR_PF;
	out_be32(&pi->piwar, flag | sz);

	return 0;
}

static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
{
	struct pci_region *io, *mem, *pref;
	int idx = 1; /* skip 0 */

	pci_get_regions(pcie->bus, &io, &mem, &pref);

	if (io)
		/* ATU : OUTBOUND : IO */
		fsl_pcie_setup_outbound_win(pcie, idx++,
					    PCI_REGION_IO,
					    io->phys_start,
					    io->bus_start,
					    io->size);

	if (mem)
		/* ATU : OUTBOUND : MEM */
		fsl_pcie_setup_outbound_win(pcie, idx++,
					    PCI_REGION_MEM,
					    mem->phys_start,
					    mem->bus_start,
					    mem->size);
	return 0;
}

static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
{
	phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
	pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
	u64 sz = min((u64)gd->ram_size, (1ull << 32));
	pci_size_t pci_sz;
	int idx;

	if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
		idx = 2;
	else
		idx = 3;

	pci_sz = 1ull << __ilog2_u64(sz);

	dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
		(u64)bus_start, (u64)phys_start, (u64)sz);

	/* if we aren't an exact power of two match, pci_sz is smaller
	 * round it up to the next power of two.  We report the actual
	 * size to pci region tracking.
	 */
	if (pci_sz != sz)
		sz = 2ull << __ilog2_u64(sz);

	fsl_pcie_setup_inbound_win(pcie, idx--, true,
				   CONFIG_SYS_PCI_MEMORY_PHYS,
				   CONFIG_SYS_PCI_MEMORY_BUS, sz);
#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
	/*
	 * On 64-bit capable systems, set up a mapping for all of DRAM
	 * in high pci address space.
	 */
	pci_sz = 1ull << __ilog2_u64(gd->ram_size);
	/* round up to the next largest power of two */
	if (gd->ram_size > pci_sz)
		pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);

	dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
		(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
		(u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);

	fsl_pcie_setup_inbound_win(pcie, idx--, true,
				   CONFIG_SYS_PCI_MEMORY_PHYS,
				   CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
#endif

	return 0;
}

static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
{
	fsl_pcie_setup_outbound_wins(pcie);
	fsl_pcie_setup_inbound_wins(pcie);

	return 0;
}

static int fsl_pcie_init_port(struct fsl_pcie *pcie)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	u32 val_32;
	u16 val_16;

	fsl_pcie_init_atmu(pcie);

#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
	val_32 = 0;
	fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
	val_32 &= ~0x03;
	fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
	udelay(1);
#endif

#ifdef CONFIG_FSL_PCIE_RESET
	u16 ltssm;
	int i;

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
		/* assert PCIe reset */
		setbits_be32(&regs->pdb_stat, 0x08000000);
		(void)in_be32(&regs->pdb_stat);
		udelay(1000);
		/* clear PCIe reset */
		clrbits_be32(&regs->pdb_stat, 0x08000000);
		asm("sync;isync");
		for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
			udelay(1000);
	} else {
		fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
		if (ltssm == 1) {
			/* assert PCIe reset */
			setbits_be32(&regs->pdb_stat, 0x08000000);
			(void)in_be32(&regs->pdb_stat);
			udelay(100);
			/* clear PCIe reset */
			clrbits_be32(&regs->pdb_stat, 0x08000000);
			asm("sync;isync");
			for (i = 0; i < 100 &&
			     !fsl_pcie_link_up(pcie); i++)
				udelay(1000);
		}
	}
#endif

#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
	if (!fsl_pcie_link_up(pcie)) {
		serdes_corenet_t *srds_regs;

		srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
		val_32 = in_be32(&srds_regs->srdspccr0);

		if ((val_32 >> 28) == 3) {
			int i;

			out_be32(&srds_regs->srdspccr0, 2 << 28);
			setbits_be32(&regs->pdb_stat, 0x08000000);
			in_be32(&regs->pdb_stat);
			udelay(100);
			clrbits_be32(&regs->pdb_stat, 0x08000000);
			asm("sync;isync");
			for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
				udelay(1000);
		}
	}
#endif

	/*
	 * The Read-Only Write Enable bit defaults to 1 instead of 0.
	 * Set to 0 to protect the read-only registers.
	 */
#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
	clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
#endif

	/*
	 * Enable All Error Interrupts except
	 * - Master abort (pci)
	 * - Master PERR (pci)
	 * - ICCA (PCIe)
	 */
	out_be32(&regs->peer, ~0x20140);

	/* set URR, FER, NFER (but not CER) */
	fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
	val_32 |= 0xf000e;
	fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);

	/* Clear all error indications */
	out_be32(&regs->pme_msg_det, 0xffffffff);
	out_be32(&regs->pme_msg_int_en, 0xffffffff);
	out_be32(&regs->pedr, 0xffffffff);

	fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
	if (val_16)
		fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);

	fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
	if (val_16)
		fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);

	return 0;
}

static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
{
	ccsr_fsl_pci_t *regs = pcie->regs;
	u32 classcode_reg;
	u32 val;

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
		classcode_reg = PCI_CLASS_REVISION;
		setbits_be32(&regs->dbi_ro_wr_en, 0x01);
	} else {
		classcode_reg = CSR_CLASSCODE;
	}

	fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
	val &= 0xff;
	val |= PCI_CLASS_BRIDGE_PCI << 16;
	fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);

	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
		clrbits_be32(&regs->dbi_ro_wr_en, 0x01);

	return 0;
}

static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
{
	return fsl_pcie_fixup_classcode(pcie);
}

static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
{
	fsl_pcie_config_ready(pcie);

	return 0;
}

static int fsl_pcie_probe(struct udevice *dev)
{
	struct fsl_pcie *pcie = dev_get_priv(dev);
	ccsr_fsl_pci_t *regs = pcie->regs;
	u16 val_16;

	pcie->bus = dev;
	pcie->block_rev = in_be32(&regs->block_rev1);

	list_add(&pcie->list, &fsl_pcie_list);
	pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
	if (!pcie->enabled) {
		printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
		return 0;
	}

	fsl_pcie_setup_law(pcie);

	pcie->mode = fsl_pcie_is_agent(pcie);

	fsl_pcie_init_port(pcie);

	printf("PCIe%d: %s ", pcie->idx, dev->name);

	if (pcie->mode) {
		printf("Endpoint");
		fsl_pcie_init_ep(pcie);
	} else {
		printf("Root Complex");
		fsl_pcie_init_rc(pcie);
	}

	if (!fsl_pcie_link_up(pcie)) {
		printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
		return 0;
	}

	fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
	printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));

	return 0;
}

static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
{
	struct fsl_pcie *pcie = dev_get_priv(dev);
	struct fsl_pcie_data *info;
	int ret;

	pcie->regs = dev_remap_addr(dev);
	if (!pcie->regs) {
		pr_err("\"reg\" resource not found\n");
		return -EINVAL;
	}

	ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
	if (ret < 0) {
		pr_err("\"law_trgt_if\" not found\n");
		return ret;
	}

	info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
	pcie->info = info;
	pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
		    info->block_offset) / info->stride;

	return 0;
}

static const struct dm_pci_ops fsl_pcie_ops = {
	.read_config	= fsl_pcie_read_config,
	.write_config	= fsl_pcie_write_config,
};

static struct fsl_pcie_data p1_p2_data = {
	.block_offset = 0xa000,
	.block_offset_mask = 0xffff,
	.stride = 0x1000,
};

static struct fsl_pcie_data p2041_data = {
	.block_offset = 0x200000,
	.block_offset_mask = 0x3fffff,
	.stride = 0x1000,
};

static struct fsl_pcie_data t2080_data = {
	.block_offset = 0x240000,
	.block_offset_mask = 0x3fffff,
	.stride = 0x10000,
};

static const struct udevice_id fsl_pcie_ids[] = {
	{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
	{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
	{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
	{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
	{ .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
	{ }
};

U_BOOT_DRIVER(fsl_pcie) = {
	.name = "fsl_pcie",
	.id = UCLASS_PCI,
	.of_match = fsl_pcie_ids,
	.ops = &fsl_pcie_ops,
	.ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
	.probe = fsl_pcie_probe,
	.priv_auto_alloc_size = sizeof(struct fsl_pcie),
};
Commit	Line	Data
b89e3d92 HZ	1	// SPDX-License-Identifier: GPL-2.0+ OR X11
	2	/*
	3	* Copyright 2019 NXP
	4	*
	5	* PCIe DM U-Boot driver for Freescale PowerPC SoCs
	6	* Author: Hou Zhiqiang <[email protected]>
	7	*/
	8
	9	#include <common.h>
	10	#include <dm.h>
	11	#include <malloc.h>
	12	#include <mapmem.h>
	13	#include <pci.h>
	14	#include <asm/fsl_pci.h>
	15	#include <asm/fsl_serdes.h>
	16	#include <asm/io.h>
	17	#include "pcie_fsl.h"
	18
	19	LIST_HEAD(fsl_pcie_list);
	20
	21	static int fsl_pcie_link_up(struct fsl_pcie *pcie);
	22
	23	static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
	24	{
	25	struct udevice *bus = pcie->bus;
	26
	27	if (!pcie->enabled)
	28	return -ENXIO;
	29
	30	if (PCI_BUS(bdf) < bus->seq)
	31	return -EINVAL;
	32
	33	if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) \|\| pcie->mode))
	34	return -EINVAL;
	35
	36	if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 \|\| PCI_FUNC(bdf) > 0))
	37	return -EINVAL;
	38
	39	if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
	40	return -EINVAL;
	41
	42	return 0;
	43	}
	44
	45	static int fsl_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
	46	uint offset, ulong *valuep,
	47	enum pci_size_t size)
	48	{
	49	struct fsl_pcie *pcie = dev_get_priv(bus);
	50	ccsr_fsl_pci_t *regs = pcie->regs;
	51	u32 val;
	52
	53	if (fsl_pcie_addr_valid(pcie, bdf)) {
	54	*valuep = pci_get_ff(size);
	55	return 0;
	56	}
	57
	58	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
	59	val = bdf \| (offset & 0xfc) \| ((offset & 0xf00) << 16) \| 0x80000000;
	60	out_be32(&regs->cfg_addr, val);
	61
	62	sync();
	63
	64	switch (size) {
65	case PCI_SIZE_8:
66	valuep = in_8((u8 )&regs->cfg_data + (offset & 3));
67	break;
68	case PCI_SIZE_16:
69	valuep = in_le16((u16 )((u8 *)&regs->cfg_data +
70	(offset & 2)));
71	break;
72	case PCI_SIZE_32:
73	*valuep = in_le32(&regs->cfg_data);
74	break;
75	}
76
77	return 0;
78	}
79
80	static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
81	uint offset, ulong value,
82	enum pci_size_t size)
83	{
84	struct fsl_pcie *pcie = dev_get_priv(bus);
85	ccsr_fsl_pci_t *regs = pcie->regs;
86	u32 val;
87	u8 val_8;
88	u16 val_16;
89	u32 val_32;
90
91	if (fsl_pcie_addr_valid(pcie, bdf))
92	return 0;
93
94	bdf = bdf - PCI_BDF(bus->seq, 0, 0);
95	val = bdf \| (offset & 0xfc) \| ((offset & 0xf00) << 16) \| 0x80000000;
96	out_be32(&regs->cfg_addr, val);
97
98	sync();
99
100	switch (size) {
101	case PCI_SIZE_8:
102	val_8 = value;
103	out_8((u8 *)&regs->cfg_data + (offset & 3), val_8);
104	break;
105	case PCI_SIZE_16:
106	val_16 = value;
107	out_le16((u16 )((u8 )&regs->cfg_data + (offset & 2)), val_16);
108	break;
109	case PCI_SIZE_32:
110	val_32 = value;
111	out_le32(&regs->cfg_data, val_32);
112	break;
113	}
114
115	return 0;
116	}
117
118	static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
119	ulong *valuep, enum pci_size_t size)
120	{
121	int ret;
122	struct udevice *bus = pcie->bus;
123
124	ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
125	offset, valuep, size);
126
127	return ret;
128	}
129
130	static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
131	ulong value, enum pci_size_t size)
132	{
133	struct udevice *bus = pcie->bus;
134
135	return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
136	offset, value, size);
137	}
138
139	static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
140	u8 *valuep)
141	{
142	ulong val;
143	int ret;
144
145	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
146	*valuep = val;
147
148	return ret;
149	}
150
151	static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
152	u16 *valuep)
153	{
154	ulong val;
155	int ret;
156
157	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
158	*valuep = val;
159
160	return ret;
161	}
162
163	static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
164	u32 *valuep)
165	{
166	ulong val;
167	int ret;
168
169	ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
170	*valuep = val;
171
172	return ret;
173	}
174
175	static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
176	u8 value)
177	{
178	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
179	}
180
181	static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
182	u16 value)
183	{
184	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
185	}
186
187	static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
188	u32 value)
189	{
190	return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
191	}
192
193	static int fsl_pcie_link_up(struct fsl_pcie *pcie)
194	{
195	ccsr_fsl_pci_t *regs = pcie->regs;
196	u16 ltssm;
197
198	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
199	ltssm = (in_be32(&regs->pex_csr0)
200	& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
201	return ltssm == LTSSM_L0_REV3;
202	}
203
204	fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
205
206	return ltssm == LTSSM_L0;
207	}
208
209	static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
210	{
211	u8 header_type;
212
213	fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
214
215	return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
216	}
217
218	static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
219	{
220	struct pci_region io, mem, *pref;
221
222	pci_get_regions(pcie->bus, &io, &mem, &pref);
223
224	if (mem)
225	set_next_law(mem->phys_start,
226	law_size_bits(mem->size),
227	pcie->law_trgt_if);
228
229	if (io)
230	set_next_law(io->phys_start,
231	law_size_bits(io->size),
232	pcie->law_trgt_if);
233
234	return 0;
235	}
236
237	static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
238	{
239	ccsr_fsl_pci_t *regs = pcie->regs;
240
241	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
242	setbits_be32(&regs->config, FSL_PCIE_V3_CFG_RDY);
243	return;
244	}
245
246	fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
247	}
248
249	static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
250	int type, u64 phys, u64 bus_addr,
251	pci_size_t size)
252	{
253	ccsr_fsl_pci_t *regs = pcie->regs;
254	pot_t *po = &regs->pot[idx];
255	u32 war, sz;
256
257	if (idx < 0)
258	return -EINVAL;
259
260	out_be32(&po->powbar, phys >> 12);
261	out_be32(&po->potar, bus_addr >> 12);
262	#ifdef CONFIG_SYS_PCI_64BIT
263	out_be32(&po->potear, bus_addr >> 44);
264	#else
265	out_be32(&po->potear, 0);
266	#endif
267
268	sz = (__ilog2_u64((u64)size) - 1);
269	war = POWAR_EN \| sz;
270
271	if (type == PCI_REGION_IO)
272	war \|= POWAR_IO_READ \| POWAR_IO_WRITE;
273	else
274	war \|= POWAR_MEM_READ \| POWAR_MEM_WRITE;
275
276	out_be32(&po->powar, war);
277
278	return 0;
279	}
280
281	static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
282	bool pf, u64 phys, u64 bus_addr,
283	pci_size_t size)
284	{
285	ccsr_fsl_pci_t *regs = pcie->regs;
286	pit_t *pi = &regs->pit[idx];
287	u32 sz = (__ilog2_u64(size) - 1);
288	u32 flag = PIWAR_LOCAL;
289
290	if (idx < 0)
291	return -EINVAL;
292
293	out_be32(&pi->pitar, phys >> 12);
294	out_be32(&pi->piwbar, bus_addr >> 12);
295
296	#ifdef CONFIG_SYS_PCI_64BIT
297	out_be32(&pi->piwbear, bus_addr >> 44);
298	#else
299	out_be32(&pi->piwbear, 0);
300	#endif
301
adc983b4 HZ	302	#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
	303	flag = 0;
	304	#endif
b89e3d92 HZ	305
	306	flag \|= PIWAR_EN \| PIWAR_READ_SNOOP \| PIWAR_WRITE_SNOOP;
	307	if (pf)
	308	flag \|= PIWAR_PF;
	309	out_be32(&pi->piwar, flag \| sz);
	310
	311	return 0;
	312	}
	313
	314	static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
	315	{
	316	struct pci_region io, mem, *pref;
	317	int idx = 1; /* skip 0 */
	318
	319	pci_get_regions(pcie->bus, &io, &mem, &pref);
	320
	321	if (io)
	322	/* ATU : OUTBOUND : IO */
	323	fsl_pcie_setup_outbound_win(pcie, idx++,
	324	PCI_REGION_IO,
	325	io->phys_start,
	326	io->bus_start,
	327	io->size);
	328
	329	if (mem)
	330	/* ATU : OUTBOUND : MEM */
	331	fsl_pcie_setup_outbound_win(pcie, idx++,
	332	PCI_REGION_MEM,
	333	mem->phys_start,
	334	mem->bus_start,
	335	mem->size);
	336	return 0;
	337	}
	338
	339	static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
	340	{
	341	phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
	342	pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
	343	u64 sz = min((u64)gd->ram_size, (1ull << 32));
	344	pci_size_t pci_sz;
	345	int idx;
	346
	347	if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
	348	idx = 2;
	349	else
	350	idx = 3;
	351
	352	pci_sz = 1ull << __ilog2_u64(sz);
	353
	354	dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
	355	(u64)bus_start, (u64)phys_start, (u64)sz);
	356
	357	/* if we aren't an exact power of two match, pci_sz is smaller
	358	* round it up to the next power of two. We report the actual
	359	* size to pci region tracking.
	360	*/
	361	if (pci_sz != sz)
	362	sz = 2ull << __ilog2_u64(sz);
	363
	364	fsl_pcie_setup_inbound_win(pcie, idx--, true,
	365	CONFIG_SYS_PCI_MEMORY_PHYS,
	366	CONFIG_SYS_PCI_MEMORY_BUS, sz);
	367	#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
	368	/*
369	* On 64-bit capable systems, set up a mapping for all of DRAM
370	* in high pci address space.
371	*/
372	pci_sz = 1ull << __ilog2_u64(gd->ram_size);
373	/* round up to the next largest power of two */
374	if (gd->ram_size > pci_sz)
375	pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
376
377	dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
378	(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
379	(u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
380
381	fsl_pcie_setup_inbound_win(pcie, idx--, true,
382	CONFIG_SYS_PCI_MEMORY_PHYS,
383	CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
384	#endif
385
386	return 0;
387	}
388
389	static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
390	{
391	fsl_pcie_setup_outbound_wins(pcie);
392	fsl_pcie_setup_inbound_wins(pcie);
393
394	return 0;
395	}
396
397	static int fsl_pcie_init_port(struct fsl_pcie *pcie)
398	{
399	ccsr_fsl_pci_t *regs = pcie->regs;
400	u32 val_32;
401	u16 val_16;
402
403	fsl_pcie_init_atmu(pcie);
404
adc983b4 HZ	405	#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
	406	val_32 = 0;
	407	fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
	408	val_32 &= ~0x03;
	409	fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
	410	udelay(1);
	411	#endif
b89e3d92	412
adc983b4 HZ	413	#ifdef CONFIG_FSL_PCIE_RESET
	414	u16 ltssm;
	415	int i;
b89e3d92	416
adc983b4 HZ	417	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
	418	/* assert PCIe reset */
	419	setbits_be32(&regs->pdb_stat, 0x08000000);
	420	(void)in_be32(&regs->pdb_stat);
	421	udelay(1000);
	422	/* clear PCIe reset */
	423	clrbits_be32(&regs->pdb_stat, 0x08000000);
	424	asm("sync;isync");
	425	for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
	426	udelay(1000);
	427	} else {
	428	fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
	429	if (ltssm == 1) {
b89e3d92 HZ	430	/* assert PCIe reset */
	431	setbits_be32(&regs->pdb_stat, 0x08000000);
	432	(void)in_be32(&regs->pdb_stat);
adc983b4	433	udelay(100);
b89e3d92 HZ	434	/* clear PCIe reset */
	435	clrbits_be32(&regs->pdb_stat, 0x08000000);
	436	asm("sync;isync");
adc983b4 HZ	437	for (i = 0; i < 100 &&
adc983b4 HZ	438	!fsl_pcie_link_up(pcie); i++)
b89e3d92	439	udelay(1000);
b89e3d92 HZ	440	}
b89e3d92 HZ	441	}
adc983b4	442	#endif
b89e3d92	443
adc983b4 HZ	444	#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
adc983b4 HZ	445	if (!fsl_pcie_link_up(pcie)) {
b89e3d92 HZ	446	serdes_corenet_t *srds_regs;
	447
	448	srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
	449	val_32 = in_be32(&srds_regs->srdspccr0);
	450
	451	if ((val_32 >> 28) == 3) {
	452	int i;
	453
	454	out_be32(&srds_regs->srdspccr0, 2 << 28);
	455	setbits_be32(&regs->pdb_stat, 0x08000000);
	456	in_be32(&regs->pdb_stat);
	457	udelay(100);
	458	clrbits_be32(&regs->pdb_stat, 0x08000000);
	459	asm("sync;isync");
	460	for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
	461	udelay(1000);
	462	}
	463	}
adc983b4	464	#endif
b89e3d92 HZ	465
	466	/*
	467	* The Read-Only Write Enable bit defaults to 1 instead of 0.
	468	* Set to 0 to protect the read-only registers.
	469	*/
adc983b4 HZ	470	#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
	471	clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
	472	#endif
b89e3d92 HZ	473
	474	/*
	475	* Enable All Error Interrupts except
	476	* - Master abort (pci)
	477	* - Master PERR (pci)
	478	* - ICCA (PCIe)
	479	*/
	480	out_be32(&regs->peer, ~0x20140);
	481
	482	/* set URR, FER, NFER (but not CER) */
	483	fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
	484	val_32 \|= 0xf000e;
	485	fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
	486
	487	/* Clear all error indications */
	488	out_be32(&regs->pme_msg_det, 0xffffffff);
	489	out_be32(&regs->pme_msg_int_en, 0xffffffff);
	490	out_be32(&regs->pedr, 0xffffffff);
	491
	492	fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
	493	if (val_16)
	494	fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
	495
	496	fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
	497	if (val_16)
	498	fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
	499
	500	return 0;
	501	}
	502
	503	static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
	504	{
	505	ccsr_fsl_pci_t *regs = pcie->regs;
d18d06ac	506	u32 classcode_reg;
b89e3d92 HZ	507	u32 val;
b89e3d92 HZ	508
d18d06ac HZ	509	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
	510	classcode_reg = PCI_CLASS_REVISION;
	511	setbits_be32(&regs->dbi_ro_wr_en, 0x01);
	512	} else {
	513	classcode_reg = CSR_CLASSCODE;
	514	}
	515
	516	fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
b89e3d92 HZ	517	val &= 0xff;
b89e3d92 HZ	518	val \|= PCI_CLASS_BRIDGE_PCI << 16;
d18d06ac HZ	519	fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
	520
	521	if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
	522	clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
b89e3d92 HZ	523
	524	return 0;
	525	}
	526
	527	static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
	528	{
	529	return fsl_pcie_fixup_classcode(pcie);
	530	}
	531
	532	static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
	533	{
	534	fsl_pcie_config_ready(pcie);
	535
	536	return 0;
	537	}
	538
	539	static int fsl_pcie_probe(struct udevice *dev)
	540	{
	541	struct fsl_pcie *pcie = dev_get_priv(dev);
	542	ccsr_fsl_pci_t *regs = pcie->regs;
	543	u16 val_16;
	544
	545	pcie->bus = dev;
	546	pcie->block_rev = in_be32(&regs->block_rev1);
	547
	548	list_add(&pcie->list, &fsl_pcie_list);
	549	pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
	550	if (!pcie->enabled) {
	551	printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
	552	return 0;
	553	}
	554
	555	fsl_pcie_setup_law(pcie);
	556
	557	pcie->mode = fsl_pcie_is_agent(pcie);
	558
	559	fsl_pcie_init_port(pcie);
	560
	561	printf("PCIe%d: %s ", pcie->idx, dev->name);
	562
	563	if (pcie->mode) {
	564	printf("Endpoint");
	565	fsl_pcie_init_ep(pcie);
	566	} else {
	567	printf("Root Complex");
	568	fsl_pcie_init_rc(pcie);
	569	}
	570
	571	if (!fsl_pcie_link_up(pcie)) {
	572	printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
	573	return 0;
	574	}
	575
	576	fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
	577	printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
	578
	579	return 0;
	580	}
	581
	582	static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
	583	{
	584	struct fsl_pcie *pcie = dev_get_priv(dev);
fbcb2ff5	585	struct fsl_pcie_data *info;
b89e3d92 HZ	586	int ret;
	587
	588	pcie->regs = dev_remap_addr(dev);
	589	if (!pcie->regs) {
	590	pr_err("\"reg\" resource not found\n");
	591	return -EINVAL;
	592	}
	593
	594	ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
	595	if (ret < 0) {
	596	pr_err("\"law_trgt_if\" not found\n");
	597	return ret;
	598	}
	599
fbcb2ff5 HZ	600	info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
	601	pcie->info = info;
	602	pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
	603	info->block_offset) / info->stride;
b89e3d92 HZ	604
	605	return 0;
	606	}
	607
	608	static const struct dm_pci_ops fsl_pcie_ops = {
	609	.read_config = fsl_pcie_read_config,
	610	.write_config = fsl_pcie_write_config,
	611	};
	612
ba827365 HZ	613	static struct fsl_pcie_data p1_p2_data = {
	614	.block_offset = 0xa000,
	615	.block_offset_mask = 0xffff,
	616	.stride = 0x1000,
	617	};
	618
1a92802e HZ	619	static struct fsl_pcie_data p2041_data = {
	620	.block_offset = 0x200000,
	621	.block_offset_mask = 0x3fffff,
	622	.stride = 0x1000,
	623	};
	624
fbcb2ff5 HZ	625	static struct fsl_pcie_data t2080_data = {
	626	.block_offset = 0x240000,
	627	.block_offset_mask = 0x3fffff,
	628	.stride = 0x10000,
	629	};
	630
b89e3d92	631	static const struct udevice_id fsl_pcie_ids[] = {
ba827365	632	{ .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
1a92802e	633	{ .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
a8c79f61	634	{ .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
4392ddbb	635	{ .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
fbcb2ff5	636	{ .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
9acc038b	637	{ .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
b89e3d92 HZ	638	{ }
	639	};
	640
	641	U_BOOT_DRIVER(fsl_pcie) = {
	642	.name = "fsl_pcie",
	643	.id = UCLASS_PCI,
	644	.of_match = fsl_pcie_ids,
	645	.ops = &fsl_pcie_ops,
	646	.ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
	647	.probe = fsl_pcie_probe,
	648	.priv_auto_alloc_size = sizeof(struct fsl_pcie),
	649	};