[J-u-boot.git] / include / configs / TQM5200.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * (C) Copyright 2004-2005
 * Martin Krause, TQ-Systems GmbH, [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
#define CONFIG_TQM5200		1	/* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules */
#define CONFIG_STK52XX		1	/* ... on a STK52XX base board */

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#ifdef CONFIG_STK52XX
#define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
#define CONFIG_PS2SERIAL	6	/* .. on PSC6			*/
#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
#define CONFIG_BOARD_EARLY_INIT_R
#endif /* CONFIG_STK52XX */

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#ifdef CONFIG_STK52XX
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
/* #define CONFIG_PCI_SCAN_SHOW	1 */

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_NET_MULTI	1
#define CONFIG_EEPRO100		1
#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#define CONFIG_NS8382X		1
#endif	/* CONFIG_STK52XX */

#ifdef CONFIG_PCI
#define ADD_PCI_CMD		CFG_CMD_PCI
#else
#define ADD_PCI_CMD		0
#endif

/*
 * Video console
 */
#if 1
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SM501
#define CONFIG_VIDEO_SM501_32BPP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CFG_CONSOLE_IS_IN_ENV
#endif

#ifdef CONFIG_VIDEO
#define ADD_BMP_CMD		CFG_CMD_BMP
#else
#define ADD_BMP_CMD		0
#endif

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/* USB */
#ifdef CONFIG_STK52XX
#define CONFIG_USB_OHCI
#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
#else
#define ADD_USB_CMD		0
#endif

/* POST support */
#define CONFIG_POST		(CFG_POST_MEMORY   | \
				 CFG_POST_CPU	   | \
				 CFG_POST_I2C)

#ifdef CONFIG_POST
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#else
#define CFG_CMD_POST_DIAG 0
#endif

/* IDE */
#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
#define ADD_IDE_CMD		(CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
#else
#define ADD_IDE_CMD		0
#endif

/*
 * Supported commands
 */
#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				ADD_BMP_CMD	| \
				ADD_IDE_CMD	| \
				ADD_PCI_CMD	| \
				ADD_USB_CMD	| \
				CFG_CMD_ASKENV	| \
				CFG_CMD_DATE	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_EEPROM	| \
				CFG_CMD_I2C	| \
				CFG_CMD_JFFS2	| \
				CFG_CMD_MII	| \
				CFG_CMD_NFS	| \
				CFG_CMD_PING	| \
				CFG_CMD_POST_DIAG | \
				CFG_CMD_REGINFO | \
				CFG_CMD_SNTP	| \
				CFG_CMD_BSP)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define	CONFIG_TIMESTAMP		/* display image timestamps */

#if (TEXT_BASE == 0xFC000000)		/* Boot low */
#   define CFG_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"bootfile=/tftpboot/tqm5200/uImage\0"				\
	"load=tftp 200000 ${u-boot}\0"					\
	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
	"update=protect off FC000000 FC05FFFF;"				\
		"erase FC000000 FC05FFFF;"				\
		"cp.b 200000 FC000000 ${filesize};"			\
		"protect on FC000000 FC05FFFF\0"			\
	""

#define CONFIG_BOOTCOMMAND	"run net_nfs"

/*
 * IPB Bus clocking configuration.
 */
#define CFG_IPBSPEED_133		/* define for 133MHz speed */

#if defined(CFG_IPBSPEED_133)
/*
 * PCI Bus clocking configuration
 *
 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
 * been tested with a IPB Bus Clock of 66 MHz.
 */
#define CFG_PCISPEED_66			/* define for 66MHz speed */
#endif

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#ifdef CONFIG_TQM5200_REV100
#define CFG_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
#else
#define CFG_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
#endif

/*
 * I2C clock frequency
 *
 * Please notice, that the resulting clock frequency could differ from the
 * configured value. This is because the I2C clock is derived from system
 * clock over a frequency divider with only a few divider values. U-boot
 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 * approximation allways lies below the configured value, never above.
 */
#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 * same configuration could be used.
 */
#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN		2
#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20

/*
 * HW-Monitor configuration on Mini-FAP
 */
#if defined (CONFIG_MINIFAP)
#define CFG_I2C_HWMON_ADDR		0x2C
#endif

/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_MINIFAP)
#undef I2C_ADDR_LIST
#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
				CFG_I2C_HWMON_ADDR,	\
				CFG_I2C_SLAVE }
#endif

/*
 * Flash configuration
 */
#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */

/* use CFI flash driver if no module variant is spezified */
#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
#define CFG_FLASH_USE_BUFFER_WRITE	1

#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
#else	/* CFG_LOWBOOT */
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
#endif	/* CFG_LOWBOOT */
#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

/* Dynamic MTD partition support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=TQM5200-0"
#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
						"1408k(kernel),"	\
						"2m(initrd),"		\
						"4m(small-fs),"		\
						"16m(big-fs),"		\
						"8m(misc)"

/*
 * Environment settings
 */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SIZE		0x10000
#define CFG_ENV_SECT_SIZE	0x20000
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

/*
 * Memory map
 */
#define CFG_MBAR		0xF0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
#else
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
#endif


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE	TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 *
 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 *	Bit 0 (mask: 0x80000000): 1
 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 *	      Use for REV200 STK52XX boards. Do not use with REV100 modules
 *	      (because, there I2C1 is used as I2C bus)
 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 *	000 -> All PSC2 pins are GIOPs
 *	001 -> CAN1/2 on PSC2 pins
 *	       Use for REV100 STK52xx boards
 * use PSC6:
 *   on STK52xx:
 *	use as UART. Pins PSC6_0 to PSC6_3 are used.
 *	Bits 9:11 (mask: 0x00700000):
 *	   101 -> PSC6 : Extended POST test is not available
 *   on MINI-FAP and TQM5200_IB:
 *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
 *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 *   tests.
 */
#if defined (CONFIG_MINIFAP)
# define CFG_GPS_PORT_CONFIG	0x91000004
#elif defined (CONFIG_STK52XX)
# if defined (CONFIG_STK52XX_REV100)
#  define CFG_GPS_PORT_CONFIG	0x81500014
# else /* STK52xx REV200 and above */
#  if defined (CONFIG_TQM5200_REV100)
#   error TQM5200 REV100 not supported on STK52XX REV200 or above
#  else/* TQM5200 REV200 and above */
#   define CFG_GPS_PORT_CONFIG	0x91500004
#  endif
# endif
#else  /* TMQ5200 Inbetriebnahme-Board */
# define CFG_GPS_PORT_CONFIG	0x81000004
#endif

/*
 * RTC configuration
 */
#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
# define CONFIG_RTC_M41T11 1
# define CFG_I2C_RTC_ADDR 0x68
# define CFG_M41T11_BASE_YEAR	1900    /* because Linux uses the same base
					   year */
#else
# define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
#endif

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
 * which is normally part of the default commands (CFV_CMD_DFL)
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE
#else
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		0
#endif

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
#else
#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
#endif
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

/* automatic configuration of chip selects */
#ifdef CONFIG_CS_AUTOCONF
#define CONFIG_LAST_STAGE_INIT
#endif

/*
 * SRAM - Do not map below 2 GB in address space, because this area is used
 * for SDRAM autosizing.
 */
#if defined (CONFIG_CS_AUTOCONF)
#define CFG_CS2_START		0xE5000000
#define CFG_CS2_SIZE		0x100000	/* 1 MByte */
#define CFG_CS2_CFG		0x0004D930
#endif

/*
 * Grafic controller - Do not map below 2 GB in address space, because this
 * area is used for SDRAM autosizing.
 */
#if defined (CONFIG_CS_AUTOCONF)
#define SM501_FB_BASE		0xE0000000
#define CFG_CS1_START		(SM501_FB_BASE)
#define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
#define CFG_CS1_CFG		0x8F48FF70
#define SM501_MMIO_BASE		CFG_CS1_START + 0x03E00000
#endif

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */

#define CFG_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/

#define CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers						     */
#define CFG_ATA_STRIDE		4

#endif /* __CONFIG_H */
Commit	Line	Data
56523f12	1	/*
8f0b7cbe	2	* (C) Copyright 2003-2005
56523f12 WD	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
56523f12 WD	4	*
8f0b7cbe	5	* (C) Copyright 2004-2005
56523f12 WD	6	* Martin Krause, TQ-Systems GmbH, [email protected]
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
56523f12 WD	30	/*
	31	* High Level Configuration Options
	32	* (easy to change)
	33	*/
	34
	35	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	36	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	37	#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
8f0b7cbe	38	#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
7e6bf358	39	#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
56523f12 WD	40
	41	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	42
	43	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	44	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	45
	46	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	47	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	48	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	49	#endif
	50
	51	/*
	52	* Serial console configuration
	53	*/
	54	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	55	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	56	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	57
7e6bf358 WD	58	#ifdef CONFIG_STK52XX
	59	#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
	60	#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
	61	#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
	62	#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
	63	#define CONFIG_BOARD_EARLY_INIT_R
	64	#endif /* CONFIG_STK52XX */
56523f12	65
56523f12 WD	66	/*
	67	* PCI Mapping:
	68	* 0x40000000 - 0x4fffffff - PCI Memory
	69	* 0x50000000 - 0x50ffffff - PCI IO Space
	70	*/
7e6bf358 WD	71	#ifdef CONFIG_STK52XX
7e6bf358 WD	72	#define CONFIG_PCI 1
56523f12	73	#define CONFIG_PCI_PNP 1
31a64923	74	/* #define CONFIG_PCI_SCAN_SHOW 1 */
56523f12 WD	75
	76	#define CONFIG_PCI_MEM_BUS 0x40000000
	77	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	78	#define CONFIG_PCI_MEM_SIZE 0x10000000
	79
	80	#define CONFIG_PCI_IO_BUS 0x50000000
	81	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	82	#define CONFIG_PCI_IO_SIZE 0x01000000
	83
	84	#define CONFIG_NET_MULTI 1
cd65a3dc	85	#define CONFIG_EEPRO100 1
56523f12 WD	86	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
56523f12 WD	87	#define CONFIG_NS8382X 1
83e40ba7	88	#endif /* CONFIG_STK52XX */
56523f12	89
8f0b7cbe	90	#ifdef CONFIG_PCI
7e6bf358	91	#define ADD_PCI_CMD CFG_CMD_PCI
8f0b7cbe	92	#else
7e6bf358 WD	93	#define ADD_PCI_CMD 0
7e6bf358 WD	94	#endif
56523f12	95
8f0b7cbe WD	96	/*
	97	* Video console
	98	*/
	99	#if 1
	100	#define CONFIG_VIDEO
	101	#define CONFIG_VIDEO_SM501
	102	#define CONFIG_VIDEO_SM501_32BPP
	103	#define CONFIG_CFB_CONSOLE
	104	#define CONFIG_VIDEO_LOGO
	105	#define CONFIG_VGA_AS_SINGLE_DEVICE
	106	#define CONFIG_CONSOLE_EXTRA_INFO
	107	#define CONFIG_VIDEO_SW_CURSOR
	108	#define CONFIG_SPLASH_SCREEN
83e40ba7	109	#define CFG_CONSOLE_IS_IN_ENV
8f0b7cbe	110	#endif
56523f12	111
8f0b7cbe WD	112	#ifdef CONFIG_VIDEO
	113	#define ADD_BMP_CMD CFG_CMD_BMP
	114	#else
	115	#define ADD_BMP_CMD 0
56523f12 WD	116	#endif
	117
	118	/* Partitions */
89c02e2c	119	#define CONFIG_MAC_PARTITION
56523f12	120	#define CONFIG_DOS_PARTITION
8f0b7cbe	121	#define CONFIG_ISO_PARTITION
56523f12 WD	122
56523f12 WD	123	/* USB */
7e6bf358	124	#ifdef CONFIG_STK52XX
56523f12	125	#define CONFIG_USB_OHCI
81050926	126	#define ADD_USB_CMD CFG_CMD_USB \| CFG_CMD_FAT
56523f12 WD	127	#define CONFIG_USB_STORAGE
56523f12 WD	128	#else
81050926	129	#define ADD_USB_CMD 0
56523f12 WD	130	#endif
	131
	132	/* POST support */
	133	#define CONFIG_POST (CFG_POST_MEMORY \| \
	134	CFG_POST_CPU \| \
	135	CFG_POST_I2C)
	136
	137	#ifdef CONFIG_POST
	138	#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
	139	/* preserve space for the post_word at end of on-chip SRAM */
	140	#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
	141	#else
	142	#define CFG_CMD_POST_DIAG 0
	143	#endif
	144
	145	/* IDE */
7e6bf358	146	#if defined (CONFIG_MINIFAP) \|\| defined (CONFIG_STK52XX)
151ab83a	147	#define ADD_IDE_CMD (CFG_CMD_IDE \| CFG_CMD_FAT \| CFG_CMD_EXT2)
56523f12 WD	148	#else
	149	#define ADD_IDE_CMD 0
	150	#endif
	151
	152	/*
	153	* Supported commands
	154	*/
	155	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
8f0b7cbe	156	ADD_BMP_CMD \| \
151ab83a	157	ADD_IDE_CMD \| \
56523f12 WD	158	ADD_PCI_CMD \| \
56523f12 WD	159	ADD_USB_CMD \| \
151ab83a	160	CFG_CMD_ASKENV \| \
56523f12	161	CFG_CMD_DATE \| \
151ab83a	162	CFG_CMD_DHCP \| \
151ab83a WD	163	CFG_CMD_EEPROM \| \
151ab83a WD	164	CFG_CMD_I2C \| \
d534f5cc	165	CFG_CMD_JFFS2 \| \
56523f12	166	CFG_CMD_MII \| \
414eec35	167	CFG_CMD_NFS \| \
56523f12	168	CFG_CMD_PING \| \
151ab83a	169	CFG_CMD_POST_DIAG \| \
414eec35	170	CFG_CMD_REGINFO \| \
6617aae9 WD	171	CFG_CMD_SNTP \| \
6617aae9 WD	172	CFG_CMD_BSP)
56523f12 WD	173
	174	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	175	#include <cmd_confdefs.h>
	176
151ab83a WD	177	#define CONFIG_TIMESTAMP /* display image timestamps */
151ab83a WD	178
56523f12	179	#if (TEXT_BASE == 0xFC000000) /* Boot low */
81050926	180	# define CFG_LOWBOOT 1
56523f12 WD	181	#endif
	182
	183	/*
	184	* Autobooting
	185	*/
	186	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	187
81050926	188	#define CONFIG_PREBOOT "echo;" \
56523f12 WD	189	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	190	"echo"
	191
	192	#undef CONFIG_BOOTARGS
	193
81050926	194	#define CONFIG_EXTRA_ENV_SETTINGS \
56523f12	195	"netdev=eth0\0" \
89c02e2c	196	"rootpath=/opt/eldk/ppc_6xx\0" \
56523f12	197	"ramargs=setenv bootargs root=/dev/ram rw\0" \
56523f12	198	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b WD	199	"nfsroot=${serverip}:${rootpath}\0" \
	200	"addip=setenv bootargs ${bootargs} " \
	201	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	202	":${hostname}:${netdev}:off panic=1\0" \
56523f12	203	"flash_self=run ramargs addip;" \
fe126d8b	204	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
7e6bf358	205	"flash_nfs=run nfsargs addip;" \
fe126d8b WD	206	"bootm ${kernel_addr}\0" \
fe126d8b WD	207	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
89c02e2c	208	"bootfile=/tftpboot/tqm5200/uImage\0" \
fe126d8b	209	"load=tftp 200000 ${u-boot}\0" \
cd65a3dc	210	"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
89c02e2c WD	211	"update=protect off FC000000 FC05FFFF;" \
89c02e2c WD	212	"erase FC000000 FC05FFFF;" \
fe126d8b	213	"cp.b 200000 FC000000 ${filesize};" \
e6325153	214	"protect on FC000000 FC05FFFF\0" \
7e6bf358	215	""
56523f12 WD	216
	217	#define CONFIG_BOOTCOMMAND "run net_nfs"
	218
	219	/*
	220	* IPB Bus clocking configuration.
	221	*/
81050926	222	#define CFG_IPBSPEED_133 /* define for 133MHz speed */
56523f12 WD	223
	224	#if defined(CFG_IPBSPEED_133)
	225	/*
	226	* PCI Bus clocking configuration
	227	*
	228	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
	229	* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
	230	* been tested with a IPB Bus Clock of 66 MHz.
	231	*/
	232	#define CFG_PCISPEED_66 /* define for 66MHz speed */
	233	#endif
	234
	235	/*
	236	* I2C configuration
	237	*/
	238	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
8f0b7cbe WD	239	#ifdef CONFIG_TQM5200_REV100
8f0b7cbe WD	240	#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
56523f12	241	#else
8f0b7cbe	242	#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
56523f12 WD	243	#endif
	244
	245	/*
	246	* I2C clock frequency
	247	*
	248	* Please notice, that the resulting clock frequency could differ from the
	249	* configured value. This is because the I2C clock is derived from system
	250	* clock over a frequency divider with only a few divider values. U-boot
	251	* calculates the best approximation for CFG_I2C_SPEED. However the calculated
	252	* approximation allways lies below the configured value, never above.
	253	*/
	254	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	255	#define CFG_I2C_SLAVE 0x7F
	256
	257	/*
	258	* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
	259	* also). For other EEPROMs configuration should be verified. On Mini-FAP the
	260	* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
	261	* same configuration could be used.
	262	*/
	263	#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	264	#define CFG_I2C_EEPROM_ADDR_LEN 2
	265	#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
	266	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
	267
	268	/*
	269	* HW-Monitor configuration on Mini-FAP
	270	*/
	271	#if defined (CONFIG_MINIFAP)
	272	#define CFG_I2C_HWMON_ADDR 0x2C
	273	#endif
	274
	275	/* List of I2C addresses to be verified by POST */
56523f12 WD	276	#if defined (CONFIG_MINIFAP)
	277	#undef I2C_ADDR_LIST
	278	#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
	279	CFG_I2C_HWMON_ADDR, \
	280	CFG_I2C_SLAVE }
	281	#endif
	282
	283	/*
	284	* Flash configuration
	285	*/
	286	#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
	287
7e6bf358 WD	288	/* use CFI flash driver if no module variant is spezified */
	289	#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
	290	#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
	291	#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
	292	#define CFG_FLASH_EMPTY_INFO
8f0b7cbe WD	293	#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
8f0b7cbe WD	294	#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
f3e06df7	295	#define CFG_FLASH_USE_BUFFER_WRITE 1
56523f12 WD	296
56523f12 WD	297	#if !defined(CFG_LOWBOOT)
89c02e2c	298	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
56523f12	299	#else /* CFG_LOWBOOT */
89c02e2c	300	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
56523f12 WD	301	#endif /* CFG_LOWBOOT */
	302	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
	303	(= chip selects) */
81050926 WD	304	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
81050926 WD	305	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
56523f12	306
d534f5cc WD	307	/* Dynamic MTD partition support */
	308	#define CONFIG_JFFS2_CMDLINE
	309	#define MTDIDS_DEFAULT "nor0=TQM5200-0"
	310	#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
	311	"1408k(kernel)," \
	312	"2m(initrd)," \
	313	"4m(small-fs)," \
	314	"16m(big-fs)," \
	315	"8m(misc)"
56523f12 WD	316
	317	/*
	318	* Environment settings
	319	*/
	320	#define CFG_ENV_IS_IN_FLASH 1
	321	#define CFG_ENV_SIZE 0x10000
	322	#define CFG_ENV_SECT_SIZE 0x20000
89c02e2c WD	323	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
89c02e2c WD	324	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
56523f12 WD	325
	326	/*
	327	* Memory map
	328	*/
	329	#define CFG_MBAR 0xF0000000
	330	#define CFG_SDRAM_BASE 0x00000000
	331	#define CFG_DEFAULT_MBAR 0x80000000
	332
	333	/* Use ON-Chip SRAM until RAM will be available */
	334	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	335	#ifdef CONFIG_POST
	336	/* preserve space for the post_word at end of on-chip SRAM */
	337	#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
	338	#else
	339	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
	340	#endif
	341
	342
	343	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	344	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	345	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	346
89c02e2c	347	#define CFG_MONITOR_BASE TEXT_BASE
56523f12 WD	348	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	349	# define CFG_RAMBOOT 1
	350	#endif
	351
89c02e2c	352	#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
d00de23b	353	#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
56523f12 WD	354	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	355
	356	/*
	357	* Ethernet configuration
	358	*/
	359	#define CONFIG_MPC5xxx_FEC 1
	360	/*
	361	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	362	*/
	363	/* #define CONFIG_FEC_10MBIT 1 */
	364	#define CONFIG_PHY_ADDR 0x00
	365
	366	/*
	367	* GPIO configuration
	368	*
	369	* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
	370	* Bit 0 (mask: 0x80000000): 1
	371	* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
8f0b7cbe	372	* 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
8f0b7cbe	373	* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
83e40ba7 WD	374	* Use for REV200 STK52XX boards. Do not use with REV100 modules
83e40ba7 WD	375	* (because, there I2C1 is used as I2C bus)
56523f12	376	* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
83e40ba7 WD	377	* use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
	378	* 000 -> All PSC2 pins are GIOPs
	379	* 001 -> CAN1/2 on PSC2 pins
	380	* Use for REV100 STK52xx boards
7e6bf358 WD	381	* use PSC6:
7e6bf358 WD	382	* on STK52xx:
8f0b7cbe WD	383	* use as UART. Pins PSC6_0 to PSC6_3 are used.
8f0b7cbe WD	384	* Bits 9:11 (mask: 0x00700000):
7e6bf358 WD	385	* 101 -> PSC6 : Extended POST test is not available
7e6bf358 WD	386	* on MINI-FAP and TQM5200_IB:
8f0b7cbe WD	387	* use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
	388	* 000 -> PSC6 could not be used as UART, CODEC or IrDA
	389	* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
	390	* tests.
56523f12 WD	391	*/
56523f12 WD	392	#if defined (CONFIG_MINIFAP)
8f0b7cbe	393	# define CFG_GPS_PORT_CONFIG 0x91000004
7e6bf358	394	#elif defined (CONFIG_STK52XX)
83e40ba7 WD	395	# if defined (CONFIG_STK52XX_REV100)
	396	# define CFG_GPS_PORT_CONFIG 0x81500014
	397	# else /* STK52xx REV200 and above */
	398	# if defined (CONFIG_TQM5200_REV100)
	399	# error TQM5200 REV100 not supported on STK52XX REV200 or above
	400	# else/* TQM5200 REV200 and above */
	401	# define CFG_GPS_PORT_CONFIG 0x91500004
	402	# endif
8f0b7cbe	403	# endif
83e40ba7	404	#else /* TMQ5200 Inbetriebnahme-Board */
8f0b7cbe	405	# define CFG_GPS_PORT_CONFIG 0x81000004
56523f12 WD	406	#endif
	407
	408	/*
	409	* RTC configuration
	410	*/
4f562f14 WD	411	#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
	412	# define CONFIG_RTC_M41T11 1
	413	# define CFG_I2C_RTC_ADDR 0x68
edd0b509 WD	414	# define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
edd0b509 WD	415	year */
4f562f14 WD	416	#else
	417	# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
	418	#endif
56523f12 WD	419
	420	/*
	421	* Miscellaneous configurable options
	422	*/
	423	#define CFG_LONGHELP /* undef to save memory */
	424	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	425	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	426	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	427	#else
	428	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	429	#endif
	430	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	431	#define CFG_MAXARGS 16 /* max number of command args */
	432	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	433
	434	/* Enable an alternate, more extensive memory test */
	435	#define CFG_ALT_MEMTEST
	436
	437	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	438	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	439
	440	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	441
	442	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	443
	444	/*
	445	* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
	446	* which is normally part of the default commands (CFV_CMD_DFL)
	447	*/
	448	#define CONFIG_LOOPW
	449
	450	/*
	451	* Various low-level settings
	452	*/
	453	#if defined(CONFIG_MPC5200)
	454	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	455	#define CFG_HID0_FINAL HID0_ICE
	456	#else
	457	#define CFG_HID0_INIT 0
	458	#define CFG_HID0_FINAL 0
	459	#endif
	460
	461	#define CFG_BOOTCS_START CFG_FLASH_BASE
	462	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	463	#ifdef CFG_PCISPEED_66
	464	#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
	465	#else
	466	#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
	467	#endif
	468	#define CFG_CS0_START CFG_FLASH_BASE
	469	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	470
7e6bf358 WD	471	/* automatic configuration of chip selects */
	472	#ifdef CONFIG_CS_AUTOCONF
	473	#define CONFIG_LAST_STAGE_INIT
	474	#endif
	475
56523f12 WD	476	/*
	477	* SRAM - Do not map below 2 GB in address space, because this area is used
	478	* for SDRAM autosizing.
	479	*/
cd65a3dc	480	#if defined (CONFIG_CS_AUTOCONF)
56523f12	481	#define CFG_CS2_START 0xE5000000
7e6bf358	482	#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
56523f12 WD	483	#define CFG_CS2_CFG 0x0004D930
	484	#endif
	485
	486	/*
	487	* Grafic controller - Do not map below 2 GB in address space, because this
	488	* area is used for SDRAM autosizing.
	489	*/
cd65a3dc	490	#if defined (CONFIG_CS_AUTOCONF)
8f0b7cbe WD	491	#define SM501_FB_BASE 0xE0000000
8f0b7cbe WD	492	#define CFG_CS1_START (SM501_FB_BASE)
56523f12	493	#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
89394047	494	#define CFG_CS1_CFG 0x8F48FF70
56523f12 WD	495	#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
	496	#endif
	497
	498	#define CFG_CS_BURST 0x00000000
8f0b7cbe	499	#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
56523f12 WD	500
	501	#define CFG_RESET_ADDRESS 0xff000000
	502
	503	/*-----------------------------------------------------------------------
	504	* USB stuff
	505	*-----------------------------------------------------------------------
	506	*/
	507	#define CONFIG_USB_CLOCK 0x0001BBBB
	508	#define CONFIG_USB_CONFIG 0x00001000
	509
	510	/*-----------------------------------------------------------------------
	511	* IDE/ATA stuff Supports IDE harddisk
	512	*-----------------------------------------------------------------------
	513	*/
	514
81050926	515	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
56523f12	516
81050926 WD	517	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
81050926 WD	518	#undef CONFIG_IDE_LED /* LED for ide not supported */
56523f12	519
81050926	520	#define CONFIG_IDE_RESET /* reset for ide supported */
56523f12 WD	521	#define CONFIG_IDE_PREINIT
	522
	523	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
8f0b7cbe	524	#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
56523f12 WD	525
	526	#define CFG_ATA_IDE0_OFFSET 0x0000
	527
	528	#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
	529
	530	/* Offset for data I/O */
	531	#define CFG_ATA_DATA_OFFSET (0x0060)
	532
	533	/* Offset for normal register accesses */
	534	#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
	535
	536	/* Offset for alternate registers */
	537	#define CFG_ATA_ALT_OFFSET (0x005C)
	538
81050926 WD	539	/* Interval between registers */
81050926 WD	540	#define CFG_ATA_STRIDE 4
56523f12 WD	541
56523f12 WD	542	#endif /* __CONFIG_H */