[J-u-boot.git] / include / configs / PM826.h

/*
 * (C) Copyright 2001-2005
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#undef CFG_RAMBOOT

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
#define CONFIG_PM826		1	/* ...on a PM8260 module	*/
#define CONFIG_CPM2		1	/* Has a CPM2 */

#undef CONFIG_DB_CR826_J30x_ON		/* J30x jumpers on D.B. carrier	*/

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

/* enable I2C and select the hardware/software driver */
#undef  CONFIG_HARD_I2C
#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
# define CFG_I2C_SPEED		50000
# define CFG_I2C_SLAVE		0xFE
/*
 * Software (bit-bang) I2C driver configuration
 */
#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
#define I2C_READ	((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
			else    iop->pdat &= ~0x00010000
#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
			else    iop->pdat &= ~0x00020000
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */


#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR	0x51

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef  CONFIG_CONS_NONE		/* define if console on something else*/
#define CONFIG_CONS_INDEX	2	/* which serial channel for console */

/*
 * select ethernet configuration
 *
 * if CONFIG_ETHER_ON_SCC is selected, then
 *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
 *   - CONFIG_NET_MULTI must not be defined
 *
 * if CONFIG_ETHER_ON_FCC is selected, then
 *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
 *   - CONFIG_NET_MULTI must be defined
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#define	CONFIG_NET_MULTI
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */

#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
#define	CONFIG_ETHER_INDEX    1		/* which SCC channel for ethernet */

#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
/*
 * - Rx-CLK is CLK11
 * - Tx-CLK is CLK10
 */
#define	CONFIG_ETHER_ON_FCC1
# define CFG_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
#ifndef CONFIG_DB_CR826_J30x_ON
# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
#else
# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
#endif
/*
 * - Rx-CLK is CLK15
 * - Tx-CLK is CLK14
 */
#define	CONFIG_ETHER_ON_FCC2
# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
/*
 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 * - Enable Full Duplex in FSMR
 */
# define CFG_CPMFCR_RAMTYPE	0
# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	64000000	/* in Hz */

#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
#define CONFIG_BAUDRATE		230400
#else
#define CONFIG_BAUDRATE		9600
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DOC
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP

#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif


#define CONFIG_NAND_LEGACY

/*
 * Disk-On-Chip configuration
 */

#define CFG_DOC_SHORT_TIMEOUT
#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/

#define CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define	CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * Flash and Boot ROM mapping
 */
#ifdef CONFIG_FLASH_32MB
#define	CFG_FLASH0_BASE		0x40000000
#define	CFG_FLASH0_SIZE		0x02000000
#else
#define	CFG_FLASH0_BASE		0xFF000000
#define	CFG_FLASH0_SIZE		0x00800000
#endif
#define	CFG_BOOTROM_BASE	0xFF800000
#define	CFG_BOOTROM_SIZE	0x00080000
#define CFG_DOC_BASE		0xFF800000
#define CFG_DOC_SIZE		0x00100000

/* Flash bank size (for preliminary settings)
 */
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#ifdef CONFIG_FLASH_32MB
#define CFG_MAX_FLASH_SECT	135	/* max num of sects on one chip */
#else
#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
#endif
#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#if 0
/* Start port with environment in flash; switch to EEPROM later */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
#define CFG_ENV_SIZE		0x40000
#define CFG_ENV_SECT_SIZE	0x40000
#else
/* Final version: environment in EEPROM */
#define CONFIG_ENV_IS_IN_EEPROM	1
#define CFG_I2C_EEPROM_ADDR	0x58
#define CFG_I2C_EEPROM_ADDR_LEN	1
#define CFG_EEPROM_PAGE_WRITE_BITS	4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
#define CFG_ENV_OFFSET		512
#define CFG_ENV_SIZE		(2048 - 512)
#endif

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CFG_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 */
#if defined(CONFIG_BOOT_ROM)
#define CFG_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
#else
#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
#endif

/* no slaves so just fill with zeros */
#define CFG_HRCW_SLAVE1		0
#define CFG_HRCW_SLAVE2		0
#define CFG_HRCW_SLAVE3		0
#define CFG_HRCW_SLAVE4		0
#define CFG_HRCW_SLAVE5		0
#define CFG_HRCW_SLAVE6		0
#define CFG_HRCW_SLAVE7		0

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 *
 * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
 * is mapped at SDRAM_BASE2_PRELIM.
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		CFG_FLASH0_BASE
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT
#endif

#ifdef	CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
#define BOOTFLAG_WARM		0x02	/* Software reboot                 */


/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers                    2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
				HID0_IFEM|HID0_ABE)
#define CFG_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE)
#define CFG_HID2        0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register                                     5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CFG_RMR         RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration                                       4-25
 *-----------------------------------------------------------------------
 */

#define BCR_APD01       0x10000000
#define CFG_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration                             4-31
 *-----------------------------------------------------------------------
 */
#if 0
#define CFG_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
#else
#define CFG_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
#endif


/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control                             4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control                     4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control                 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control                                   9-8
 *-----------------------------------------------------------------------
 */
#define CFG_SCCR        (SCCR_DFBRG00)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration                         13-7
 *-----------------------------------------------------------------------
 */
#define CFG_RCCR        0

/*
 * Init Memory Controller:
 *
 * Bank Bus     Machine PortSz  Device
 * ---- ---     ------- ------  ------
 *  0   60x     GPCM    64 bit  FLASH
 *  1   60x     SDRAM   64 bit  SDRAM
 *
 */

	/* Initialize SDRAM on local bus
	 */
#define CFG_INIT_LOCAL_SDRAM


/* Minimum mask to separate preliminary
 * address ranges for CS[0:2]
 */
#define CFG_MIN_AM_MASK	0xC0000000

/*
 * we use the same values for 32 MB and 128 MB SDRAM
 * refresh rate = 7.73 uS (64 MHz Bus Clock)
 */
#define CFG_MPTPR       0x2000
#define CFG_PSRT        0x0E

#define CFG_MRS_OFFS	0x00000000


#if defined(CONFIG_BOOT_ROM)
/*
 * Bank 0 - Boot ROM (8 bit wide)
 */
#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
			 BRx_PS_8			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_3_CLK			|\
			 ORxG_EHTR			|\
			 ORxG_TRLX)

/*
 * Bank 1 - Flash (64 bit wide)
 */
#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
			 BRx_PS_64			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_3_CLK			|\
			 ORxG_EHTR			|\
			 ORxG_TRLX)

#else	/* ! CONFIG_BOOT_ROM */

/*
 * Bank 0 - Flash (64 bit wide)
 */
#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
			 BRx_PS_64                      |\
			 BRx_MS_GPCM_P                  |\
			 BRx_V)

#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
			 ORxG_CSNT                      |\
			 ORxG_ACS_DIV1                  |\
			 ORxG_SCY_3_CLK                 |\
			 ORxG_EHTR                      |\
			 ORxG_TRLX)

/*
 * Bank 1 - Disk-On-Chip
 */
#define CFG_BR1_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
			 BRx_PS_8			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_3_CLK			|\
			 ORxG_EHTR			|\
			 ORxG_TRLX)

#endif /* CONFIG_BOOT_ROM */

/* Bank 2 - SDRAM
 */

#ifndef CFG_RAMBOOT
#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
			 BRx_PS_64                      |\
			 BRx_MS_SDRAM_P                 |\
			 BRx_V)

	/* SDRAM initialization values for 8-column chips
	 */
#define CFG_OR2_8COL    (CFG_MIN_AM_MASK	        |\
			 ORxS_BPD_4                     |\
			 ORxS_ROWST_PBI0_A9             |\
			 ORxS_NUMR_12)

#define CFG_PSDMR_8COL  (PSDMR_SDAM_A13_IS_A5           |\
			 PSDMR_BSMA_A14_A16             |\
			 PSDMR_SDA10_PBI0_A10           |\
			 PSDMR_RFRC_7_CLK               |\
			 PSDMR_PRETOACT_2W              |\
			 PSDMR_ACTTORW_1W               |\
			 PSDMR_LDOTOPRE_1C              |\
			 PSDMR_WRC_1C                   |\
			 PSDMR_CL_2)

	/* SDRAM initialization values for 9-column chips
	 */
#define CFG_OR2_9COL    (CFG_MIN_AM_MASK                |\
			 ORxS_BPD_4                     |\
			 ORxS_ROWST_PBI0_A7             |\
			 ORxS_NUMR_13)

#define CFG_PSDMR_9COL  (PSDMR_SDAM_A14_IS_A5           |\
			 PSDMR_BSMA_A13_A15             |\
			 PSDMR_SDA10_PBI0_A9            |\
			 PSDMR_RFRC_7_CLK               |\
			 PSDMR_PRETOACT_2W              |\
			 PSDMR_ACTTORW_1W               |\
			 PSDMR_LDOTOPRE_1C              |\
			 PSDMR_WRC_1C                   |\
			 PSDMR_CL_2)

#define CFG_OR2_PRELIM   CFG_OR2_9COL
#define CFG_PSDMR        CFG_PSDMR_9COL

#endif /* CFG_RAMBOOT */

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768	1	/*
414eec35	2	* (C) Copyright 2001-2005
0f8c9768 WD	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	#undef CFG_RAMBOOT
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37
	38	#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
	39	#define CONFIG_PM826 1 /* ...on a PM8260 module */
9c4c5ae3	40	#define CONFIG_CPM2 1 /* Has a CPM2 */
0f8c9768	41
aacf9a49 WD	42	#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
aacf9a49 WD	43
0f8c9768 WD	44	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
0f8c9768 WD	45
32bf3d14	46	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
0f8c9768 WD	47
	48	#undef CONFIG_BOOTARGS
	49	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	50	"bootp; " \
	51	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	52	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
0f8c9768 WD	53	"bootm"
	54
	55	/* enable I2C and select the hardware/software driver */
	56	#undef CONFIG_HARD_I2C
	57	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
	58	# define CFG_I2C_SPEED 50000
	59	# define CFG_I2C_SLAVE 0xFE
	60	/*
	61	* Software (bit-bang) I2C driver configuration
	62	*/
	63	#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
	64	#define I2C_ACTIVE (iop->pdir \|= 0x00010000)
	65	#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
	66	#define I2C_READ ((iop->pdat & 0x00010000) != 0)
	67	#define I2C_SDA(bit) if(bit) iop->pdat \|= 0x00010000; \
	68	else iop->pdat &= ~0x00010000
	69	#define I2C_SCL(bit) if(bit) iop->pdat \|= 0x00020000; \
	70	else iop->pdat &= ~0x00020000
	71	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	72
	73
	74	#define CONFIG_RTC_PCF8563
	75	#define CFG_I2C_RTC_ADDR 0x51
	76
	77	/*
	78	* select serial console configuration
	79	*
	80	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	81	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	82	* for SCC).
	83	*
	84	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	85	* defined elsewhere (for example, on the cogent platform, there are serial
	86	* ports on the motherboard which are used for the serial console - see
	87	* cogent/cma101/serial.[ch]).
	88	*/
	89	#define CONFIG_CONS_ON_SMC /* define if console on SMC */
	90	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
	91	#undef CONFIG_CONS_NONE /* define if console on something else*/
	92	#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
	93
	94	/*
	95	* select ethernet configuration
	96	*
aacf9a49 WD	97	* if CONFIG_ETHER_ON_SCC is selected, then
	98	* - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
	99	* - CONFIG_NET_MULTI must not be defined
	100	*
	101	* if CONFIG_ETHER_ON_FCC is selected, then
	102	* - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
	103	* - CONFIG_NET_MULTI must be defined
0f8c9768 WD	104	*
0f8c9768 WD	105	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7	106	* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
0f8c9768	107	*/
aacf9a49	108	#define CONFIG_NET_MULTI
0f8c9768	109	#undef CONFIG_ETHER_NONE /* define if ether on something else */
0f8c9768	110
aacf9a49 WD	111	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
	112	#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */
	113
	114	#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
0f8c9768 WD	115	/*
	116	* - Rx-CLK is CLK11
	117	* - Tx-CLK is CLK10
aacf9a49 WD	118	*/
	119	#define CONFIG_ETHER_ON_FCC1
	120	# define CFG_CMXFCR_MASK1 (CMXFCR_FC1\|CMXFCR_RF1CS_MSK\|CMXFCR_TF1CS_MSK)
	121	#ifndef CONFIG_DB_CR826_J30x_ON
	122	# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11\|CMXFCR_TF1CS_CLK10)
	123	#else
	124	# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11\|CMXFCR_TF1CS_CLK12)
	125	#endif
	126	/*
	127	* - Rx-CLK is CLK15
	128	* - Tx-CLK is CLK14
	129	*/
	130	#define CONFIG_ETHER_ON_FCC2
	131	# define CFG_CMXFCR_MASK2 (CMXFCR_FC2\|CMXFCR_RF2CS_MSK\|CMXFCR_TF2CS_MSK)
	132	# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13\|CMXFCR_TF2CS_CLK14)
	133	/*
0f8c9768 WD	134	* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
	135	* - Enable Full Duplex in FSMR
	136	*/
0f8c9768 WD	137	# define CFG_CPMFCR_RAMTYPE 0
	138	# define CFG_FCC_PSMR (FCC_PSMR_FDE\|FCC_PSMR_LPB)
	139
0f8c9768 WD	140	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
	141	#define CONFIG_8260_CLKIN 64000000 /* in Hz */
	142
	143	#if defined(CONFIG_CONS_NONE) \|\| defined(CONFIG_CONS_USE_EXTC)
	144	#define CONFIG_BAUDRATE 230400
	145	#else
	146	#define CONFIG_BAUDRATE 9600
	147	#endif
	148
	149	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	150	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	151
	152	#undef CONFIG_WATCHDOG /* watchdog disabled */
	153
18225e8d JL	154	/*
	155	* BOOTP options
	156	*/
	157	#define CONFIG_BOOTP_SUBNETMASK
	158	#define CONFIG_BOOTP_GATEWAY
	159	#define CONFIG_BOOTP_HOSTNAME
	160	#define CONFIG_BOOTP_BOOTPATH
	161	#define CONFIG_BOOTP_BOOTFILESIZE
0f8c9768	162
acf02697 JL	163
	164	/*
	165	* Command line configuration.
	166	*/
	167	#include <config_cmd_default.h>
	168
	169	#define CONFIG_CMD_BEDBUG
	170	#define CONFIG_CMD_DATE
	171	#define CONFIG_CMD_DHCP
	172	#define CONFIG_CMD_DOC
	173	#define CONFIG_CMD_EEPROM
	174	#define CONFIG_CMD_I2C
	175	#define CONFIG_CMD_NFS
	176	#define CONFIG_CMD_SNTP
	177
5d232d0e	178	#ifdef CONFIG_PCI
acf02697 JL	179	#define CONFIG_CMD_PCI
	180	#endif
	181
0f8c9768	182
cc4a0cee	183	#define CONFIG_NAND_LEGACY
addb2e16	184
0f8c9768 WD	185	/*
	186	* Disk-On-Chip configuration
	187	*/
	188
	189	#define CFG_DOC_SHORT_TIMEOUT
	190	#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
	191
	192	#define CFG_DOC_SUPPORT_2000
	193	#define CFG_DOC_SUPPORT_MILLENNIUM
	194
	195	/*
	196	* Miscellaneous configurable options
	197	*/
	198	#define CFG_LONGHELP /* undef to save memory */
	199	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
acf02697	200	#if defined(CONFIG_CMD_KGDB)
0f8c9768 WD	201	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	202	#else
	203	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	204	#endif
	205	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	206	#define CFG_MAXARGS 16 /* max number of command args */
	207	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	208
	209	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	210	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	211
	212	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	213
	214	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	215
	216	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	217
ac6dbb85	218	#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
0f8c9768 WD	219
	220	/*
	221	* For booting Linux, the board info and command line data
	222	* have to be in the first 8 MB of memory, since this is
	223	* the maximum mapped by the Linux kernel during initialization.
	224	*/
	225	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	226
	227	/*-----------------------------------------------------------------------
	228	* Flash and Boot ROM mapping
	229	*/
efa329cb WD	230	#ifdef CONFIG_FLASH_32MB
	231	#define CFG_FLASH0_BASE 0x40000000
	232	#define CFG_FLASH0_SIZE 0x02000000
	233	#else
	234	#define CFG_FLASH0_BASE 0xFF000000
	235	#define CFG_FLASH0_SIZE 0x00800000
	236	#endif
3bac3513	237	#define CFG_BOOTROM_BASE 0xFF800000
0f8c9768	238	#define CFG_BOOTROM_SIZE 0x00080000
3bac3513	239	#define CFG_DOC_BASE 0xFF800000
0f8c9768 WD	240	#define CFG_DOC_SIZE 0x00100000
0f8c9768 WD	241
0f8c9768 WD	242	/* Flash bank size (for preliminary settings)
	243	*/
	244	#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
	245
	246	/*-----------------------------------------------------------------------
	247	* FLASH organization
	248	*/
	249	#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
efa329cb WD	250	#ifdef CONFIG_FLASH_32MB
	251	#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */
	252	#else
0f8c9768	253	#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
efa329cb	254	#endif
0f8c9768 WD	255	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	256	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	257
	258	#if 0
	259	/* Start port with environment in flash; switch to EEPROM later */
	260	#define CFG_ENV_IS_IN_FLASH 1
	261	#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
	262	#define CFG_ENV_SIZE 0x40000
	263	#define CFG_ENV_SECT_SIZE 0x40000
	264	#else
	265	/* Final version: environment in EEPROM */
bb1f8b4f	266	#define CONFIG_ENV_IS_IN_EEPROM 1
0f8c9768 WD	267	#define CFG_I2C_EEPROM_ADDR 0x58
	268	#define CFG_I2C_EEPROM_ADDR_LEN 1
	269	#define CFG_EEPROM_PAGE_WRITE_BITS 4
	270	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
3bac3513 WD	271	#define CFG_ENV_OFFSET 512
3bac3513 WD	272	#define CFG_ENV_SIZE (2048 - 512)
0f8c9768 WD	273	#endif
	274
	275	/*-----------------------------------------------------------------------
	276	* Hard Reset Configuration Words
	277	*
	278	* if you change bits in the HRCW, you must also change the CFG_*
	279	* defines for the various registers affected by the HRCW e.g. changing
	280	* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
	281	*/
	282	#if defined(CONFIG_BOOT_ROM)
	283	#define CFG_HRCW_MASTER (HRCW_BPS01 \| HRCW_CIP \| HRCW_ISB100 \| HRCW_BMS)
	284	#else
	285	#define CFG_HRCW_MASTER (HRCW_CIP \| HRCW_ISB100 \| HRCW_BMS)
	286	#endif
	287
	288	/* no slaves so just fill with zeros */
	289	#define CFG_HRCW_SLAVE1 0
	290	#define CFG_HRCW_SLAVE2 0
	291	#define CFG_HRCW_SLAVE3 0
	292	#define CFG_HRCW_SLAVE4 0
	293	#define CFG_HRCW_SLAVE5 0
	294	#define CFG_HRCW_SLAVE6 0
	295	#define CFG_HRCW_SLAVE7 0
	296
	297	/*-----------------------------------------------------------------------
	298	* Internal Memory Mapped Register
	299	*/
	300	#define CFG_IMMR 0xF0000000
	301
	302	/*-----------------------------------------------------------------------
	303	* Definitions for initial stack pointer and data area (in DPRAM)
	304	*/
	305	#define CFG_INIT_RAM_ADDR CFG_IMMR
	306	#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
	307	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
	308	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	309	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	310
	311	/*-----------------------------------------------------------------------
	312	* Start addresses for the final memory configuration
	313	* (Set up by the startup code)
	314	* Please note that CFG_SDRAM_BASE _must_ start at 0
	315	*
	316	* 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
	317	* is mapped at SDRAM_BASE2_PRELIM.
	318	*/
	319	#define CFG_SDRAM_BASE 0x00000000
	320	#define CFG_FLASH_BASE CFG_FLASH0_BASE
	321	#define CFG_MONITOR_BASE TEXT_BASE
	322	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	323	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
	324
	325	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	326	# define CFG_RAMBOOT
	327	#endif
	328
10f67017	329	#ifdef CONFIG_PCI
4d75a504 WD	330	#define CONFIG_PCI_PNP
4d75a504 WD	331	#define CONFIG_EEPRO100
53cf9435	332	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
10f67017	333	#endif
4d75a504	334
0f8c9768 WD	335	/*
	336	* Internal Definitions
	337	*
	338	* Boot Flags
	339	*/
	340	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
	341	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	342
	343
	344	/*-----------------------------------------------------------------------
	345	* Cache Configuration
	346	*/
	347	#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
acf02697	348	#if defined(CONFIG_CMD_KGDB)
0f8c9768 WD	349	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	350	#endif
	351
	352	/*-----------------------------------------------------------------------
	353	* HIDx - Hardware Implementation-dependent Registers 2-11
	354	*-----------------------------------------------------------------------
	355	* HID0 also contains cache control - initially enable both caches and
	356	* invalidate contents, then the final state leaves only the instruction
	357	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	358	* but Soft reset does not.
	359	*
	360	* HID1 has only read-only information - nothing to set.
	361	*/
	362	#define CFG_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|HID0_DCI\|\
8bde7f77	363	HID0_IFEM\|HID0_ABE)
0f8c9768 WD	364	#define CFG_HID0_FINAL (HID0_ICE\|HID0_IFEM\|HID0_ABE)
	365	#define CFG_HID2 0
	366
	367	/*-----------------------------------------------------------------------
	368	* RMR - Reset Mode Register 5-5
	369	*-----------------------------------------------------------------------
	370	* turn on Checkstop Reset Enable
	371	*/
	372	#define CFG_RMR RMR_CSRE
	373
	374	/*-----------------------------------------------------------------------
	375	* BCR - Bus Configuration 4-25
	376	*-----------------------------------------------------------------------
	377	*/
	378
	379	#define BCR_APD01 0x10000000
	380	#define CFG_BCR (BCR_APD01\|BCR_ETM\|BCR_LETM) /* 8260 mode */
	381
	382	/*-----------------------------------------------------------------------
	383	* SIUMCR - SIU Module Configuration 4-31
	384	*-----------------------------------------------------------------------
	385	*/
	386	#if 0
	387	#define CFG_SIUMCR (SIUMCR_DPPC00\|SIUMCR_APPC10\|SIUMCR_CS10PC01)
	388	#else
	389	#define CFG_SIUMCR (SIUMCR_DPPC10\|SIUMCR_APPC10)
	390	#endif
	391
	392
	393	/*-----------------------------------------------------------------------
	394	* SYPCR - System Protection Control 4-35
	395	* SYPCR can only be written once after reset!
	396	*-----------------------------------------------------------------------
	397	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	398	*/
	399	#if defined(CONFIG_WATCHDOG)
	400	#define CFG_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	401	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
0f8c9768 WD	402	#else
0f8c9768 WD	403	#define CFG_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	404	SYPCR_SWRI\|SYPCR_SWP)
0f8c9768 WD	405	#endif /* CONFIG_WATCHDOG */
	406
	407	/*-----------------------------------------------------------------------
	408	* TMCNTSC - Time Counter Status and Control 4-40
	409	*-----------------------------------------------------------------------
	410	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	411	* and enable Time Counter
	412	*/
	413	#define CFG_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
	414
	415	/*-----------------------------------------------------------------------
	416	* PISCR - Periodic Interrupt Status and Control 4-42
	417	*-----------------------------------------------------------------------
	418	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	419	* Periodic timer
	420	*/
	421	#define CFG_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
	422
	423	/*-----------------------------------------------------------------------
	424	* SCCR - System Clock Control 9-8
	425	*-----------------------------------------------------------------------
	426	*/
7152b1d0	427	#define CFG_SCCR (SCCR_DFBRG00)
0f8c9768 WD	428
	429	/*-----------------------------------------------------------------------
	430	* RCCR - RISC Controller Configuration 13-7
	431	*-----------------------------------------------------------------------
	432	*/
	433	#define CFG_RCCR 0
	434
	435	/*
	436	* Init Memory Controller:
	437	*
	438	* Bank Bus Machine PortSz Device
	439	* ---- --- ------- ------ ------
	440	* 0 60x GPCM 64 bit FLASH
	441	* 1 60x SDRAM 64 bit SDRAM
0f8c9768 WD	442	*
	443	*/
	444
	445	/* Initialize SDRAM on local bus
	446	*/
	447	#define CFG_INIT_LOCAL_SDRAM
	448
	449
	450	/* Minimum mask to separate preliminary
	451	* address ranges for CS[0:2]
	452	*/
	453	#define CFG_MIN_AM_MASK 0xC0000000
	454
efa329cb WD	455	/*
	456	* we use the same values for 32 MB and 128 MB SDRAM
	457	* refresh rate = 7.73 uS (64 MHz Bus Clock)
	458	*/
	459	#define CFG_MPTPR 0x2000
	460	#define CFG_PSRT 0x0E
0f8c9768 WD	461
	462	#define CFG_MRS_OFFS 0x00000000
	463
	464
	465	#if defined(CONFIG_BOOT_ROM)
	466	/*
	467	* Bank 0 - Boot ROM (8 bit wide)
	468	*/
	469	#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)\|\
	470	BRx_PS_8 \|\
	471	BRx_MS_GPCM_P \|\
	472	BRx_V)
	473
	474	#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) \|\
	475	ORxG_CSNT \|\
	476	ORxG_ACS_DIV1 \|\
	477	ORxG_SCY_3_CLK \|\
	478	ORxG_EHTR \|\
	479	ORxG_TRLX)
	480
	481	/*
	482	* Bank 1 - Flash (64 bit wide)
	483	*/
	484	#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) \|\
	485	BRx_PS_64 \|\
	486	BRx_MS_GPCM_P \|\
	487	BRx_V)
	488
	489	#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) \|\
	490	ORxG_CSNT \|\
	491	ORxG_ACS_DIV1 \|\
	492	ORxG_SCY_3_CLK \|\
	493	ORxG_EHTR \|\
	494	ORxG_TRLX)
	495
	496	#else /* ! CONFIG_BOOT_ROM */
	497
	498	/*
	499	* Bank 0 - Flash (64 bit wide)
	500	*/
	501	#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	502	BRx_PS_64 \|\
	503	BRx_MS_GPCM_P \|\
	504	BRx_V)
0f8c9768 WD	505
0f8c9768 WD	506	#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) \|\
8bde7f77 WD	507	ORxG_CSNT \|\
	508	ORxG_ACS_DIV1 \|\
	509	ORxG_SCY_3_CLK \|\
	510	ORxG_EHTR \|\
	511	ORxG_TRLX)
0f8c9768 WD	512
	513	/*
	514	* Bank 1 - Disk-On-Chip
	515	*/
	516	#define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) \|\
	517	BRx_PS_8 \|\
	518	BRx_MS_GPCM_P \|\
	519	BRx_V)
	520
	521	#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) \|\
	522	ORxG_CSNT \|\
	523	ORxG_ACS_DIV1 \|\
	524	ORxG_SCY_3_CLK \|\
	525	ORxG_EHTR \|\
	526	ORxG_TRLX)
	527
	528	#endif /* CONFIG_BOOT_ROM */
	529
	530	/* Bank 2 - SDRAM
	531	*/
efa329cb	532
0f8c9768 WD	533	#ifndef CFG_RAMBOOT
0f8c9768 WD	534	#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	535	BRx_PS_64 \|\
	536	BRx_MS_SDRAM_P \|\
	537	BRx_V)
0f8c9768 WD	538
	539	/* SDRAM initialization values for 8-column chips
	540	*/
	541	#define CFG_OR2_8COL (CFG_MIN_AM_MASK \|\
8bde7f77 WD	542	ORxS_BPD_4 \|\
	543	ORxS_ROWST_PBI0_A9 \|\
	544	ORxS_NUMR_12)
0f8c9768 WD	545
0f8c9768 WD	546	#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 \|\
8bde7f77 WD	547	PSDMR_BSMA_A14_A16 \|\
	548	PSDMR_SDA10_PBI0_A10 \|\
	549	PSDMR_RFRC_7_CLK \|\
	550	PSDMR_PRETOACT_2W \|\
	551	PSDMR_ACTTORW_1W \|\
	552	PSDMR_LDOTOPRE_1C \|\
	553	PSDMR_WRC_1C \|\
	554	PSDMR_CL_2)
0f8c9768 WD	555
	556	/* SDRAM initialization values for 9-column chips
	557	*/
	558	#define CFG_OR2_9COL (CFG_MIN_AM_MASK \|\
8bde7f77 WD	559	ORxS_BPD_4 \|\
	560	ORxS_ROWST_PBI0_A7 \|\
	561	ORxS_NUMR_13)
0f8c9768 WD	562
0f8c9768 WD	563	#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 \|\
8bde7f77 WD	564	PSDMR_BSMA_A13_A15 \|\
	565	PSDMR_SDA10_PBI0_A9 \|\
	566	PSDMR_RFRC_7_CLK \|\
	567	PSDMR_PRETOACT_2W \|\
	568	PSDMR_ACTTORW_1W \|\
	569	PSDMR_LDOTOPRE_1C \|\
	570	PSDMR_WRC_1C \|\
	571	PSDMR_CL_2)
0f8c9768 WD	572
	573	#define CFG_OR2_PRELIM CFG_OR2_9COL
	574	#define CFG_PSDMR CFG_PSDMR_9COL
	575
	576	#endif /* CFG_RAMBOOT */
	577
	578	#endif /* __CONFIG_H */