[J-u-boot.git] / include / configs / PM826.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#undef CFG_RAMBOOT

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
#define CONFIG_PM826		1	/* ...on a PM8260 module	*/

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; " 								\
	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " 	\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " 	\
	"bootm"

/* enable I2C and select the hardware/software driver */
#undef  CONFIG_HARD_I2C
#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
# define CFG_I2C_SPEED		50000
# define CFG_I2C_SLAVE		0xFE
/*
 * Software (bit-bang) I2C driver configuration
 */
#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
#define I2C_READ	((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
			else    iop->pdat &= ~0x00010000
#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
			else    iop->pdat &= ~0x00020000
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */


#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR	0x51

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef  CONFIG_CONS_NONE		/* define if console on something else*/
#define CONFIG_CONS_INDEX	2	/* which serial channel for console */

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 * from CONFIG_COMMANDS to remove support for networking.
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
#define	CONFIG_ETHER_INDEX    1		/* which SCC/FCC channel for ethernet */

#if (CONFIG_ETHER_INDEX == 1)
/*
 * - Rx-CLK is CLK11
 * - Tx-CLK is CLK10
 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 * - Enable Full Duplex in FSMR
 */
# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
# define CFG_CPMFCR_RAMTYPE	0
# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)

#endif /* CONFIG_ETHER_INDEX */

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	64000000	/* in Hz */

#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
#define CONFIG_BAUDRATE		230400
#else
#define CONFIG_BAUDRATE		9600
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
				 CFG_CMD_BEDBUG	| \
				 CFG_CMD_DATE	| \
				 CFG_CMD_EEPROM | \
				 CFG_CMD_I2C	| \
				 CFG_CMD_DOC)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Disk-On-Chip configuration
 */

#define CFG_DOC_SHORT_TIMEOUT
#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/

#define CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define	CFG_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * Flash and Boot ROM mapping
 */

#define	CFG_BOOTROM_BASE	0x60000000
#define	CFG_BOOTROM_SIZE	0x00080000
#define	CFG_FLASH0_BASE		0x40000000
#define	CFG_FLASH0_SIZE		0x02000000
#define CFG_DOC_BASE		0x60000000
#define CFG_DOC_SIZE		0x00100000


/* Flash bank size (for preliminary settings)
 */
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#if 0
/* Start port with environment in flash; switch to EEPROM later */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
#define CFG_ENV_SIZE		0x40000
#define CFG_ENV_SECT_SIZE	0x40000
#else
/* Final version: environment in EEPROM */
#define CFG_ENV_IS_IN_EEPROM	1
#define CFG_I2C_EEPROM_ADDR	0x58
#define CFG_I2C_EEPROM_ADDR_LEN	1
#define CFG_EEPROM_PAGE_WRITE_BITS	4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
#define CFG_ENV_OFFSET		0
#define CFG_ENV_SIZE		2048
#endif

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CFG_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 */
#if defined(CONFIG_BOOT_ROM)
#define CFG_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
#else
#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
#endif

/* no slaves so just fill with zeros */
#define CFG_HRCW_SLAVE1		0
#define CFG_HRCW_SLAVE2		0
#define CFG_HRCW_SLAVE3		0
#define CFG_HRCW_SLAVE4		0
#define CFG_HRCW_SLAVE5		0
#define CFG_HRCW_SLAVE6		0
#define CFG_HRCW_SLAVE7		0

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 *
 * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
 * is mapped at SDRAM_BASE2_PRELIM.
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		CFG_FLASH0_BASE
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
#define BOOTFLAG_WARM		0x02	/* Software reboot                 */


/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers                    2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
                                HID0_IFEM|HID0_ABE)
#define CFG_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE)
#define CFG_HID2        0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register                                     5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CFG_RMR         RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration                                       4-25
 *-----------------------------------------------------------------------
 */

#define BCR_APD01       0x10000000
#define CFG_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration                             4-31
 *-----------------------------------------------------------------------
 */
#if 0
#define CFG_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
#else
#define CFG_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
#endif


/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control                             4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
                         SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
                         SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control                     4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control                 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control                                   9-8
 *-----------------------------------------------------------------------
 */
#define CFG_SCCR        (SCCR_DFBRG01)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration                         13-7
 *-----------------------------------------------------------------------
 */
#define CFG_RCCR        0

/*
 * Init Memory Controller:
 *
 * Bank Bus     Machine PortSz  Device
 * ---- ---     ------- ------  ------
 *  0   60x     GPCM    64 bit  FLASH
 *  1   60x     SDRAM   64 bit  SDRAM
 *  2   Local   SDRAM   32 bit  SDRAM
 *
 */

	/* Initialize SDRAM on local bus
	 */
#define CFG_INIT_LOCAL_SDRAM


/* Minimum mask to separate preliminary
 * address ranges for CS[0:2]
 */
#define CFG_MIN_AM_MASK	0xC0000000

#define CFG_MPTPR       0x1F00

#define CFG_MRS_OFFS	0x00000000


#if defined(CONFIG_BOOT_ROM)
/*
 * Bank 0 - Boot ROM (8 bit wide)
 */
#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
			 BRx_PS_8			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_3_CLK			|\
			 ORxG_EHTR			|\
			 ORxG_TRLX)

/*
 * Bank 1 - Flash (64 bit wide)
 */
#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
			 BRx_PS_64			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_3_CLK			|\
			 ORxG_EHTR			|\
			 ORxG_TRLX)

#else	/* ! CONFIG_BOOT_ROM */

/*
 * Bank 0 - Flash (64 bit wide)
 */
#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
                         BRx_PS_64                      |\
                         BRx_MS_GPCM_P                  |\
                         BRx_V)

#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
                         ORxG_CSNT                      |\
                         ORxG_ACS_DIV1                  |\
                         ORxG_SCY_3_CLK                 |\
                         ORxG_EHTR                      |\
                         ORxG_TRLX)

/*
 * Bank 1 - Disk-On-Chip
 */
#define CFG_BR1_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
			 BRx_PS_8			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_3_CLK			|\
			 ORxG_EHTR			|\
			 ORxG_TRLX)

#endif /* CONFIG_BOOT_ROM */

/* Bank 2 - SDRAM
 */
#define CFG_PSRT        0x0F
#ifndef CFG_RAMBOOT
#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
                         BRx_PS_64                      |\
                         BRx_MS_SDRAM_P                 |\
                         BRx_V)

	/* SDRAM initialization values for 8-column chips
	 */
#define CFG_OR2_8COL    (CFG_MIN_AM_MASK	        |\
                         ORxS_BPD_4                     |\
                         ORxS_ROWST_PBI0_A9             |\
                         ORxS_NUMR_12)

#define CFG_PSDMR_8COL  (PSDMR_SDAM_A13_IS_A5           |\
                         PSDMR_BSMA_A14_A16             |\
                         PSDMR_SDA10_PBI0_A10           |\
                         PSDMR_RFRC_7_CLK               |\
                         PSDMR_PRETOACT_2W              |\
                         PSDMR_ACTTORW_1W               |\
                         PSDMR_LDOTOPRE_1C              |\
                         PSDMR_WRC_1C                   |\
                         PSDMR_CL_2)

	/* SDRAM initialization values for 9-column chips
	 */
#define CFG_OR2_9COL    (CFG_MIN_AM_MASK                |\
                         ORxS_BPD_4                     |\
                         ORxS_ROWST_PBI0_A7             |\
                         ORxS_NUMR_13)

#define CFG_PSDMR_9COL  (PSDMR_SDAM_A14_IS_A5           |\
                         PSDMR_BSMA_A13_A15             |\
                         PSDMR_SDA10_PBI0_A9            |\
                         PSDMR_RFRC_7_CLK               |\
                         PSDMR_PRETOACT_2W              |\
                         PSDMR_ACTTORW_1W               |\
                         PSDMR_LDOTOPRE_1C              |\
                         PSDMR_WRC_1C                   |\
                         PSDMR_CL_2)

#define CFG_OR2_PRELIM   CFG_OR2_9COL
#define CFG_PSDMR        CFG_PSDMR_9COL

#endif /* CFG_RAMBOOT */

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	#undef CFG_RAMBOOT
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37
	38	#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
	39	#define CONFIG_PM826 1 /* ...on a PM8260 module */
	40
	41	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	42
	43	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	44
	45	#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
	46
	47	#undef CONFIG_BOOTARGS
	48	#define CONFIG_BOOTCOMMAND \
	49	"bootp; " \
	50	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	51	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
	52	"bootm"
	53
	54	/* enable I2C and select the hardware/software driver */
	55	#undef CONFIG_HARD_I2C
	56	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
	57	# define CFG_I2C_SPEED 50000
	58	# define CFG_I2C_SLAVE 0xFE
	59	/*
	60	* Software (bit-bang) I2C driver configuration
	61	*/
	62	#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
	63	#define I2C_ACTIVE (iop->pdir \|= 0x00010000)
	64	#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
65	#define I2C_READ ((iop->pdat & 0x00010000) != 0)
66	#define I2C_SDA(bit) if(bit) iop->pdat \|= 0x00010000; \
67	else iop->pdat &= ~0x00010000
68	#define I2C_SCL(bit) if(bit) iop->pdat \|= 0x00020000; \
69	else iop->pdat &= ~0x00020000
70	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
71
72
73	#define CONFIG_RTC_PCF8563
74	#define CFG_I2C_RTC_ADDR 0x51
75
76	/*
77	* select serial console configuration
78	*
79	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
80	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
81	* for SCC).
82	*
83	* if CONFIG_CONS_NONE is defined, then the serial console routines must
84	* defined elsewhere (for example, on the cogent platform, there are serial
85	* ports on the motherboard which are used for the serial console - see
86	* cogent/cma101/serial.[ch]).
87	*/
88	#define CONFIG_CONS_ON_SMC /* define if console on SMC */
89	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
90	#undef CONFIG_CONS_NONE /* define if console on something else*/
91	#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
92
93	/*
94	* select ethernet configuration
95	*
96	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
97	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
98	* for FCC)
99	*
100	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
101	* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
102	* from CONFIG_COMMANDS to remove support for networking.
103	*/
104	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
105	#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
106	#undef CONFIG_ETHER_NONE /* define if ether on something else */
107	#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
108
109	#if (CONFIG_ETHER_INDEX == 1)
110	/*
111	* - Rx-CLK is CLK11
112	* - Tx-CLK is CLK10
113	* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
114	* - Enable Full Duplex in FSMR
115	*/
116	# define CFG_CMXFCR_MASK (CMXFCR_FC1\|CMXFCR_RF1CS_MSK\|CMXFCR_TF1CS_MSK)
117	# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11\|CMXFCR_TF1CS_CLK10)
118	# define CFG_CPMFCR_RAMTYPE 0
119	# define CFG_FCC_PSMR (FCC_PSMR_FDE\|FCC_PSMR_LPB)
120
121	#endif /* CONFIG_ETHER_INDEX */
122
123	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
124	#define CONFIG_8260_CLKIN 64000000 /* in Hz */
125
126	#if defined(CONFIG_CONS_NONE) \|\| defined(CONFIG_CONS_USE_EXTC)
127	#define CONFIG_BAUDRATE 230400
128	#else
129	#define CONFIG_BAUDRATE 9600
130	#endif
131
132	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
133	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
134
135	#undef CONFIG_WATCHDOG /* watchdog disabled */
136
137	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT\|CONFIG_BOOTP_BOOTFILESIZE)
138
139	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
140	CFG_CMD_BEDBUG \| \
141	CFG_CMD_DATE \| \
142	CFG_CMD_EEPROM \| \
6aff3115	143	CFG_CMD_I2C \| \
0f8c9768 WD	144	CFG_CMD_DOC)
	145
	146	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	147	#include <cmd_confdefs.h>
	148
	149	/*
	150	* Disk-On-Chip configuration
	151	*/
	152
	153	#define CFG_DOC_SHORT_TIMEOUT
	154	#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
	155
	156	#define CFG_DOC_SUPPORT_2000
	157	#define CFG_DOC_SUPPORT_MILLENNIUM
	158
	159	/*
	160	* Miscellaneous configurable options
	161	*/
	162	#define CFG_LONGHELP /* undef to save memory */
	163	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	164	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	165	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	166	#else
	167	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	168	#endif
	169	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	170	#define CFG_MAXARGS 16 /* max number of command args */
	171	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	172
	173	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	174	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	175
	176	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	177
	178	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	179
	180	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	181
	182	#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
	183
	184	/*
	185	* For booting Linux, the board info and command line data
	186	* have to be in the first 8 MB of memory, since this is
	187	* the maximum mapped by the Linux kernel during initialization.
	188	*/
	189	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	190
	191	/*-----------------------------------------------------------------------
	192	* Flash and Boot ROM mapping
	193	*/
	194
	195	#define CFG_BOOTROM_BASE 0x60000000
	196	#define CFG_BOOTROM_SIZE 0x00080000
	197	#define CFG_FLASH0_BASE 0x40000000
	198	#define CFG_FLASH0_SIZE 0x02000000
	199	#define CFG_DOC_BASE 0x60000000
	200	#define CFG_DOC_SIZE 0x00100000
	201
	202
	203	/* Flash bank size (for preliminary settings)
	204	*/
	205	#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
	206
	207	/*-----------------------------------------------------------------------
208	* FLASH organization
209	*/
210	#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
211	#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
212
213	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
214	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
215
216	#if 0
217	/* Start port with environment in flash; switch to EEPROM later */
218	#define CFG_ENV_IS_IN_FLASH 1
219	#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
220	#define CFG_ENV_SIZE 0x40000
221	#define CFG_ENV_SECT_SIZE 0x40000
222	#else
223	/* Final version: environment in EEPROM */
224	#define CFG_ENV_IS_IN_EEPROM 1
225	#define CFG_I2C_EEPROM_ADDR 0x58
226	#define CFG_I2C_EEPROM_ADDR_LEN 1
227	#define CFG_EEPROM_PAGE_WRITE_BITS 4
228	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
229	#define CFG_ENV_OFFSET 0
230	#define CFG_ENV_SIZE 2048
231	#endif
232
233	/*-----------------------------------------------------------------------
234	* Hard Reset Configuration Words
235	*
236	* if you change bits in the HRCW, you must also change the CFG_*
237	* defines for the various registers affected by the HRCW e.g. changing
238	* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
239	*/
240	#if defined(CONFIG_BOOT_ROM)
241	#define CFG_HRCW_MASTER (HRCW_BPS01 \| HRCW_CIP \| HRCW_ISB100 \| HRCW_BMS)
242	#else
243	#define CFG_HRCW_MASTER (HRCW_CIP \| HRCW_ISB100 \| HRCW_BMS)
244	#endif
245
246	/* no slaves so just fill with zeros */
247	#define CFG_HRCW_SLAVE1 0
248	#define CFG_HRCW_SLAVE2 0
249	#define CFG_HRCW_SLAVE3 0
250	#define CFG_HRCW_SLAVE4 0
251	#define CFG_HRCW_SLAVE5 0
252	#define CFG_HRCW_SLAVE6 0
253	#define CFG_HRCW_SLAVE7 0
254
255	/*-----------------------------------------------------------------------
256	* Internal Memory Mapped Register
257	*/
258	#define CFG_IMMR 0xF0000000
259
260	/*-----------------------------------------------------------------------
261	* Definitions for initial stack pointer and data area (in DPRAM)
262	*/
263	#define CFG_INIT_RAM_ADDR CFG_IMMR
264	#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
265	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
266	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
267	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
268
269	/*-----------------------------------------------------------------------
270	* Start addresses for the final memory configuration
271	* (Set up by the startup code)
272	* Please note that CFG_SDRAM_BASE _must_ start at 0
273	*
274	* 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
275	* is mapped at SDRAM_BASE2_PRELIM.
276	*/
277	#define CFG_SDRAM_BASE 0x00000000
278	#define CFG_FLASH_BASE CFG_FLASH0_BASE
279	#define CFG_MONITOR_BASE TEXT_BASE
280	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
281	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
282
283	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
284	# define CFG_RAMBOOT
285	#endif
286
287	/*
288	* Internal Definitions
289	*
290	* Boot Flags
291	*/
292	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
293	#define BOOTFLAG_WARM 0x02 /* Software reboot */
294
295
296	/*-----------------------------------------------------------------------
297	* Cache Configuration
298	*/
299	#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
300	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
301	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
302	#endif
303
304	/*-----------------------------------------------------------------------
305	* HIDx - Hardware Implementation-dependent Registers 2-11
306	*-----------------------------------------------------------------------
307	* HID0 also contains cache control - initially enable both caches and
308	* invalidate contents, then the final state leaves only the instruction
309	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
310	* but Soft reset does not.
311	*
312	* HID1 has only read-only information - nothing to set.
313	*/
314	#define CFG_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|HID0_DCI\|\
315	HID0_IFEM\|HID0_ABE)
316	#define CFG_HID0_FINAL (HID0_ICE\|HID0_IFEM\|HID0_ABE)
317	#define CFG_HID2 0
318
319	/*-----------------------------------------------------------------------
320	* RMR - Reset Mode Register 5-5
321	*-----------------------------------------------------------------------
322	* turn on Checkstop Reset Enable
323	*/
324	#define CFG_RMR RMR_CSRE
325
326	/*-----------------------------------------------------------------------
327	* BCR - Bus Configuration 4-25
328	*-----------------------------------------------------------------------
329	*/
330
331	#define BCR_APD01 0x10000000
332	#define CFG_BCR (BCR_APD01\|BCR_ETM\|BCR_LETM) /* 8260 mode */
333
334	/*-----------------------------------------------------------------------
335	* SIUMCR - SIU Module Configuration 4-31
336	*-----------------------------------------------------------------------
337	*/
338	#if 0
339	#define CFG_SIUMCR (SIUMCR_DPPC00\|SIUMCR_APPC10\|SIUMCR_CS10PC01)
340	#else
341	#define CFG_SIUMCR (SIUMCR_DPPC10\|SIUMCR_APPC10)
342	#endif
343
344
345	/*-----------------------------------------------------------------------
346	* SYPCR - System Protection Control 4-35
347	* SYPCR can only be written once after reset!
348	*-----------------------------------------------------------------------
349	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
350	*/
351	#if defined(CONFIG_WATCHDOG)
352	#define CFG_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
353	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
354	#else
355	#define CFG_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
356	SYPCR_SWRI\|SYPCR_SWP)
357	#endif /* CONFIG_WATCHDOG */
358
359	/*-----------------------------------------------------------------------
360	* TMCNTSC - Time Counter Status and Control 4-40
361	*-----------------------------------------------------------------------
362	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
363	* and enable Time Counter
364	*/
365	#define CFG_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
366
367	/*-----------------------------------------------------------------------
368	* PISCR - Periodic Interrupt Status and Control 4-42
369	*-----------------------------------------------------------------------
370	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
371	* Periodic timer
372	*/
373	#define CFG_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
374
375	/*-----------------------------------------------------------------------
376	* SCCR - System Clock Control 9-8
377	*-----------------------------------------------------------------------
378	*/
379	#define CFG_SCCR (SCCR_DFBRG01)
380
381	/*-----------------------------------------------------------------------
382	* RCCR - RISC Controller Configuration 13-7
383	*-----------------------------------------------------------------------
384	*/
385	#define CFG_RCCR 0
386
387	/*
388	* Init Memory Controller:
389	*
390	* Bank Bus Machine PortSz Device
391	* ---- --- ------- ------ ------
392	* 0 60x GPCM 64 bit FLASH
393	* 1 60x SDRAM 64 bit SDRAM
394	* 2 Local SDRAM 32 bit SDRAM
395	*
396	*/
397
398	/* Initialize SDRAM on local bus
399	*/
400	#define CFG_INIT_LOCAL_SDRAM
401
402
403	/* Minimum mask to separate preliminary
404	* address ranges for CS[0:2]
405	*/
406	#define CFG_MIN_AM_MASK 0xC0000000
407
408	#define CFG_MPTPR 0x1F00
409
410	#define CFG_MRS_OFFS 0x00000000
411
412
413	#if defined(CONFIG_BOOT_ROM)
414	/*
415	* Bank 0 - Boot ROM (8 bit wide)
416	*/
417	#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)\|\
418	BRx_PS_8 \|\
419	BRx_MS_GPCM_P \|\
420	BRx_V)
421
422	#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) \|\
423	ORxG_CSNT \|\
424	ORxG_ACS_DIV1 \|\
425	ORxG_SCY_3_CLK \|\
426	ORxG_EHTR \|\
427	ORxG_TRLX)
428
429	/*
430	* Bank 1 - Flash (64 bit wide)
431	*/
432	#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) \|\
433	BRx_PS_64 \|\
434	BRx_MS_GPCM_P \|\
435	BRx_V)
436
437	#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) \|\
438	ORxG_CSNT \|\
439	ORxG_ACS_DIV1 \|\
440	ORxG_SCY_3_CLK \|\
441	ORxG_EHTR \|\
442	ORxG_TRLX)
443
444	#else /* ! CONFIG_BOOT_ROM */
445
446	/*
447	* Bank 0 - Flash (64 bit wide)
448	*/
449	#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) \|\
450	BRx_PS_64 \|\
451	BRx_MS_GPCM_P \|\
452	BRx_V)
453
454	#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) \|\
455	ORxG_CSNT \|\
456	ORxG_ACS_DIV1 \|\
457	ORxG_SCY_3_CLK \|\
458	ORxG_EHTR \|\
459	ORxG_TRLX)
460
461	/*
462	* Bank 1 - Disk-On-Chip
463	*/
464	#define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) \|\
465	BRx_PS_8 \|\
466	BRx_MS_GPCM_P \|\
467	BRx_V)
468
469	#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) \|\
470	ORxG_CSNT \|\
471	ORxG_ACS_DIV1 \|\
472	ORxG_SCY_3_CLK \|\
473	ORxG_EHTR \|\
474	ORxG_TRLX)
475
476	#endif /* CONFIG_BOOT_ROM */
477
478	/* Bank 2 - SDRAM
479	*/
480	#define CFG_PSRT 0x0F
481	#ifndef CFG_RAMBOOT
482	#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) \|\
483	BRx_PS_64 \|\
484	BRx_MS_SDRAM_P \|\
485	BRx_V)
486
487	/* SDRAM initialization values for 8-column chips
488	*/
489	#define CFG_OR2_8COL (CFG_MIN_AM_MASK \|\
490	ORxS_BPD_4 \|\
491	ORxS_ROWST_PBI0_A9 \|\
492	ORxS_NUMR_12)
493
494	#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 \|\
495	PSDMR_BSMA_A14_A16 \|\
496	PSDMR_SDA10_PBI0_A10 \|\
497	PSDMR_RFRC_7_CLK \|\
498	PSDMR_PRETOACT_2W \|\
499	PSDMR_ACTTORW_1W \|\
500	PSDMR_LDOTOPRE_1C \|\
501	PSDMR_WRC_1C \|\
502	PSDMR_CL_2)
503
504	/* SDRAM initialization values for 9-column chips
505	*/
506	#define CFG_OR2_9COL (CFG_MIN_AM_MASK \|\
507	ORxS_BPD_4 \|\
508	ORxS_ROWST_PBI0_A7 \|\
509	ORxS_NUMR_13)
510
511	#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 \|\
512	PSDMR_BSMA_A13_A15 \|\
513	PSDMR_SDA10_PBI0_A9 \|\
514	PSDMR_RFRC_7_CLK \|\
515	PSDMR_PRETOACT_2W \|\
516	PSDMR_ACTTORW_1W \|\
517	PSDMR_LDOTOPRE_1C \|\
518	PSDMR_WRC_1C \|\
519	PSDMR_CL_2)
520
521	#define CFG_OR2_PRELIM CFG_OR2_9COL
522	#define CFG_PSDMR CFG_PSDMR_9COL
523
524	#endif /* CFG_RAMBOOT */
525
526	#endif /* __CONFIG_H */