[J-u-boot.git] / include / phy.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 *	Andy Fleming <[email protected]>
 *
 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
 */

#ifndef _PHY_H
#define _PHY_H

#include <linux/list.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>

#define PHY_FIXED_ID		0xa5a55a5a

#define PHY_MAX_ADDR 32

#define PHY_FLAG_BROKEN_RESET	(1 << 0) /* soft reset not supported */

#define PHY_DEFAULT_FEATURES	(SUPPORTED_Autoneg | \
				 SUPPORTED_TP | \
				 SUPPORTED_MII)

#define PHY_10BT_FEATURES	(SUPPORTED_10baseT_Half | \
				 SUPPORTED_10baseT_Full)

#define PHY_100BT_FEATURES	(SUPPORTED_100baseT_Half | \
				 SUPPORTED_100baseT_Full)

#define PHY_1000BT_FEATURES	(SUPPORTED_1000baseT_Half | \
				 SUPPORTED_1000baseT_Full)

#define PHY_BASIC_FEATURES	(PHY_10BT_FEATURES | \
				 PHY_100BT_FEATURES | \
				 PHY_DEFAULT_FEATURES)

#define PHY_GBIT_FEATURES	(PHY_BASIC_FEATURES | \
				 PHY_1000BT_FEATURES)

#define PHY_10G_FEATURES	(PHY_GBIT_FEATURES | \
				SUPPORTED_10000baseT_Full)

#ifndef PHY_ANEG_TIMEOUT
#define PHY_ANEG_TIMEOUT	4000
#endif


typedef enum {
	PHY_INTERFACE_MODE_MII,
	PHY_INTERFACE_MODE_GMII,
	PHY_INTERFACE_MODE_SGMII,
	PHY_INTERFACE_MODE_SGMII_2500,
	PHY_INTERFACE_MODE_QSGMII,
	PHY_INTERFACE_MODE_TBI,
	PHY_INTERFACE_MODE_RMII,
	PHY_INTERFACE_MODE_RGMII,
	PHY_INTERFACE_MODE_RGMII_ID,
	PHY_INTERFACE_MODE_RGMII_RXID,
	PHY_INTERFACE_MODE_RGMII_TXID,
	PHY_INTERFACE_MODE_RTBI,
	PHY_INTERFACE_MODE_XGMII,
	PHY_INTERFACE_MODE_XAUI,
	PHY_INTERFACE_MODE_RXAUI,
	PHY_INTERFACE_MODE_SFI,
	PHY_INTERFACE_MODE_INTERNAL,
	PHY_INTERFACE_MODE_NONE,	/* Must be last */

	PHY_INTERFACE_MODE_COUNT,
} phy_interface_t;

static const char *phy_interface_strings[] = {
	[PHY_INTERFACE_MODE_MII]		= "mii",
	[PHY_INTERFACE_MODE_GMII]		= "gmii",
	[PHY_INTERFACE_MODE_SGMII]		= "sgmii",
	[PHY_INTERFACE_MODE_SGMII_2500]		= "sgmii-2500",
	[PHY_INTERFACE_MODE_QSGMII]		= "qsgmii",
	[PHY_INTERFACE_MODE_TBI]		= "tbi",
	[PHY_INTERFACE_MODE_RMII]		= "rmii",
	[PHY_INTERFACE_MODE_RGMII]		= "rgmii",
	[PHY_INTERFACE_MODE_RGMII_ID]		= "rgmii-id",
	[PHY_INTERFACE_MODE_RGMII_RXID]		= "rgmii-rxid",
	[PHY_INTERFACE_MODE_RGMII_TXID]		= "rgmii-txid",
	[PHY_INTERFACE_MODE_RTBI]		= "rtbi",
	[PHY_INTERFACE_MODE_XGMII]		= "xgmii",
	[PHY_INTERFACE_MODE_XAUI]		= "xaui",
	[PHY_INTERFACE_MODE_RXAUI]		= "rxaui",
	[PHY_INTERFACE_MODE_SFI]		= "sfi",
	[PHY_INTERFACE_MODE_INTERNAL]		= "internal",
	[PHY_INTERFACE_MODE_NONE]		= "",
};

static inline const char *phy_string_for_interface(phy_interface_t i)
{
	/* Default to unknown */
	if (i > PHY_INTERFACE_MODE_NONE)
		i = PHY_INTERFACE_MODE_NONE;

	return phy_interface_strings[i];
}


struct phy_device;

#define MDIO_NAME_LEN 32

struct mii_dev {
	struct list_head link;
	char name[MDIO_NAME_LEN];
	void *priv;
	int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
	int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
			u16 val);
	int (*reset)(struct mii_dev *bus);
	struct phy_device *phymap[PHY_MAX_ADDR];
	u32 phy_mask;
};

/* struct phy_driver: a structure which defines PHY behavior
 *
 * uid will contain a number which represents the PHY.  During
 * startup, the driver will poll the PHY to find out what its
 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 * gotten from the PHY will be masked to
 * discard any bits which may change based on revision numbers
 * unimportant to functionality
 *
 */
struct phy_driver {
	char *name;
	unsigned int uid;
	unsigned int mask;
	unsigned int mmds;

	u32 features;

	/* Called to do any driver startup necessities */
	/* Will be called during phy_connect */
	int (*probe)(struct phy_device *phydev);

	/* Called to configure the PHY, and modify the controller
	 * based on the results.  Should be called after phy_connect */
	int (*config)(struct phy_device *phydev);

	/* Called when starting up the controller */
	int (*startup)(struct phy_device *phydev);

	/* Called when bringing down the controller */
	int (*shutdown)(struct phy_device *phydev);

	int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
	int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
			u16 val);
	struct list_head list;
};

struct phy_device {
	/* Information about the PHY type */
	/* And management functions */
	struct mii_dev *bus;
	struct phy_driver *drv;
	void *priv;

#ifdef CONFIG_DM_ETH
	struct udevice *dev;
#else
	struct eth_device *dev;
#endif

	/* forced speed & duplex (no autoneg)
	 * partner speed & duplex & pause (autoneg)
	 */
	int speed;
	int duplex;

	/* The most recently read link state */
	int link;
	int port;
	phy_interface_t interface;

	u32 advertising;
	u32 supported;
	u32 mmds;

	int autoneg;
	int addr;
	int pause;
	int asym_pause;
	u32 phy_id;
	u32 flags;
};

struct fixed_link {
	int phy_id;
	int duplex;
	int link_speed;
	int pause;
	int asym_pause;
};

static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
	struct mii_dev *bus = phydev->bus;

	return bus->read(bus, phydev->addr, devad, regnum);
}

static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
			u16 val)
{
	struct mii_dev *bus = phydev->bus;

	return bus->write(bus, phydev->addr, devad, regnum, val);
}

#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;

/* For now, XGMII is the only 10G interface */
static inline int is_10g_interface(phy_interface_t interface)
{
	return interface == PHY_INTERFACE_MODE_XGMII;
}

#endif

int phy_init(void);
int phy_reset(struct phy_device *phydev);
struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
		phy_interface_t interface);
#ifdef CONFIG_DM_ETH
void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct udevice *dev,
				phy_interface_t interface);
#else
void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct eth_device *dev,
				phy_interface_t interface);
#endif
int phy_startup(struct phy_device *phydev);
int phy_config(struct phy_device *phydev);
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int phy_set_supported(struct phy_device *phydev, u32 max_speed);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_restart_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
int genphy_parse_link(struct phy_device *phydev);
int genphy_config(struct phy_device *phydev);
int genphy_startup(struct phy_device *phydev);
int genphy_shutdown(struct phy_device *phydev);
int gen10g_config(struct phy_device *phydev);
int gen10g_startup(struct phy_device *phydev);
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);

int phy_b53_init(void);
int phy_mv88e61xx_init(void);
int phy_aquantia_init(void);
int phy_atheros_init(void);
int phy_broadcom_init(void);
int phy_cortina_init(void);
int phy_davicom_init(void);
int phy_et1011c_init(void);
int phy_lxt_init(void);
int phy_marvell_init(void);
int phy_micrel_ksz8xxx_init(void);
int phy_micrel_ksz90x1_init(void);
int phy_meson_gxl_init(void);
int phy_natsemi_init(void);
int phy_realtek_init(void);
int phy_smsc_init(void);
int phy_teranetics_init(void);
int phy_ti_init(void);
int phy_vitesse_init(void);
int phy_xilinx_init(void);
int phy_mscc_init(void);
int phy_fixed_init(void);

int board_phy_config(struct phy_device *phydev);
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);

/**
 * phy_get_interface_by_name() - Look up a PHY interface name
 *
 * @str:	PHY interface name, e.g. "mii"
 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
 */
int phy_get_interface_by_name(const char *str);

/**
 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
 * is RGMII (all variants)
 * @phydev: the phy_device struct
 */
static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
{
	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
}

/**
 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
 * is SGMII (all variants)
 * @phydev: the phy_device struct
 */
static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
{
	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
		phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
}

/* PHY UIDs for various PHYs that are referenced in external code */
#define PHY_UID_CS4340  0x13e51002
#define PHY_UID_CS4223  0x03e57003
#define PHY_UID_TN2020	0x00a19410

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
5f184715 AF	2	/*
5f184715 AF	3	* Copyright 2011 Freescale Semiconductor, Inc.
b21f87a3	4	* Andy Fleming <[email protected]>
5f184715	5	*
5f184715 AF	6	* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
	7	*/
	8
	9	#ifndef _PHY_H
	10	#define _PHY_H
	11
	12	#include <linux/list.h>
	13	#include <linux/mii.h>
	14	#include <linux/ethtool.h>
	15	#include <linux/mdio.h>
	16
db40c1aa HS	17	#define PHY_FIXED_ID 0xa5a55a5a
db40c1aa HS	18
5f184715 AF	19	#define PHY_MAX_ADDR 32
5f184715 AF	20
ddcd1f30 SX	21	#define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */
ddcd1f30 SX	22
4dae610b	23	#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg \| \
5f184715 AF	24	SUPPORTED_TP \| \
	25	SUPPORTED_MII)
	26
4dae610b FF	27	#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half \| \
	28	SUPPORTED_10baseT_Full)
	29
	30	#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half \| \
	31	SUPPORTED_100baseT_Full)
	32
	33	#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half \| \
5f184715 AF	34	SUPPORTED_1000baseT_Full)
5f184715 AF	35
4dae610b FF	36	#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES \| \
	37	PHY_100BT_FEATURES \| \
	38	PHY_DEFAULT_FEATURES)
	39
	40	#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES \| \
	41	PHY_1000BT_FEATURES)
	42
5f184715 AF	43	#define PHY_10G_FEATURES (PHY_GBIT_FEATURES \| \
	44	SUPPORTED_10000baseT_Full)
	45
4fb3f0c8	46	#ifndef PHY_ANEG_TIMEOUT
5f184715	47	#define PHY_ANEG_TIMEOUT 4000
4fb3f0c8	48	#endif
5f184715 AF	49
	50
	51	typedef enum {
	52	PHY_INTERFACE_MODE_MII,
	53	PHY_INTERFACE_MODE_GMII,
	54	PHY_INTERFACE_MODE_SGMII,
c35f8693	55	PHY_INTERFACE_MODE_SGMII_2500,
7794b1a7	56	PHY_INTERFACE_MODE_QSGMII,
5f184715 AF	57	PHY_INTERFACE_MODE_TBI,
	58	PHY_INTERFACE_MODE_RMII,
	59	PHY_INTERFACE_MODE_RGMII,
	60	PHY_INTERFACE_MODE_RGMII_ID,
	61	PHY_INTERFACE_MODE_RGMII_RXID,
	62	PHY_INTERFACE_MODE_RGMII_TXID,
	63	PHY_INTERFACE_MODE_RTBI,
	64	PHY_INTERFACE_MODE_XGMII,
d11e9347 SR	65	PHY_INTERFACE_MODE_XAUI,
	66	PHY_INTERFACE_MODE_RXAUI,
	67	PHY_INTERFACE_MODE_SFI,
ff114e0f	68	PHY_INTERFACE_MODE_INTERNAL,
c74c8e66 SG	69	PHY_INTERFACE_MODE_NONE, /* Must be last */
	70
	71	PHY_INTERFACE_MODE_COUNT,
5f184715 AF	72	} phy_interface_t;
	73
	74	static const char *phy_interface_strings[] = {
	75	[PHY_INTERFACE_MODE_MII] = "mii",
	76	[PHY_INTERFACE_MODE_GMII] = "gmii",
	77	[PHY_INTERFACE_MODE_SGMII] = "sgmii",
c35f8693	78	[PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
7794b1a7	79	[PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
5f184715 AF	80	[PHY_INTERFACE_MODE_TBI] = "tbi",
	81	[PHY_INTERFACE_MODE_RMII] = "rmii",
	82	[PHY_INTERFACE_MODE_RGMII] = "rgmii",
	83	[PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
	84	[PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
	85	[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
	86	[PHY_INTERFACE_MODE_RTBI] = "rtbi",
	87	[PHY_INTERFACE_MODE_XGMII] = "xgmii",
d11e9347 SR	88	[PHY_INTERFACE_MODE_XAUI] = "xaui",
	89	[PHY_INTERFACE_MODE_RXAUI] = "rxaui",
	90	[PHY_INTERFACE_MODE_SFI] = "sfi",
ff114e0f	91	[PHY_INTERFACE_MODE_INTERNAL] = "internal",
5f184715 AF	92	[PHY_INTERFACE_MODE_NONE] = "",
	93	};
	94
	95	static inline const char *phy_string_for_interface(phy_interface_t i)
	96	{
	97	/* Default to unknown */
	98	if (i > PHY_INTERFACE_MODE_NONE)
	99	i = PHY_INTERFACE_MODE_NONE;
	100
	101	return phy_interface_strings[i];
	102	}
	103
	104
	105	struct phy_device;
	106
	107	#define MDIO_NAME_LEN 32
	108
	109	struct mii_dev {
	110	struct list_head link;
	111	char name[MDIO_NAME_LEN];
	112	void *priv;
	113	int (read)(struct mii_dev bus, int addr, int devad, int reg);
	114	int (write)(struct mii_dev bus, int addr, int devad, int reg,
	115	u16 val);
	116	int (reset)(struct mii_dev bus);
	117	struct phy_device *phymap[PHY_MAX_ADDR];
	118	u32 phy_mask;
	119	};
	120
	121	/* struct phy_driver: a structure which defines PHY behavior
	122	*
	123	* uid will contain a number which represents the PHY. During
	124	* startup, the driver will poll the PHY to find out what its
	125	* UID--as defined by registers 2 and 3--is. The 32-bit result
	126	* gotten from the PHY will be masked to
	127	* discard any bits which may change based on revision numbers
	128	* unimportant to functionality
	129	*
	130	*/
	131	struct phy_driver {
	132	char *name;
	133	unsigned int uid;
	134	unsigned int mask;
	135	unsigned int mmds;
	136
	137	u32 features;
	138
	139	/* Called to do any driver startup necessities */
	140	/* Will be called during phy_connect */
	141	int (probe)(struct phy_device phydev);
	142
	143	/* Called to configure the PHY, and modify the controller
	144	* based on the results. Should be called after phy_connect */
	145	int (config)(struct phy_device phydev);
	146
	147	/* Called when starting up the controller */
	148	int (startup)(struct phy_device phydev);
	149
	150	/* Called when bringing down the controller */
	151	int (shutdown)(struct phy_device phydev);
	152
b71841b9 SB	153	int (readext)(struct phy_device phydev, int addr, int devad, int reg);
	154	int (writeext)(struct phy_device phydev, int addr, int devad, int reg,
	155	u16 val);
5f184715 AF	156	struct list_head list;
	157	};
	158
	159	struct phy_device {
	160	/* Information about the PHY type */
	161	/* And management functions */
	162	struct mii_dev *bus;
	163	struct phy_driver *drv;
	164	void *priv;
	165
c74c8e66 SG	166	#ifdef CONFIG_DM_ETH
	167	struct udevice *dev;
	168	#else
5f184715	169	struct eth_device *dev;
c74c8e66	170	#endif
5f184715 AF	171
	172	/* forced speed & duplex (no autoneg)
	173	* partner speed & duplex & pause (autoneg)
	174	*/
	175	int speed;
	176	int duplex;
	177
	178	/* The most recently read link state */
	179	int link;
	180	int port;
	181	phy_interface_t interface;
	182
	183	u32 advertising;
	184	u32 supported;
	185	u32 mmds;
	186
	187	int autoneg;
	188	int addr;
	189	int pause;
	190	int asym_pause;
	191	u32 phy_id;
	192	u32 flags;
	193	};
	194
f55a776c SX	195	struct fixed_link {
	196	int phy_id;
	197	int duplex;
	198	int link_speed;
	199	int pause;
	200	int asym_pause;
	201	};
	202
5f184715 AF	203	static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
	204	{
	205	struct mii_dev *bus = phydev->bus;
	206
	207	return bus->read(bus, phydev->addr, devad, regnum);
	208	}
	209
	210	static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
	211	u16 val)
	212	{
	213	struct mii_dev *bus = phydev->bus;
	214
	215	return bus->write(bus, phydev->addr, devad, regnum, val);
	216	}
	217
	218	#ifdef CONFIG_PHYLIB_10G
	219	extern struct phy_driver gen10g_driver;
	220
	221	/* For now, XGMII is the only 10G interface */
	222	static inline int is_10g_interface(phy_interface_t interface)
	223	{
	224	return interface == PHY_INTERFACE_MODE_XGMII;
	225	}
	226
	227	#endif
	228
	229	int phy_init(void);
	230	int phy_reset(struct phy_device *phydev);
1adb406b TK	231	struct phy_device phy_find_by_mask(struct mii_dev bus, unsigned phy_mask,
1adb406b TK	232	phy_interface_t interface);
c74c8e66 SG	233	#ifdef CONFIG_DM_ETH
	234	void phy_connect_dev(struct phy_device phydev, struct udevice dev);
	235	struct phy_device phy_connect(struct mii_dev bus, int addr,
	236	struct udevice *dev,
	237	phy_interface_t interface);
	238	#else
1adb406b	239	void phy_connect_dev(struct phy_device phydev, struct eth_device dev);
5f184715 AF	240	struct phy_device phy_connect(struct mii_dev bus, int addr,
	241	struct eth_device *dev,
	242	phy_interface_t interface);
c74c8e66	243	#endif
5f184715 AF	244	int phy_startup(struct phy_device *phydev);
	245	int phy_config(struct phy_device *phydev);
	246	int phy_shutdown(struct phy_device *phydev);
	247	int phy_register(struct phy_driver *drv);
b18acb0a	248	int phy_set_supported(struct phy_device *phydev, u32 max_speed);
5f184715	249	int genphy_config_aneg(struct phy_device *phydev);
8682aba7	250	int genphy_restart_aneg(struct phy_device *phydev);
5f184715	251	int genphy_update_link(struct phy_device *phydev);
e2043f5c	252	int genphy_parse_link(struct phy_device *phydev);
5f184715 AF	253	int genphy_config(struct phy_device *phydev);
	254	int genphy_startup(struct phy_device *phydev);
	255	int genphy_shutdown(struct phy_device *phydev);
	256	int gen10g_config(struct phy_device *phydev);
	257	int gen10g_startup(struct phy_device *phydev);
	258	int gen10g_shutdown(struct phy_device *phydev);
	259	int gen10g_discover_mmds(struct phy_device *phydev);
	260
137963d7	261	int phy_b53_init(void);
24ae3961	262	int phy_mv88e61xx_init(void);
f7c38cf8	263	int phy_aquantia_init(void);
9082eeac AF	264	int phy_atheros_init(void);
9082eeac AF	265	int phy_broadcom_init(void);
9b18e519	266	int phy_cortina_init(void);
9082eeac	267	int phy_davicom_init(void);
f485c8a3	268	int phy_et1011c_init(void);
9082eeac AF	269	int phy_lxt_init(void);
9082eeac AF	270	int phy_marvell_init(void);
d397f7c4 AG	271	int phy_micrel_ksz8xxx_init(void);
d397f7c4 AG	272	int phy_micrel_ksz90x1_init(void);
8995a96d	273	int phy_meson_gxl_init(void);
9082eeac AF	274	int phy_natsemi_init(void);
9082eeac AF	275	int phy_realtek_init(void);
b6abf555	276	int phy_smsc_init(void);
9082eeac	277	int phy_teranetics_init(void);
721aed79	278	int phy_ti_init(void);
9082eeac	279	int phy_vitesse_init(void);
ed6fad3e	280	int phy_xilinx_init(void);
a5fd13ad	281	int phy_mscc_init(void);
db40c1aa	282	int phy_fixed_init(void);
a836626c	283
2fb63964	284	int board_phy_config(struct phy_device *phydev);
5707d5ff	285	int get_phy_id(struct mii_dev bus, int addr, int devad, u32 phy_id);
2fb63964	286
c74c8e66 SG	287	/**
	288	* phy_get_interface_by_name() - Look up a PHY interface name
	289	*
	290	* @str: PHY interface name, e.g. "mii"
	291	* @return PHY_INTERFACE_MODE_... value, or -1 if not found
	292	*/
	293	int phy_get_interface_by_name(const char *str);
	294
3ab72fe8 DM	295	/**
	296	* phy_interface_is_rgmii - Convenience function for testing if a PHY interface
	297	* is RGMII (all variants)
	298	* @phydev: the phy_device struct
	299	*/
	300	static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
	301	{
	302	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
	303	phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
	304	}
	305
3c221af3 DM	306	/**
	307	* phy_interface_is_sgmii - Convenience function for testing if a PHY interface
	308	* is SGMII (all variants)
	309	* @phydev: the phy_device struct
	310	*/
	311	static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
	312	{
	313	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
	314	phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
	315	}
	316
a836626c	317	/* PHY UIDs for various PHYs that are referenced in external code */
9b18e519	318	#define PHY_UID_CS4340 0x13e51002
552e7c57	319	#define PHY_UID_CS4223 0x03e57003
a836626c TT	320	#define PHY_UID_TN2020 0x00a19410
a836626c TT	321
5f184715	322	#endif